Hitachi HD64465 User Manual

Windows ce intelligent peripheral controller

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Windows

ADE-602-168B

Rev. 3.0

03/08/01

Hitachi Ltd.

CE Intelligent Peripheral Controller

HD64465

User's Manual

Table of Contents

Summary of Contents for Hitachi HD64465

Page 1 ® Windows CE Intelligent Peripheral Controller HD64465 User’s Manual ADE-602-168B Rev. 3.0 03/08/01 Hitachi Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 Revisions and Additions in this Edition Page Item Description Description of register address <Former Edition> 0x……… / ………h <This Edition> H’……… Description of HD64465BQ Add the description of new product “HD64465BQ” HD64465BP Specifications <Former Edition> Changed PLL used in bypass mode and 48 MHz clock input into UCK terminal <This Edition>...
Page 4 Page Item Description 6.3.2 System Configuration Add the following description Register (SCONFR) Note that the relationship between HW[3:0] and CPU programmed inserted wait states (IWS) is 2 ≤ 1 WS ≤ Description of Bits 11 - 8 1+HW[3:0]. Hence, the CPU default inserted wait states should be 2.
Page 5 Page Item Description (26) Timing control Register Delete the default value (ITMCR) Bits 5 - 0 (2) ECP Address FIFO Register Default value of bits 2 - 0 (ECPAFifo) <Former Edition> 111b <This Edition> 111 (4) Device Control Register (der) Default value of bits 2 - 0 (Address H’1000A004, Mode All) <Former Edition>...
Page 6 HD64465BP Specifications Changed 1. Change in Specifications Item changed Guaranteed value before change Guaranteed value after change PLL stabilization time Not guaranteed 2. Major Influences Due to Above Change in Specifications Preconditions Problems in usage PLL used in bypass mode No problem (no standby time added) Reset signal input after turning power on No problem (no standby time added)
Page 7: Table Of Contents
1.16 Package ..........................4 Section 2 General Description.................5 Section 3 System Block Diagram..............7 Application Circuit ......................7 System Block Diagram......................8 Physical Address Space.....................9 HD64465 Memory Address ....................10 Pin Configuration ......................11 3.5.1 HD64465BP Top View ..................11 3.5.2 HD64465BP Bottom View...................12 3.5.3 HD64465BQ Top View ..................13 3.5.4...
Page 8 Signal Timing Description ....................45 5.4.1 Low Speed Timing ....................45 5.4.2 High Speed Timing ....................47 Internal Bus Data Swap Rules...................49 Internal Peripheral Bus AC Timing Specification.............50 Section 6 Power Management and System Configuration......51 Overview ...........................51 Features ..........................51 Register Description ......................52 6.3.1 System Module Standby Control Register (SMSCR) ..........52 6.3.2...
Page 9 NITR: Interrupt Trigger Mode Register ................86 Section 9 Timer ....................89 Overview ...........................89 9.1.1 Features ........................89 9.1.2 Block Diagram .....................90 9.1.3 Pin Configuration ....................91 9.1.4 Register Configuration ..................91 Timer Register........................92 9.2.1 TCVR1: Timer 1 Constant Value Register............92 9.2.2 TCVR0: Timer 0 Constant Value Register............93 9.2.3 TRVR1: Timer 1 Read Value Register ..............93 9.2.4...
Page 10 10.4.10 PCC1 Card Status Change Interrupt Enable Register (PCC1CSCIER)....125 10.4.11 PCC1 Software Control Register (PCC1SCR) .............127 Section 11 FIR Module ..................129 11.1 Overview ...........................129 11.1.1 Features ........................129 11.1.2 Functional Block Diagram of FIR................130 11.2 FIR Controller Register Description..................132 11.2.1 UART Register of FIR Portion ................132 11.2.2 FIR Controller Register ..................133 11.2.3 Register Description .....................134 11.3 FIR Transmit Operation ....................153...
Page 11 14.2.2 Receive Data Register (RDR) ................185 14.2.3 Control Register (CR) ..................186 14.2.4 Status Register (SR) .....................187 14.2.5 Frequency Select Register ..................189 14.2.6 Command/Status Address Register (CSAR) ............190 14.2.7 Command/Status Data Register (CSDR)..............191 14.2.8 PCM Playback/Record Left Channel (PCML).............192 14.2.9 PCM Playback/Record Right Channel (PCMR) ..........193 14.2.10 Line 1 Data Register (LINE1) ................194 14.2.11 PCM Center Playback/MIC ADC Channel (PCMC) ...........195 14.2.12 PCM Left Surround Channel Data Register (PCMLS) ........196...
Page 12 15.2.5 Transmit Data Buffers (TXDB0,1) ..............236 15.2.6 Transmit Shift Register (TSFTR).................236 15.2.7 Receive Data Buffers (RXDB0,1)................237 15.2.8 Receive Shift Register (RSFTR) ................237 15.3 Data Transfer........................237 15.3.1 Data Transmit.......................237 15.3.2 Data Receive ......................238 15.4 Divider..........................239 15.5 External Chip Control Signal ....................240 15.6 Interrupt..........................241 15.7 How to Use the Special Pin (RLYCNT, RING)..............242 15.7.1 How to use the RLYCNT pin................242...
Page 13 18.1.1 Device Description / Purpose ................259 18.1.2 Reference Information..................259 18.2 Function Description ......................260 18.2.1 System Architecture .....................260 18.2.2 USB Host Controller ....................261 18.2.3 USB Interface.......................293 18.2.4 Power Management....................315 18.2.5 Register/Address Summary..................316 Section 19 A/D Converter .................333 19.1 Overview ...........................333 19.1.1 Features ........................333 19.1.2 Block Diagram .....................334 19.1.3 Input Pins ......................334 19.1.4 Register Configuration ..................335...
Page 14 Tables Table 4-1. HD64465BP Signal Names (by pin numbers in alphabetical order) ......15 Table 4-2. HD64465BQ Signal Names (by pin numbers in alphabetical order)......20 Table 4-3. Pin Descriptions of Test Mode Select.................25 Table 4-4. Pin Descriptions of CPU Interface................25 Table 4-5. Pin Descriptions of PCMCIA 0 Interface ..............27 Table 4-6.
Page 15 Table 13-3. Status Port Register Description ................173 Table 13-4. Control Port Register Description................173 Table 13-5. Bit Map of the ECP Mode Register ................174 Table 13-6. ECP Register Definition ...................175 Table 13-7. ECP Mode Description .....................175 Table 14-1. Pin Function of Serial CODEC Interface Module ............183 Table 14-2.
Page 16 Table 18-28. HcInterruptDisable Register ...................322 Table 18-29. HcHCCA Register ....................323 Table 18-30. HcPeriodCurrentED Register..................323 Table 18-31. HcControlHeadED....................323 Table 18-32. HcControlCurrentED Register................324 Table 18-33. HcBulkHeadED Register ..................324 Table 18-34. HcBulkCurrentED Register ..................324 Table 18-35. HcDoneHead Register ....................325 Table 18-36. HcFmInterval Register....................325 Table 18-37.
Page 17 Figure 5-3. Low-Speed Internal Peripheral Bus Access Timing With TWe Phase......46 Figure 5-4. High-Speed Basic Internal Peripheral Bus Access Timing ........47 Figure 5-5. High-Speed Internal Peripheral Bus Access Timing With TWe Phase .....48 Figure 6-1. AFECK Related Clock Diagram ................59 Figure 6-2.
Page 18 Figure 15-3. HC1 Pin and Control Data Outputs .................240 Figure 15-4. TDEI Output Timing ....................241 Figure 15-5. RDFI Output Timing ....................242 Figure 16-1. H8 Keyboard Controller Interface Block Diagram..........244 Figure 16-2. Keyboard Controller Interface Read Timing ............247 Figure 16-3. Keyboard Controller Interface Write Timing ............247 Figure 17-1.
Page 19 Figure 20-11. UART DTR, RTS Timing ..................358 Figure 20-12. UART Rx Timing....................359 Figure 20-13. Control Signal Delay Time of Parallel Port Timing ..........359 Figure 20-14. EPP Address or Data Write Timing ..............359 Figure 20-15. EPP Address or Data Read Timing ...............360 Figure 20-16.
Page 20: Section 1 Features
Section 1 Features CPU Interface • Supports Hitachi SH-4/SH7709/SH3-DSP family of CPUs with bus speeds from 15 MHz up to 66 MHz. • Supports STANDBY mode when CKIO is stopped. • Memory mapped on area 4 of SH4/SH7709/SH3DSP for internal registers •...
Page 21: Interrupt Controller
Interrupt Controller • Provides an interrupt to SH-4/SH7709/SH3-DSP, which is generated by an internal module interrupt request • Module interrupts can be masked on/off by setting the registers. Power Management • Supports STANDBY mode to stop clock for each module •...
Page 22: Printer Interface
1.10 Printer interface • Supports three access modes, SPP, EPP and ECP(ECP mode only supports PIO mode) • 5V interface to printer • Supports STANDBY mode 1.11 Audio CODEC Interface • Directly interfaced to CS4271/CS4218/AC97 Codec for controlling voice data to the speaker, or from the mic.
Page 23: Usb Host Controller
1.14 USB Host Controller • Supports direct interfaces of 2 USB ports • Supports device bandwidth of 12Mbps or 1.5Mbps • Supports power management mode to protect USB Bus power; and over-current detector to protect USB Bus from abnormal over-current load •...
Page 24: Section 2 General Description
Section 2 General Description The HD64465 is directly connected to SH-4/SH7709/SH3-DSP, and consists of PCMCIA controller, analog front end (AFE) interface, I/O port controller, timer, UART, parallel port interface controller, keyboard interface, CS4218/CS4271/AC97 Codec interface, IrDA controller, USB Host controller, AC97 Codec, 10-bit ADC and power management unit. This chip pairs with SH-4/SH7709/SH3-DSP processors, and features all the key peripheral functions required by the ®...
Page 25 Rev. 3.0, 03/01, page 6 of 390...
Page 26: System Block Diagram
Section 3 System Block Diagram Application Circuit DRAM SH-4/SH7709 Touch Panel UART IrDA Keyboard HD64465 Controller PS/2 PRINTER Keyboard CS4218/ PCMCIA 0 STLC7546 CS4271/ TOUCH Devices KEYBOARD AC97 SPEAKER Rev. 3.0, 03/01, page 7 of 390...
Page 27: System Block Diagram
System Block Diagram HD64465 STLC7546/7550 To Public Line AFE I/F Timer & PMU To KeyBoard SH-4/SH7709/ INTC KBC I/F SH3-DSP To Printer UART Printer I/F To Host PC Clock Gen & DRAM PS/2 CS4271/ To Host PC IrDA CODEC I/F...
Page 28: Physical Address Space
Physical Address Space Ordinary memory / Area 0: H'00000000 Burst ROM Internal I/O Area 1: H'04000000 Ordinary memory / Area 2: H'08000000 SDRAM, DRAM Ordinary memory / Area 3: H'0C000000 SDRAM, DRAM, PSRAM Internal Registers of Intelligent Peripheral Intelligent Peripheral Controller Area 4: H'10000000 Controller Ordinary memory /...
Page 29: Hd64465 Memory Address
HD64465 Memory Address H'10000000- Standby & System Register H'10000FFF H'10001000- Reserved H'10001FFF H'10002000- PCMCIA Register H'10002FFF H'10003000- AFE I/F Register H'10003FFF H'10004000- GPIO Register H'10004FFF H'10005000- INTC Register H'10005FFF H'10006000- Timer Register H'10006FFF H'10007000- IrDA Register H'10007FFF H'10008000- UART Register...
Page 30: Pin Configuration
Pin Configuration 3.5.1 HD64465BP Top View RXD0 AVSS1 UCKE UCK VCC5 ACK# INIT# VCC5 RI0# VCC5 TSMX VCC5 RESET ERR# PPD1 DCD0# RESE TSPX AVCC5 PPD7 SLIN# SLCT KBDATA TPO# TSPY TSMY AVCC4 PPD4 AFD# PPD2 KBCK RESE OVR# TMI# ACPD# AVSS6 AVSS4...
Page 31: Hd64465Bp Bottom View
3.5.2 HD64465BP Bottom View 18 17 RESE MSCK AVCC AVSS RXD0 R10# VCC5 INIT# VCC5 ACK# VCC5 TSMX VCC5 UCKE AVSS1 TMO# RESE DCD0 PPD1 ERR# SLCT SLIN# PPD7 AVCC TSPX PB0/ PB1/ TPO# TMO1# TMO0# RESE KBCK DSR0 DTR0 PPD2 AFD# PPD4...
Page 32: Hd64465Bq Top View
3.5.3 HD64465BQ Top View UCKE AVCC6 DSR0# TSMY PPD4 BUSY STB# PPD1 PEN# AVCC3 RESE PB4 ACPD# TSPY VCC5 ACK# SLCT ERR# PPD0 RTS0# CTS0# TMO# TSMX PPD6 PPD2 RXD0 KBCK OVR# SEL0 CD1# ACCLK TSPX PPD7 VCC5 VCC5 PWM1 VCC1 PCC1 PCC1...
Page 33: Hd64465Bq Bottom View
3.5.4 HD64465BQ Bottom View PPD4 AVCC6 PPD1 STB# BUSY TSMY UCKE DSR0# PEN# RTS0# PPD0 ERR# SLCT ACK# VCC5 TSPY ACPD# RESE AVCC3 CTS0# TMO# KBCK RXD0 PPD2 PPD6 TSMX SEL0 CD1# OVR# PCC1 PCC1 VCC1 PWM1 VCC5 VCS5 PPD7 TSPX ACCLK VS2#...
Page 34: Section 4 Pin Description
Section 4 Pin Description Table 4.1 HD64465BP Signal Names (by pin numbers in alphabetical order) Signal Signal Signal Signal AVSS1 PB1/TMO1# PB4/KBWAKEUP# D1 ACPD#/ACIRQ/ PWE# UCKE PB0/TMO0# AVCC1 AVCC6 USBD1P USBD1M PB5/KBRESUME VCC5 TSPX TSPY AVSS6 TSMX AVCC5 TSMY AVSS4 VCC5 PPD7 AVCC4...
Page 35 Table 4.1 HD64465BP Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Signal Signal Signal SIBDOUT AVCC2 SIBCLK SCLK DOUT SIBDIN TRST MCLKO ACCLK RING OFFHOOK/RLY E11 VCC PCC1VS2# WEA# PCC1A25 E12 USBD2M PCC1VS1# PCC1RESET PCC1A24 E13 USBPEN# PCC1BVD2/SPKR1 PCC1ICIOWRA# L25 PCC1A23 E14 TXD0...
Page 36: Table 4-1. Hd64465Bp Signal Names (By Pin Numbers In Alphabetical Order)
Table 4.1 HD64465BP Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Signal Signal Signal XIOR# RESETPI# XIOW# SH_MODE PCC1A2 PCC1A9 PCC1A1 PCC1A8 PCC1A0 PCC1A7 PCC1D7 VCCB PCC1A17 PCC1D13 PCC1A16 PCC1D5 PCC1D8 PCC1D4 PCC1D0 PCC1D12 VCCB PCC1D3 PCC1A6 PCC1A13 PCC1A5 PCC1A12 KBCS#...
Page 37 Table 4.1 HD64465BP Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Signal Signal Signal IRQ0# AA23 PCC0D15 DRAK1 DREQ1# DRAK0 AA24 PCC0D7 AA25 PCC1A15 AA26 PCC1A14 CS4# RDWR# AC10 WE0# AD10 WE1#/WE# AE10 WE2#/ICIORD# AC11 CE2A# AD11 CE1A#/CS5# AE11 CE2B# AC12 IOIS16# AD12 VCC0SEL1/ AE12 VCC0SEL0/...
Page 38 Table 4.1 HD64465BP Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Signal Signal AF11 CE1B#/CS6# AF21 PCC0ICIORDB# AF12 VCC0VPP1/LATCH AF22 PCC0CE1B# AF13 PCC0VS1# AF23 PCC0A11 RDY#/WAIT# AF14 PCC0BVD2/SPKR0 AF24 VCCA DREQ0# AF15 PCC0D0 AF25 PCC0A7 AF16 VCCA AF26 PCC0A6 AF17 PCC0D11 AF18 PCC0A22 AF19 PCC0A18...
Page 39: Table 4-2. Hd64465Bq Signal Names (By Pin Numbers In Alphabetical Order)
Table 4.2 HD64465BQ Signal Names (by pin numbers in alphabetical order) Signal Pin Signal Signal Signal PB0/TMO0 PB4/KBWAEUP# C1 ACRST# UCKE ACPD#/ACIRQ SIBDIN AVCC6 ACCLK TSMY TSPY USBD1P PB1/TMO1# PPD4 VCC5 TSMX USBD1M BUSY ACK# PPD6 TSPX STB# SLCT PPD7 PDD1 ERR# PPD2...
Page 40 Table 4.2 HD64465BQ Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Pin Signal Signal Signal AFECKE RING AFERST# DOUT TRST# AVCC2 OFFHOOK/RLY AFECK AVSS1 PB5/KBRESUM SIBCLK SIBSYNC AVSS6 SIBDOUT AVCC4 VCC5 VCC3 AVCC1 SLIN# PPD5 AVSS4 AVCC5 INIT# PPD3 AFD# DTR0#...
Page 41 Table 4.2 HD64465BQ Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Signal Signal Signal KBIRQ0 P80LE KBCS# CKIO XIOW# AFEPDN# KBIRQ1 SCLK MCLKO AVSS2 XIOR# RESETPI# VCC3 SH_MODE VCC3 VCC3 PCC1A17 PCC1A1 VCC3 PCC1A25 PCC1D1 PCC1D12 PCC1A5 PCC1CE1A# PCC1A16 PCC1D14 PCC1A2...
Page 42 Table 4.2 HD64465BQ Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Signal Signal Signal DREQ0# VCC3 DREQ1# DRAK1 WE1#/WE# VCC0VPP0 RDWR# CS4# PCC0A19 CE2B# VCC0SEL0/ VCC0SEL1/ DATA CLOCK PCC0REG# PCC0D1 PCC0WP#/ PCC0VS1# IOIS16 PCC1A13 PCC0A21 PCC0D9 PCC0D2 PCC1A9 PCC0RESET PCC0A14 PCC0D11...
Page 43 Table 4.2 HD64465BQ Signal Names (by pin numbers in alphabetical order) [cont’d] Signal Signal Signal Signal IRQ0# DRAK0 RDY#/WAIT# WE2#/ICIORD WE3#/ICIOWR CE2A# CE1A#/CS5# CE1B#/CS6# Y9 IOIS16# PCC0VS2# PCC0CD1# PCC0CD2# VCC0VPP1/ LATCH PCC0WAIT# PCC0BVD2/SPK PCC0BVD1/ PCC0RDY/ STSCHG0# IREQ0# PCC0A22 VCCA PCC0D8 PCC0D0 PCC0A18 PCC0A24...
Page 44: Table 4.3 Pin Descriptions Of Test Mode Select
Table 4.3 Pin Descriptions of Test Mode Select Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description Test Mode Test Mode Enable 0 = Disabled 1 = Enabled Boundary Scan Data Input This pin can be floating when not using. Boundary Scan Data Output Boundary Scan Mode Select.
Page 45 Table 4.4 Pin Descriptions of CPU Interface (cont’d) Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description CS4# Chip select 4 of CPU AC10 WE0# D7-D0 write strobe signal AD10 WE1#/WE# D15-D8 write strobe signal, or PCMCIA write strobe signal AE10 D23-D16 write strobe signal, or PCMCIA I/O WE2#/ICIORD# READ...
Page 46: Table 4.5 Pin Descriptions Of Pcmcia 0 Interface
Table 4.5 Pin Descriptions of PCMCIA 0 Interface Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description PCMCIA 0 (memory and IO) AE17, AD17, Y14, V13, PCC0A25-A0 O Address bus [25:0] of PCMCIA card 0 AC17, AF18, W14, U12, AE18, AD18, P12, Y15, N12, AC18, AF19, U13, V14,...
Page 47 Table 4.5 Pin Descriptions of PCMCIA 0 Interface (cont’d) Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description AB14 PCC0WP#/ Reflects the states of the Write Protect IOIS16# switch on PCCMCIA memory cards. For I/O cards, PCC0WP# is used for the card, which is 16-bit Port (IOIS16#) function.
Page 48: Table 4.6 Pin Descriptions Of Pcmcia 1 Interface
Table 4.6 Pin Descriptions of PCMCIA 1 Interface Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description PCMCIA 1 (memory or IO) L23-26, J15, J17, H18- PCC1A25-A0 O Address bus [25:0] of PCMCIA card 1 20, J18-20, M23-26, N22- K14, K16, P17, 23, AA25-26, R18, N15, U19, Y23-26, W23-...
Page 49 Table 4.6 Pin Descriptions of PCMCIA 1 Interface (cont’d) Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description PCC1BVD1/ The signal indicates the battery condition on STSCHG1# the PCC1 memory card. Both PCC1BVD1 and PCC1BVD2 are in high level when the battery is in good condition.
Page 50: Table 4-7. Pin Descriptions Of Uart 0
Table 4.7 Pin Descriptions of UART 0 Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description UART 0 TXD0 Data output for UART0 RXD0 Data input for UART0 RTS0# Request to Send Output for UART0 CTS0# Clear to Send Input for UART0 DTR0# Data Terminal Ready Output for UART0 DSR0#...
Page 51: Table 4.9 Pin Descriptions Of Printer Port Interface
Table 4.9 Pin Descriptions of Printer Port Interface Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description Printer Interface STB# Printer Strobe. Active low, this signal is the complement of bit 0 of the printer control register. It is used to strobe the printer data into the printer AFD# Printer Autofeed.
Page 52: Table 4.10 Pin Descriptions Of Afe Interface
Table 4.10 Pin Descriptions of AFE Interface Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description AFE Interface DOUT Serial Transmit Data Output Pin (TxD). This signal is connected to AFE module DI. Serial Receive Data Input Pin (RxD). This signal comes from AFE module DOUT. SCLK Shift Clock Input Pin.
Page 53: Table 4.11 Pin Descriptions Of Codec Interface
Table 4.11 Pin Descriptions of CODEC Interface Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description CODEC Interface ACCLK Audio Codec clock ACRST# Audio Codec reset. The pin can also be used to act as PLL3 test output pin at PLL test mode ACPD#/ACIRQ When the connected CODEC is CS4271, the...
Page 54: Table 4.13 Pin Descriptions Of Keyboard Interface
Table 4.13 Pin Descriptions of Keyboard Interface Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description Keyboard Interface KBCS# Keyboard Controller Chip Select XIOW# Keyboard Controller Write Enable XIOR# Keyboard Controller Read Enable KBIRQ0 Keyboard Controller Interrupt 0 KBIRQ1 Keyboard Controller Interrupt 1 Table 4.14 Pin Descriptions of IO Port A Pin No.
Page 55: Table 4.15 Pin Description Of Io Port B
Table 4.15 Pin Description of IO Port B Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description IO Port B (multifunction with TIMER or AFE) Port B bit 7 for GPIO Port B bit 6 for GPIO PB5/ IO/I Multifunction Pin: Port B bit 5 for GPIO/The KBRESUME signal is used to resume standby keyboard controller...
Page 56: Table 4.17 Pin Descriptions Of Io Port D
Table 4.17 Pin Descriptions of IO Port D Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description IO Port D Port D bit 7 for GPIO Port D bit 6 for GPIO Port D bit 5 for GPIO Port D bit 4 for GPIO Port D bit 3 for GPIO Port D bit 2 for GPIO Port D bit 1 for GPIO...
Page 57: Table 4.20 Pin Descriptions Of Ps/2 Interface
Table 4.20 Pin Descriptions of PS/2 Interface Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description PS/2 Interface KBCK PS/2 keyboard clock input/output KBDATA PS/2 keyboard data input/output MSCK PS/2 mouse clock input/output MSDATA PS/2 mouse data input/output Table 4.21 Pin Descriptions of System Reset Interface Pin No.
Page 58: Table 4-24. Pin Descriptions Of Lcd Interface
Table 4.24 Pin Descriptions of No Connected Pins Pin No. Pin No. (HD64465BP) (HD64465BQ) Symbol Description No Connection A24-A26, A20, A19, B20- No Connected pins (total 23 pins). B24-B26, 18, C18, C17, C24-C26, D17, D16, E17- D24-D26, E23, 15, F16, F15 Table 4.25 Pin Descriptions of Power/Ground Pin No.
Page 59 Rev. 3.0, 03/01, page 40 of 390...
Page 60: Section 5 Internal Cpu Interface
CPU INTERFACE Module builds an internal peripheral bus interface on HD64465. This interface provides a bridge between Hitachi SH-3/SH-4 CPU and all peripheral modules in HD64465. This section will explain the functionality and timing of all signals defined in CPU interface module.
Page 61: Cpu Interface Signal Description
CPU Interface Signal Description 5.2.1 System Bus Interface Signals In system bus interface, the configuration of BSC in SH-4/SH-3 needs to be programmed properly. The followings list the bus configuration requirements. 1. Area: Area 4 2. Bus width: Longword (32 bits) size and little endian access. 3.
Page 62: Internal Bus Interface Signals
5.2.2 Internal Bus Interface Signals Signal Name I/O Type Description Internal Module Reset: This signal is module reset of *module. (For example, *RESET# LCDC reset signal is LCDC_RESET#) *STBY Module Standby: This signal is used to control the standby mode for each peripheral module.
Page 63: Function Description
Function Description CPU Interface Module is a bridge between the CPU bus and all peripheral modules in HD64465. This interface module handles the command, address and data transaction between CPU and HD64465 modules. The diagram of Figure 5-1 illustrates how the interface signals are connected.
Page 64: Signal Timing Description
5.4.1 Low Speed Timing HD64465 provides a programmable bit (SLS) in System Configuration Register (SCONFR) to increase the system performance, depending on different bus clock (CKIO) rates. When SLS bit is programmed with 1, the internal bus timing is switched to the basic cycle composed of two wait states.
Page 65: Figure 5.3 Low-Speed Internal Peripheral Bus Access Timing With Twe Phase
Low-Speed Internal Bus Access Timing with TWe phase is shown in the Figure 5-3. The diagram shows the cycles are T1, TWs1, TWs2, TWe and T2 phases. Note that there are two wait states and one external peripheral hardware wait state in command cycle. In this case, the basic command cycle is not enough for peripheral operation, it is responsible for the peripheral module to insert its own wait signal before T2 stage.
Page 66: High Speed Timing
With the programmable bit (SLS) contained in System Configuration Register (SCONFR), the HD64465 is able to increase the system performance, depending on different bus clock (CKIO) rates. When SLS bit is programmed with 0, the internal bus timing is switched to the basic cycle composed of three wait states.
Page 67: Figure 5.5 High-Speed Internal Peripheral Bus Access Timing With Twe Phase
High-Speed Internal Bus Access Timing with TWe phase is shown in the Figure 5-5. The diagram shows the cycles are T1, TWs1, TWs2, TWs3, TWe and T2 phases. Note that there are three wait states and one peripheral hardware wait state in command cycle. In this case, the basic command cycle is insufficient for peripheral operation.
Page 68: Internal Bus Data Swap Rules
Internal Bus Data Swap Rules Internal Bus Data Swap Rules are defined to satisfy the legacy peripheral modules. This is because the data bus width has been changed from 16 bits to 32 bits. For the compliance with these legacy peripheral modules, it is required to establish a data swap mechanism described below: Case 1: Word Access (16 bits) IMADDR[1]=0 CPU Bus...
Page 69: Internal Peripheral Bus Ac Timing Specification
Internal Peripheral Bus AC Timing Specification SH-3 (15MHz) SH-3 (40MHz) SH-4 (66MHz) Symbol Item Unit Address delay time TMSD Module Select delay time TRWD Read Write delay time TRDD Read Strobe delay time TRDS Read Data setup time TRDH Read Data hold time TWED Write Enable delay time TEDD...
Page 70: Section 6 Power Management And System Configuration
Standby mode, Bus gating, Wait states, Peripheral Clock Control, Module Software Reset and Test Mode. Each module in the HD64465 is provided with the STANDBY mode. All peripheral module functions are halted in the STANDBY mode; thereby reducing the power consumption. The Bus gating control is used with STANDBY mode for further power saving capability The Hardware external wait cycle inserted by CPU interface module is an option to extend data read/write cycles.
Page 71: Register Description
Register Description The following table lists all the registers. The unit of the register size and access size is byte. The register size is the actual size of registers. The access size defines the data bus width of host CPU, which is used to access each register.
Page 72 System Module Standby Control Register (SMSCR) [cont’d] Description Default Reserved. PS2ST: PS2 Standby. When this bit is set, the PS2 will enter the standby mode until this bit is cleared. The PS2 will be in normal operation mode after this bit is cleared. This bit is set after reset.
Page 73: System Configuration Register (Sconfr)
6.3.2 System Configuration Register (SCONFR) This register provides a flexible approach for system configuration. The hardware wait insertion control is flexible to control CPU interface command cycle. Parallel Port function select can also be programmed by this register. The detailed functionality, which can be configured, is described below: Address: H'10000002 Bit Name...
Page 74: System Bus Control Register (Sbcr)
System Configuration Register (SCONFR) [cont’d] Description Default USBCKS: USB Host interface Clock Switch. When this bit is cleared, USB Host interface clock will be the clock output from PLL1. When this bit is set, the USB Host interface clock will be the half frequency of CKIO. SCDICKS: Serial Codec Interface Clock Switch.
Page 75 System Bus Control Register (SBCR) [cont’d] Description Default PDOF: Port D Output Floating Control. When this bit is set, the output will be floating. When this bit is cleared, the output floating is disabled. PDIG: Port D Input Gating Control. When this bit is set, the input to port D will be gated to fixed value.
Page 76: System Peripheral Clock Control Register (Spccr)
6.3.4 System Peripheral Clock Control Register (SPCCR) This register provides the function of peripheral clock control for each peripheral module. When the peripheral module is in standby mode, the peripheral clock can be turned off to reduce more power consumption, thanks to the free running of the peripheral clock. To stop the peripheral clock, the peripheral module standby mode must be asserted first.
Page 77 System Peripheral Clock Control Register (SPCCR) [cont’d] Description Default FIRCLK: FIR Controller Clock Control. When this bit is set, the FIR clock will be halted. The FIR clock will run normally after this bit is cleared. Note that this bit can be cleared only Twkst ms later, the UCKOSC bit has already been cleared.
Page 78: Figure 6.1 Afeck Related Clock Diagram
Peripheral Clock Relationship Diagrams shows the working relationship among the clock source and generated peripheral clocks. It also indicates the sequence of turning off one peripheral clock without interfering the other peripheral clocks operation. For example, in Figure 6-1, If the bit AFEOSC is set, then peripheral clocks like AFE_clk and SCDI_clk will be halted because the source clock AFECK is halted.
Page 79: Figure 6.2 Uck Related Clock Diagram
PLL2 Clock Gating USB_clk 48Mhz 12Mhz Control USBCLK UCKOSC Clock Gating FIR_clk Control AFE_cmd_clk FIRCLK Frequency divider Clock x(1/2) 24Mhz Gating PP_clk24 Control Clock PPCLK Gating KBC_clk Control KBCCLK Clock Gating UART_PP_cmd_clk Control UARTCLK & PPCLK Frequency divider Clock x(1/4) 12Mhz (To Figure 1) Gating ADC_clk...
Page 80: System Peripheral S/W Reset Control Register (Spsrcr)
6.3.5 System Peripheral S/W Reset Control Register (SPSRCR) The software reset of each peripheral module is an option when the peripheral module encounters functional failures after clearing the STANDBY mode of the module. These software reset bits need the clock from UCK oscillator to count the reset period, which means that the UCKOSC bit needs to be cleared first before setting these reset bits.
Page 81 System Peripheral S/W Reset Control Register (SPSRCR) [cont’d] Description Default PPSRT: Parallel Port Controller Software Reset. When this bit is set, the parallel port controller will be reset. This reset is equivalent to hardware reset. All the parallel port registers are set to the reset default values. Note that the software reset bit is self- clearing.
Page 82: System Pll Control Register (Spllcr)
6.3.6 System PLL Control Register (SPLLCR) This register provides the PLL control options. Address: H'1000000A Bit Name Initial Value Bit Name PLL2SB PLL1SB - PLL2BP PLL1BP Initial Value Description Default 15 - 6 Reserved. PLL2SB: PLL2 Standby control. When this bit is set, the PLL2 standby mode is enabled. When this bit is cleared, the PLL2 standby mode is disabled.
Page 83: System Revision Register (Srr)
6.3.7 System Revision Register (SRR) This register records the revision number of the controller, which is read only. The revision number is presented with mj.mi. The mj[7:0] stands for the major change number and its value is the content of the register’s high byte. The mi[7:0] stands for the minor change number, and its value is the content of the register’s low byte.
Page 84: System Hardware Reset Timing
HD64465 provides the system hardware reset function to control SH-4/SH-3 CPU power-on reset or manual reset. In Figure 6-3, it shows that two input signals on HD64465, RESETMI# and RESETPI#, which control the manual reset and power-on reset respectively. The other signals, RESETPO# and RESETMO#, are the output signals connected to SH-4/SH-3 CPU for power-on reset and manual reset.
Page 85: Manual Reset Output
When RESETMI# is asserted, it means the manual reset is occurred. The manual reset signal from HD64465, RESETMO#, is connected to CPU manual reset input. For SH-4 and SH-3 CPU, the manual reset mechanism is different. Figure 6-5 shows the manual reset timing for SH-4 CPU and Figure 6-6 shows the manual reset timing for SH-3 CPU.
Page 86: Section 7 General Purpose I/O Port
Section 7 General Purpose I/O Port Overview The HD64465 incorporates five general purpose 8-bit I/O ports (Port A, Port B , Port C, Port D and Port E ). As shown in the Table 7-1 below, the port pins are multiplexed with other functions, which are controlled by Port Control Registers (GPxCR x: A,B,C,D,E).
Page 87 Table 7.1 The List of I/O Port Pin Function Configurations(cont’d) Port Function 1 Function 2 PB7 I/O (port) Reserved PB6 I/O (port) Reserved PB5 I/O (port) KBC RESUME# (KBC) PB4 I/O (port) KBC WAKEUP# (KBC) PB3 I/O (port) Reserved PB2 I/O (port) Reserved PB1 I/O (port) TMO1# (Timer)
Page 88: Register Configuration
Register Configuration Each I/O Port consists of four registers: Port Control Register, Port Data Register, Interrupt Control Register and Interrupt Status Register. Table 7-2 below summarizes the port address configuration of each register. Table 7.2 The List of Register Configurations Initial Register Access...
Page 89: Register Descriptions
Register Descriptions All ports are 8-bit input/output ports with the pin configuration shown in Figure 7-1 below. Each pin contains an input pull-up MOS, which is controlled by its I/O Control Register (GPxCR x:A,B,C,D,E). Port X ⇔ (input / output) / Function 2 ⇔...
Page 90 GPCDR -- Address: H'10004014 Bit Name PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT Initial Value GPDDR -- Address: H'10004016 Bit Name PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT Initial Value GPEDR -- Address: H'10004018 Bit Name PE7DT PE6DT PE5DT PE4DT PE3DT...
Page 91: Port Control Register
7.3.2 Port Control Register GPACR -- Address: H'10004000 Bit Name PA7MD1 PA7MD0 PA6MD1 PA6MD0 PA5MD1 PA5MD0 PA4MD1 PA4MD0 Initial Value Bit Name PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial Value GPBCR -- Address: H'10004002 Bit Name PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial Value Bit Name PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0...
Page 92: Table 7-3. Control Bits Definition Of The Port X Control Register And Its Relevant Read/Write Operation Of Port Data Register
GPDCR -- Address: H'10004006 Bit Name PD7MD1 PD7MD0 PD6MD1 PD6MD0 PD5MD1 PD5MD0 PD4MD1 PD4MD0 Initial Value Bit Name PD3MD1 PD3MD0 PD2MD1 PD2MD0 PD1MD1 PD1MD0 PD0MD1 PB0MD0 Initial Value GPECR -- Address: H'10004008 Bit Name PE7MD1 PE7MD0 PE6MD1 PE6MD0 PE5MD1 PE5MD0 PE4MD1 PE4MD0 Initial Value Bit Name PE3MD1 PE3MD0 PE2MD1 PE2MD0 PE1MD1 PE1MD0 PE0MD1 PE0MD0...
Page 93: Port Interrupt Control Register
7.3.3 Port Interrupt Control Register This register is used to enable or disable to generate the interrupt request when an interrupt event is triggered on each I/O port pin. An interrupt request is generated when an interrupt event is triggered and its corresponding register bit is set to “1”. But the Interrupt request will not be generated if its corresponding control register bit is “0,”...
Page 94 GPCICR -- Address: H'10004024 (cont’d) Bit Name PC7IM PC6IM PC5IM PC4IM PC3IM PC2IM PC1IM PC0IM Initial Value GPDICR -- Address: H'10004026 Bit Name PD7TS PD6TS PD5TS PD4TS PD3TS PD2TS PD1TS PD0TS Initial Value Bit Name PD7IM PD6IM PD5IM PD4IM PD3IM PD2IM PD1IM PD0IM...
Page 95: Port Interrupt Status Register
7.3.4 Port Interrupt Status Register GPAISR -- Address: H'10004040 Bit Name PA7ISR PA6ISR PA5ISR PA4ISR PA3ISR PA2ISR PA1ISR PA0ISR Initial Value GPBISR -- Address: H'10004042 Bit Name PB7ISR PB6ISR PB5ISR PB4ISR PB3ISR PB2ISR PB1ISR PB0ISR Initial Value GPCISR -- Address: H'10004044 Bit Name PC7ISR PC6ISR PC5ISR PC4ISR PC3ISR PC2ISR PC1ISR PC0ISR Initial Value...
Page 96 GPEISR -- Address: H'10004048 Bit Name PE7ISR PE6ISR PE5ISR PE4ISR PE3ISR PE2ISR PE1ISR PE0ISR Initial Value When an interrupt event occurs on an I/O port pin and its corresponding interrupt control register (GPXICR) bit is set to “1” (enabled), the corresponding interrupt status bit is read as “1”. Note that interrupt output is kept active till writing ‘1’...
Page 97 Rev. 3.0, 03/01, page 78 of 390...
Page 98: Interrupt Controller (Intc)
Section 8 Interrupt Controller (INTC) Overview The Intelligent Peripheral Controller interrupts are issued from the modules of PS/2, PCMCIA, AFE, GPIO port, Timer, Keyboard Controller, IrDA , UART, PP, SCDI, USB, and ADC. The controller contains a register for the interrupt request status issued from each module. After SH-4/SH7709 detects the interrupt, it reads the interrupt request register to see which module generates the interrupt, and then reads the interrupt request register in each module.
Page 99: Block Diagram
8.1.2 Block Diagram (Interrupt Request) PS/2 (Interrupt Request) PCMCIA (Interrupt Request) (Interrupt Request) GPIO Port (Interrupt Request) Timer (Interrupt Request) IRQ0# NITR NIRR (Interrupt Request) IrDA (Interrupt Request) UART (Interrupt Request) (Interrupt Request) SCDI (Interrupt Request) (Interrupt Request) NIMR External Interface Figure 8.1 Block Diagram of the Interrupt Controller 8.1.3...
Page 100: Interrupt Sources
Interrupt Sources 8.2.1 On-Chip Module Interrupt Interrupt sources are derived from on-chip peripheral module Interrupts. Each interrupt provides a mask bit in each module listed below: • PS/2 Keyboard • PS/2 Mouse • PCMCIA Controller (PCC) • Analog Front End (AFE) Interface •...
Page 101: Nirr: Interrupt Request Register
NIRR: Interrupt Request Register The NIRR, a 16-bit register, indicates interrupt requests from the internal modules of PS/2, PCMCIA, AFE, GPIO, Timer, KBC, IrDA, UART, PP, SCDI, USB, and ADC. Address: H'10005000 Bit Name PS2KBR PCC0R PCC1R AFER GPIOR TMU0R TMU1R KBCR Initial Value...
Page 102 NIRR: Interrupt Request Register [cont’d] Description Default TIMER 1 interrupt request status (TMU1R) This bit represents TIMER 1 interrupt request status. 1: The interrupt request is generated from TIMER 1. 0: No interrupt requests are generated from TIMER 1. KBC interrupt request status (KBCR) This bit represents KBC interrupt request status.
Page 103: Nimr: Interrupt Mask Register
NIMR: Interrupt Mask Register The NIMR, a 16-bit register, serves to mask interrupt requests from the internal modules of PS/2, PCMCIA, AFE, GPIO, Timer, KBC, IrDA, UART, PP, SCDI, USB, and ADC. This register is initialized to H’0000 at RESET. Address: H'10005002 Bit Name PS2KBM PCC0M...
Page 104 NIMR: Interrupt Mask Register [cont’d] Description Default TIMER 0 Interrupt Mask Control (TMU0M) This bit is used to control the mask option for TIMER 0 interrupt request. 1: The interrupt request from TIMER 0 is masked. 0: The interrupt request from TIMER 0 is not masked. Timer 1 Interrupt Mask Control (TMU1M) This bit is used to control the mask option for TIMER 1 interrupt request.
Page 105: Nitr: Interrupt Trigger Mode Register
NIMR: Interrupt Mask Register [cont’d] Description Default ADC Interrupt Mask Control (ADCM) This bit is used to control the mask option for ADC interrupt request. 1: The interrupt request from ADC is masked. 0: The interrupt request from ADC is not masked. NITR: Interrupt Trigger Mode Register The NITR, a 16-bit register, determines the trigger mode of the interrupt requests from the internal modules of PS/2, PCMCIA, AFE, GPIO, Timer, KBC, IrDA, UART, PP, SCDI, USB and ADC.
Page 106 NITR: Interrupt Trigger Mode Register [cont’d] Description Default AFE Interrupt Trigger Mode (AFET) This bit is used to set the trigger mode for AFE interrupt request. 1: The interrupt request from AFE is in edge trigger mode. 0: The interrupt request from AFE is in level trigger mode. GPIO Interrupt Trigger Mode (GPIOT) This bit is used to set the trigger mode for GPIO interrupt request.
Page 107 NITR: Interrupt Trigger Mode Register [cont’d] Description Default SCDI Interrupt Trigger Mode (SCDIT) This bit is used to set the trigger mode for SCDI interrupt request. 1: The interrupt request from SCDI is in edge trigger mode. 0: The interrupt request from SCDI is in level trigger mode. USB Interrupt Trigger Mode (USBT) This bit is used to set the trigger mode for USB interrupt request.
Page 108: Section 9 Timer
Section 9 Timer Overview The timer in the HD64465 provides two channels of programmable counters. Interrupt requests are generated whenever the counter reaches zero. In order to reduce power consumption, clock pre- scaled circuit and STANDBY mode are added. Two-channel pulse width modulation (PWM) functions are also provided for VR control of LCD.
Page 109: Block Diagram
9.1.2 Block Diagram DREQ1# TMO1# Prescale 16-bit TMO0# CKIO 1, 1/4, 1/8, 1/16 counter timer1r (Interrupt request) timer0r TCVR1 TCR1 TCVR0 TCR0 CPU BUS TRVR1 Interface TRVR0 TIRR TIDR PWM1 Clock Scales 16-bit CKIO PWM0 counter 1,1/2,1/4,1/8,1/16,1/32 PWM1LPC PWM1CS CPU BUS PWM1HPC PWM0CS Interface...
Page 110: Pin Configuration
9.1.3 Pin Configuration Name Abbr. Description Timer 1 output TMO1# Multiplexed with PB1/TMO1#. Timer output signal is enabled by bit 3 ETMO1 in Timer 1 Control register TCR1. Timer 0 output TMO0# Multiplexed with PB0/TMO0#. Timer output signal is enabled by bit 3 ETMO0 in Timer 0 Control register TCR0.
Page 111: Timer Register
Timer Register 9.2.1 TCVR1: Timer 1 Constant Value Register The TCVR1, a 16-bit register, provides the counter constant for timer 1. The register is initialized to H’ FFFF at RESET. Address: H'10006000 Bit Name Initial Value Bit Name Initial Value Description Default 15 - 0...
Page 112: Tcvr0: Timer 0 Constant Value Register
9.2.2 TCVR0: Timer 0 Constant Value Register The TCVR0, a 16-bit register, provides the counter constant for the timer 0. The register is initialized to H’FFFF at RESET. Address: H'10006002 Bit Name Initial Value Bit Name Initial Value Description Default 15 - 0 These bits are set as the timer 0 constant value.
Page 113: Trvr0: Timer 0 Read Value Register
9.2.4 TRVR0: Timer 0 Read Value Register The TRVR0, a 16-bit register, serves to read the counting value in timer 0. This register would be reset to H’0002 when the timer is stopped. Address: H'10006006 Bit Name Initial Value Bit Name Initial Value Description Default...
Page 114: Tcr1: Timer 1 Control Register
9.2.5 TCR1: Timer 1 Control Register The TCR 1, a 16-bit register, is used to control the timer 1. Address: H'10006008 Bit Name reserved reserved reserved reserved reserved reserved reserved reserved Initial Value Bit Name reserved reserved reserved EDMA ETMO1 PST11 PST10 T1STP...
Page 115: Tcr0: Timer 0 Control Register
9.2.6 TCR0: Timer 0 Control Register The TCR 0, a 16-bit register, is used to control the timer 0. Address: H'1000600A Bit Name reserved reserved reserved reserved reserved reserved reserved reserved Initial Value Bit Name reserved reserved reserved EADT ETMO0 PST01 PST00 T0STP...
Page 116: Tirr: Timer Interrupt Request Register
9.2.7 TIRR: Timer Interrupt Request Register The TIRR, a 16-bit register, reflects the interrupt status from the timer 1 and the timer 0. Address: H'1000600C Bit Name reserved reserved reserved reserved reserved reserved reserved reserved Initial Value Bit Name reserved reserved reserved reserved reserved reserved TMU1R TMU0R Initial Value Description...
Page 117: Tidr*: Timer Interrupt Disable Register
9.2.8 TIDR*: Timer Interrupt Disable Register The TIDR, a 16-bit register, is used to disable the interrupt request from the timer 1 and the timer Address: H'1000600E Bit Name reserved reserved reserved reserved reserved reserved reserved reserved Initial Value Bit Name reserved reserved reserved reserved reserved reserved TMU1D TMU0D Initial Value...
Page 118: Pwm1Cs: Pwm 1 Clock Scale Register
9.2.9 PWM1CS: PWM 1 Clock Scale Register The PWM1CS, a 16-bit register, is used to control the clock scale for PWM 1 width counting. The register is initialized to H’ 0000 at RESET. Address: H'10006010 Bit Name Initial Value Bit Name P1CS5 P1CS4 P1CS3...
Page 119: Pwm1Lpc: Pwm 1 Low Pulse Width Counter Register
9.2.10 PWM1LPC: PWM 1 Low Pulse Width Counter Register The PWM1LPC, a 16-bit register, defines the low pulse width of PWM. The register is initialized to H’ FFFF at RESET. Address: H'10006012 Bit Name P1LC15 P1LC14 P1LC13 P1LC12 P1LC11 P1LC10 P1LC9 P1LC8 Initial Value Bit Name...
Page 120: Pwm1Hpc: Pwm 1 High Pulse Width Counter Register
9.2.11 PWM1HPC: PWM 1 High Pulse Width Counter Register The PWM1HPC, a 16-bit register, defines the high pulse width of PWM 1. The register is initialized to H’ FFFF at RESET. Address: H'10006014 Bit Name P1HC15 P1HC14 P1HC13 P1HC12 P1HC11 P1HC10 P1HC9 P1HC8 Initial Value Bit Name...
Page 121: Pwm0Cs: Pwm 0 Clock Scale Register
9.2.12 PWM0CS: PWM 0 Clock Scale Register The PWM0CS, a 16-bit register, is used to control the clock scale for PWM 0 width counting. The register is initialized to H’ 0000 at RESET. Address: H'10006018 Bit Name Initial Value Bit Name P0CS5 P0CS4 P0CS3...
Page 122: Pwm0Lpc: Pwm 0 Low Pulse Width Counter Register
9.2.13 PWM0LPC: PWM 0 Low Pulse Width Counter Register The PWM0LPC, a 16-bit register, defines the low pulse width of PWM 0. The register is initialized to H’ FFFF at RESET. Address: H'1000601A Bit Name P0LC15 P0LC14 P0LC13 P0LC12 P0LC11 P0LC10 P0LC9 P0LC8 Initial Value Bit Name...
Page 123: Pwm0Hpc: Pwm 0 High Pulse Width Counter Register
9.2.14 PWM0HPC: PWM 0 High Pulse Width Counter Register The PWM0HPC, a 16-bit register, defines the high pulse width of PWM 0. The register is initialized to H’ FFFF at RESET. Address: H'1000601C Bit Name P0HC15 P0HC14 P0HC13 P0HC12 P0HC11 P0HC10 P0HC9 P0HC8 Initial Value Bit Name...
Page 124: Figure 9-2. Interrupt Request Timer1/0R Timing Diagram In Case Prescale *1
CKIO timer1/0_clk TCR1/0 TIRR ID[15:0] h'07 TMU1/0M RD/WR MWE1#/0# timercs# TRVR 1/0 timer1/0r Figure 9.2 Interrupt Request Timer1/0r Timing Diagram in Case Prescale *1, Timer1/0_clk=CKIO CKIO timer1/0_clk TIRR ID[15:0] TMU1/0M RD/WR MWE1#/0# timercs# TRVR 1/0 timer1/0r Figure 9.3 Interrupt Request Timer1/0r Timing Diagram in Case Prescale*1/4, Timer1/0_clk = CKIO/4 Rev.
Page 125: A/D Trigger Signal Adtrig
CKIO timer1/0_clk TIRR ID[15:0] TMU1/0M RD/WR MWE1#/0# timercs# TRVR 1/0 timer1/0r Figure 9.4 Interrupt Request Timer1/0r Timing Diagram in Case Prescale*1/8, Timer1/0_clk = CKIO/8 CKIO timer1/0_clk TIRR ID[15:0] TMU1/0M RD/WR MWE1#/0# timercs# TRVR 1/0 timer1/0r Figure 9.5 Interrupt Request Timer1/0r Timing Diagram in Case Prescale*1/16, Timer1/0_clk = CKIO/16 A/D Trigger Signal ADTRIG# The A/D trigger signal ADTRIG# is enabled by the control bit EADT in TCR0.
Page 126: Figure 9.6 A/D Trigger Signal Adtrig# Timing Diagram In Case Prescale 1, Timer0_Clk=Ckio
CKIO timer1/0_clk TRVR1/0 n-10 n-11 n-12 n-13 n-14 n-15 ADTRIG# Figure 9.6 A/D Trigger Signal ADTRIG# Timing Diagram in Case Prescale 1, Timer0_clk=CKIO CKIO timer1/0_clk TRVR1/0 ADTRIG# Figure 9.7 A/D Trigger Signal ADTRIG# Timing Diagram in Case Prescale 1/4, Timer0_clk=CKIO/4 CKIO timer1/0_clk TRVR1/0...
Page 127: Dma Request Enable Function
DMA Request Enable Function The Timer supports the DMA Request Enable Function using DREQ1# by setting the control bit EDMA in TCR1. When the DMA Request Function is enabled, the DMA cycle will operate in Burst Mode and perform the edge detection on DREQ1#; that is to say, the timer will issue a DMA request periodically by pulling the DREQ1# to low, and by releasing the DREQ1# when the first cycle DRAK1 output is detected.
Page 128: Section 10 Pc Card Controller (Pcc)
Section 10 PC Card Controller (PCC) 10.1 Overview The PC Card Controller (PCC) controls the internal buffers, interrupts, and PCMCIA-defined ports of the PC card interfaces, which should be connected to the Intelligent Peripheral Controller (IPC). The PCC enables two slots of the PC cards that are compliant with the specifications PCMCIA Rev.
Page 129: Register Description
Table 10.1 PC Card Controller Registers [cont’d] Read/ Initial Register Name Symbol Write Value Address Register Size PCC1 interface status register PCC1ISR H’10002010 8 bits (16 bits) PCC1 general control register PCC1GCR H’00 H’10002012 8 bits (16 bits) PCC1 card status change register PCC1CSCR H’00 H’10002014 8 bits (16 bits)
Page 130 PCC0 Interface Status Register (PCC0ISR) [cont’d] Description Default PCC0VS2# Pin Status (P0VS2) If this bit is high: Indicates that the value of pin PCC0VS2# of the PC card connected to PCC0 is 1. If this bit is low: Indicates that the value of pin PCC0VS2# of the PC card connected to PCC0 is 0.
Page 131: Pcc0 General Control Register (Pcc0Gcr)
10.4.2 PCC0 General Control Register (PCC0GCR) Bit Name P0DRV P0PCCR P0PCCT P0VCC0 P0MMOD P0PA25 P0PA24 P0REG Initial Value The PCC0 general control register (PCC0GCR) is an 8-bit READ/WRITE register. It controls reset, address pins PCC0A25 and PCC0A24, and pin PCC0REG, and sets the PC card type for the PC card connected to PCC0.
Page 132 PCC0 General Control Register (PCC0GCR) [cont’d] Description Default PCC0 Memory Mode (P0MMOD) If this bit is high: (continuous 16MB area mode) A24 Bit2 Bit1 Bit0 PCMCIA Access Range don’t care 16MB Attribute memory Area Memory Bank Select 16MB of 64MB Common memory Area don’t care don’t care 16-MB I/O Space...
Page 133: Pcc0 Card Status Change Register (Pcc0Cscr)
10.4.3 PCC0 Card Status Change Register (PCC0CSCR) Bit Name P0SCDI P0IREQ P0SC P0CDC P0RC P0BW P0BD PSW_SEL Initial Value The PCC0 Card Status Change Register (PCC0CSCR) is an 8-bit READ/WRITE register. PCC0CSCR is set to 1 by each interrupt factor of the PC card connected to PCC0 (only bits 7 and 6 can be set to 1 as required).
Page 134 PCC0 Card Status Change Register (PCC0CSCR) [cont’d] Description Default PCC0 STSCHG Change (P0SC) If this bit is high: Indicates that the STSCHG pin in the PC card is changed from 1 to 0 when the PC card is in the I/O and Memory card interface. If this bit is low: Indicates that the value of pin STSCHG on the PC card remains unchanged when the PC card is in the I/O and Memory card interface.
Page 135: Pcc0 Card Status Change Interrupt Enable Register (Pcc0Cscier)
10.4.4 PCC0 Card Status Change Interrupt Enable Register (PCC0CSCIER) Bit Name P0CRE P0SCE P0CDE P0RE P0BWE P0BDE P0IREQE1 P0IREQE0 Initial Value The PCC0 card status change interrupt enable register (PCC0CSCIER) is an 8-bit READ and WRITE register. PCC0CSCIER is capable of setting a valid or invalid interrupt for each interrupt factor of the PC card connected to PCC0.
Page 136 PCC0 Card Status Change Interrupt Enable Register (PCC0CSCIER) [cont’d] Description Default PCC0 Card Detect Change Interrupt Enable (P0CDE) If this bit is high: An interrupt occurs for the PC card connected to PCC0 when the values of the PCC0CD1# and PCC0CD2# pins are changed. If this bit is low: No interrupt occurs for the PC card connected to PCC0 regardless of the values of the PCC0CD1# and PCC0CD2# pins.
Page 137: Pcc0 Software Control Register (Pcc0Scr)
10.4.5 PCC0 Software Control Register (PCC0SCR) 6+'1 Bit Name P0VPP1 P0VPP0 P0VCC1 P0SWP Initial Value The PCC0 Software Control Register (PCC0CSCR) is an 8-bit READ/WRITE register. The way it controls pin VCC0SEL1 resembles to that of pin P0VCC0 in the PCC0GCR register does to pin VCC0SEL0.
Page 138: Pcc Serial Power Switch Control Register (Pccpsr)
10.4.6 PCC Serial Power Switch Control Register (PCCPSR) %B9&&8 %B9&&6 B_VPP_ $B9&&6 $B9&&8 A_VPP_ Bit Name B_VPP_ A_VPP_ Initial Value The PCC0PSR Serial Power Switch Control Register (P0PSR), an 8-bit READ/WRITE register, serves as the bit0-bit7 of the serial power switch TPS2206. P0PSR is initialized at power-up reset, and holds its value at software reset or in software-based STANDBY mode.
Page 139 PCC1 Interface Status Register (PCC1ISR) [cont’d] Description Default PCC1 Ready/IREQ1 Pin Status (P1READY/IREQ1) If this bit is high: Indicates that the value of pin PCC1RDY is 1 when the PC card connected to PCC1 is the IC memory card interface. Indicates that the value of pin IREQ is 1 when the I/O and Memory card interface is the PC card connected to PCC1.
Page 140: Pcc1 General Control Register (Pcc1Gcr)
PCC1 Interface Status Register (PCC1ISR) [cont’d] Description Default I/O and Card Interface 1: Indicates that the value of pin SPKR on the PC card connected to PCC1 is 1. 0: Indicates that the value of pin SPKR on the PC card connected to PCC1 is 0. 1: Indicates that the value of pin STSCHG in the PC card connected to PCC1 is 1.
Page 141 PCC1 General Control Register (PCC1GCR) [cont’d] Description Default PCC1 Memory Mode (P1MMOD) If this bit is high: (continuous 16MB area mode) bit 2 bit 1 bit 0 PCMCIA Access Range don’t care don’t care 16MB Attribute memory Area Memory Bank Select don’t care 16MB of 64MB Common memory Area don’t care don’t care 16-MB I/O Space If this bit is low: (continuous 32MB area mode)
Page 142: Pcc1 Card Status Change Register (Pcc1Cscr)
10.4.9 PCC1 Card Status Change Register (PCC1CSCR) Bit Name P1SCDI - P1IREQ P1SC P1CDC P1RC P1BW P1BD Initial Value The PCC1 Card Status Change Register (PCC1CSCR) is an 8-bit READ/WRITE register. PCC1CSCR is set to 1 by each interrupt factor of the PC card connected to PCC1 (only bit 7 and 6 can be set to 1 as required).
Page 143 PCC1 Card Status Change Register (PCC1CSCR) [cont’d] Description Default PCC1 Card Detect Change (P1CDC) If this bit is high: Indicates that CD1 and CD2 in the PC card are changed. If this bit is low: Indicates that CD1 and CD2 in the PC card are not changed. (Initial value) Write 0 to bit 3 in order to reset this bit to 0.
Page 144: Pcc1 Card Status Change Interrupt Enable Register (Pcc1Cscier)
10.4.10 PCC1 Card Status Change Interrupt Enable Register (PCC1CSCIER) Bit Name P1CRE P1SCE P1CDE P1RE P1BWE P1BDE P1IREQE1 P1IREQE0 Initial Value The PCC1 card status change interrupt enable register (PCC1CSCIER) is an 8-bit READ and WRITE register. PCC1CSCIER is capable of setting a valid or invalid interrupt for each interrupt factor of the PC card connected to PCC1.
Page 145 PCC1 Card Status Change Interrupt Enable Register (PCC1CSCIER) [cont’d] Description Default PCC1 Ready Change Interrupt Enable (P1RE) If this bit is high: An interrupt occurs for the PC card connected to PCC1 when the value of pin PCC1RDY is changed from 0 to 1. If this bit is low: No interrupt occurs for the PC card connected to PCC1 regardless of the value of pin PCC1RDY.
Page 146: Pcc1 Software Control Register (Pcc1Scr)
10.4.11 PCC1 Software Control Register (PCC1SCR) Bit Name P1VPP1 P1VPP0 P1VCC1 P1SWP Initial Value The PCC1 Software Control Register (PCC1CSCR) is an 8-bit READ/WRITE register. The way it controls pin VCC1SEL1 resembles to that of pin P1VCC1 in the PCC1GCR register does to pin VCC1SEL0.
Page 147 Rev. 3.0, 03/01, page 128 of 390...
Page 148: Section 11 Fir Module
Section 11 FIR Module 11.1 Overview The FIR module is fully IrDA1.1 compliant, and supports the serial infrared link at 288Kbit, 576Kbit, 1.152Mbit and 4Mbit. The three lower speeds are complied with Synchronous Data Link Control (SDLC) protocol, a packet with start/stop flags delimiting a data packet encoded by zero- insertion.
Page 149: Functional Block Diagram Of Fir
11.1.2 Functional Block Diagram of FIR Internal Bus Interface FIR TX/RV FIFO FIR UART related register (16550 compatible) HP-SIR / Sharp-ASK FIR MODEM MODEM FIR Flow SIR Flow Figure 11.1 Functional Block Diagram of FIR The FIR module contains five blocks. The Internal Bus Interface block implements the logic between FIR core and internal bus.
Page 150 To use SIR or ASK transfer protocol, the data flow is from host to UART, and to HP-SIR MODEM: 1. Host sets SIR Register (ISIRR) to HP-SIR MODEM (see FIR Controller registers description in section 11.2.2 on the next page.) 2.
Page 151: Fir Controller Register Description
11.2 FIR Controller Register Description 11.2.1 UART Register of FIR Portion The register has the same definition as that of UART, except that the address spaces are different. Register DLAB* Address READ WRITE Data H'10007000 IrRBR (Receiver Buffer Register) IrTBR (Transmitter Buffer Register) Control H'10007002 IrIER (Interrupt Enable Register)
Page 152: Fir Controller Register
11.2.2 FIR Controller Register Table 11.1 Summary of FIR Controller Registers Bank Address READ WRITE H'10007100 IMSTCR (Master Control Register) IMSTCR (Master Control Register) H'10007102 IMSTSR (Master Status Register) IMISCR (Miscellaneous Control Register) H'10007104 IRFR (Rx FIFO Register) ITFR (Tx FIFO Register) H'10007106 ITC1R (Tx Control 1 Register) ITC1R (Tx Control 1 Register)
Page 153: Register Description
11.2.3 Register Description (1) Master Control Register (IMSTR) Address: H'10007100 (Bank 0, 1, 2, Read/ Write) Bit Name TXEN RXEN BKSEL4 BKSEL3 BKSEL2 BKSEL1 BKSEL0 Initial Value Description Default FIR Interrupt Enable (IEN) Setting this bit to 1 enables all FIR Controller interrupts. Transmitter Enable (TXEN) Setting this bit to 1 enables the transmitter logic in the FIR Controller.
Page 154 (2) Master Status Register (IMSTSR) Address: H'10007102 (Bank 0, Read) Bit Name IID2 IID1 IID0 Initial Value Description Default Reserved Timer Interrupt (TMI) When set to 1, indicates a timer interrupt is pending. Transmitter Interrupt (TXI) When set to 1, indicates a transmitter interrupt is pending. Receiver Interrupt (RXI) When set to 1, indicates a receiver interrupt is pending.
Page 155 (3) Miscellaneous Control Register (IMISCR) Address: H'10007102 (Bank 0, Write) Bit Name DCS1 DCS0 ILOOP Initial Value Description Default 7 - 6 DMA Channel Select (DCS[1:0]) DMA Channel Select. Specify DMA channel usage. DMA Channel Select No DMA DMA Channel for Receive DMA Channel for Transmit Reserved Reserved...
Page 156 (5) Tx FIFO Register (ITFR) Address: H'10007104 (Bank 0, Write) Bit Name Initial Value Description Default 7 - 0 Transmit Data: Used to write transmit packet data to Tx FIFO. (6) Tx Control 1 Register (ITC1R) Address: H'10007106 (Bank 0, Read/ Write) Bit Name TFRIEN TFUIEN TFTL ADRTS...
Page 157 Tx Control 1 Register (ITC1R) [cont’d] Description Default Automatic Clear EOM Control (ACEOM) Setting this bit to ‘1’ causes the EOM bit to be cleared automatically when the Tx Status Register is read. Setting this bit to ‘0’ causes the EOM bit to remain set after the Tx Status Register has been read.
Page 158 (7) Tx Control 2 Register (ITC2R) Address: H'10007108 (Bank 0, Read/ Write) Bit Name ACRCG SIP NSFP EEIL3 EEIL2 EEIL1 EEIL0 Initial Value Description Default Send Break (SB) Send Break: Setting this bit to ‘1’ causes the transmitter to transmit zeros. Automatic CRC Generation (ACRCG) Setting this bit to ‘1’...
Page 159 (8) Tx Status Register (ITSR) Address: H'1000710A (Bank 0, Read) Bit Name TFUR TFRDY EEOM Initial Value Description Default 7 - 4 Reserved Tx FIFO Underrun (TFUR) When set to ‘1,’ indicates Tx FIFO ran out of data before the transmitter could finish transmitting all the data (i.e.
Page 160 (9) Rx Control Register (IRCR) Address: H'1000710C (Bank 0, Read/ Write) Bit Name RFTL ACRCC RADM1 RADM0 SYNIEN - RFRIEN SCIEN Initial Value Description Default Rx FIFO Threshold Level (RFTL) Setting this bit to ‘1’ sets the Rx FIFO threshold to half-full (more than 8 bytes of Receive data are still remaining in FIFO).
Page 161 (10) Rx Status Register (IRSR) Address: H'1000710E (Bank 0, Read) Bit Name ABORT CRCER RFOVF RFEM SYNC Initial Value Description Default Abort Detect (ABORT) When set to ‘1’, indicates abort sequence detected in the receive data stream of current packet. In 1Mbit mode, the abort sequence is characterized by seven or more consecutive 1 in the data stream.
Page 162 (11) Reset Command Register (IRSTCR) Address: H'1000710E (Bank 0, Write) Bit Name RSTC3 RSTC2 RSTC1 RSTC0 Initial Value Description Default 7 - 4 RESET Command: Used to send a RESET signal to the appropriate hardware in order to clear a particular status condition, a counter, or a general reset.
Page 163 (13) Rx Byte Count Low Register (IRBCLR) Address: H'10007104 (Bank 1, Read) Bit Name RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0 Initial Value Description Default 7 - 0 Rx Byte Count, D0 - D7: Provides a running count (Low-order value) of the number of bytes of data being received. It is useful when receiving back-to-back packets.
Page 164 (15) Rx Ring Frame Pointer Low Register (IRRFPLR) Address: H'10007108 (Bank 1, Read) Bit Name RFP7 RFP6 RFP5 RFP4 RFP3 RFP2 RFP1 RFP0 Initial Value Description Default 7 - 0 Ring Frame Pointer (RFP), D0 - D7: Used in back-to-back packet reception to provide the end-of-packet pointer value. Bit Name The RFP value is initially set to 0000h.
Page 165 (17) Tx Byte Count Low Register (ITBCLR) Address: H'1000710C (Bank 1, Read/ Write) Bit Name TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 Initial Value Description Default 0 - 7 Tx Byte Count, D0 – D7: Provide a running count (low-order value) of the number of bytes remaining to be transmitted.
Page 166 (19) Infrared Configuration 1 Register (IIRC1R) Address: H'10007102 (Bank 2, Read/ Write) Bit Name IRSPD3 IRSPD2 IRSPD1 IRSPD0 IRMOD3 IRMOD2 IRMOD1 IRMOD0 Initial Value Description Default 7 - 4 Infrared Speed (IRSPD[3:0]) 0000 Specify the data rate under 1Mbit FIR modulation. Infrared Speed 1.152 Mbps 0.756 Mbps...
Page 167 (20) Infrared Transceiver Control Register (IIRTCR) Address: H'10007104 (Bank 2, Read/ Write) Bit Name DFREQ MODSEL ECHO TXDF Initial Value Description Default 7 - 6 Reserved High/Low Data frequency (DFREQ) When an HP-like transceiver is selected in the configuration register, high or low infrared data frequency is determined by this bit.
Page 168 (21) Infrared Configuration 2 Register (IIRC2R) Address: H'10007106 (Bank 2, Read/ Write) Bit Name ACEN CCTRL1 CCTRL0 DSIRI DFIRI Initial Value Description Default 7, 3, 2 4M pulse auto-chopping mechanism (ACEN, CCTRL1, CCTRL0) These bits control the 4M pulse auto-chopping mechanism. This feature handles transceivers which deliver single pulses that exceed the 165ns maximum supported by the 4M demodulator.
Page 169 (22) Timer Register (ITMR) Address: H'10007108 (Bank 2, Read/ Write) Bit Name TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 Initial Value Description Default 7 - 0 Timer value (TMR[7:0]) Timer value, D0 - D7: Specify the initialization value for the down counter. The counter has a period of 128us.
Page 170 (24) SIR Register (ISIRR) Address: H'10007120 (Read/ Write) Bit Name SLOOP SIRMOD Initial Value Description Default 7 - 2 Reserved SIR Loop-back (SLOOP) Sets this bit to 1 to enable SIR loop back mode. Sets this bit to 0 to enable SIR Normal mode.
Page 171 (26) Timing Control Register (ITMCR) Address: H'100071F0 (Read/ Write) Bit Name TMCR2 TMCR1 TMCR0 Initial Value Description Default 7 - 3 Reserved 0 - 2 Timing Control (TMCR[2:0]) These three bits TMCR[2:0] are used to adjust the timing for different CKIO frequency rates.
Page 172: Fir Transmit Operation
11.3 FIR Transmit Operation T1: Setup Phase: (1) Set up Tx Control Registers for Transmitting options. a. Set DCS[1:0] in IMISCR to select DMA channel for Transmit. (Set 80h to IMISCR) b. Set SIP[1:0] and NSFP in ITC2R to send a SIR Interaction Pulse and decide the number of starting flags or preamble.
Page 173: Fir Receive Operation
T4: End of Transmission (1) The byte Counter counts down to 0. (2) DMA request stops. The transmitter sends out the remaining data in the FIFO. (3) CRC generator inverts the CRC and sends it out. (4) Closing Flag is sent. EOM latch is set, and Interrupt is activated. T5: Idle Phase: (1) The transmitter continues sending ‘1’s or Flags (1M)/Preambles (4M) depending on TIDL bit in ITC1R.
Page 174 (3) Set Receiver Enable bit. Set IEN and RXEN to enable FIR interrupt and Receiver. (Set a0h to IMSTCR) (4) FIR mode logic detects Carrier, receive clock starts running. If consecutive ‘1’s are received, the receive clock may not be synchronized with the incoming data. T2: Flag(s)/Preambles Detection: (1) When the Start flag is detected, all counters in the receiver are initialized.
Page 175: Example Of Initialization And Programming Procedure For Hp-Sir
T6: Post Frame Phase: (1) DMA request continues until all the received data in the FIFO have been transferred. Two more bytes in the following format will be stored in Rx FIFO and transmitted to the host receive buffer: First byte: 7 - 0, Byte count 7 to 0 Second byte: 7 - Abort 6 - Frame Error 5 - Overrun...
Page 176: Section 12 Uart
65535; the data rate of each can also be programmed from 115.2K baud down to 50 baud. The c haracter options are programmable for 1 start bit; 1, 1.5, or 2 stop bits; even, odd, stick or no parity; and privileged interrupts. The HD64465 provides two UART ports. 12.2 Features •...
Page 177: Serial Channel Register Description
12.3 Serial Channel Register Description Table 12.1 Serial Channel Registers Register DLAB* Address READ WRITE Data Base+h0000 URBR (Receiver Buffer Register) UTBR (Transmitter Buffer Register) Control Base+h0002 UIER (Interrupt Enable Register) UIER Base+h0004 UIIR (Interrupt identification Register) UFCR (FIFO Control Register) Base+h0006 ULCR (Line Control Register) ULCR...
Page 178: Control Registers: Uier, Uiir, Ufcr, Udll, Udlm, Ulcr, Umcr
12.3.2 Control Registers: UIER, UIIR, UFCR, UDLL, UDLM, ULCR, UMCR (1) UIER (READ/WRITE) UIER is used to enable (or disable) four active high interrupts that activate the interrupt outputs, with its lower four bits: bit 0~bit 3. Description Default 7 - 4 These bits are always “0”.
Page 179: Table 12.2 Interrupt Identification Register
Table 12.2 Interrupt Identification Register FIFO Interrupt Identification Mode Register Interrupt Set and Reset Functions Priority Interrupt RESET Bit 3 Bit 2 Bit 1 Bit 0 Level Interrupt Type Interrupt Source Control None None First Receiver Line OE, PE, FE, or BI ULSR READ Status Second...
Page 180 (3) UFCR (WRITE only) This register is used to enable, clear the FIFO, and set the RCVR FIFO trigger levels. Description Default 7, 6 These bits set the trigger levels for the RCVR FIFO interrupt. UFCR(7) UFCR(6) RCVR FIFO Trigger Level 1 byte 4 bytes 8 bytes...
Page 181: Table 12.3 Baud Rates Using (9.216Mhz/5) Clock
Table 12.3 Baud Rates Using (9.216MHz/5) Clock Desired Baud Rate Divisor Used 2304 1536 1047 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 (6) ULCR (READ/WRITE) ULCR controls the format of the data character and gives the information of the serial line. Description Default Divisor Latch Access Bit: Must be set high to access the Divisor Latches of the baud...
Page 182: Table 12.4 Modem Control Register Bits
ULCR (READ/WRITE) [cont’d] Description Default Parity Enable (PEN): A parity bit, between the last data word bit and stop bit, will be generated or checked (transmit or receive data) when ULCR(3) is high. Stop Bit Select (STB): Specifies the number of stop bits in each serial character, summarized as the following: ULCR(2) Word Length...
Page 183: Status Register Ulsr And Umsr
(7) UMCR (READ/WRITE) [cont’d] Description Default 7 - 5 Are always low Provides a loopback feature for diagnostic test of the serial channel when it is set high. Serial Output (SOUT) is set to the Marking State Shift Register output Loops back into the Receiver Shift Register.
Page 184: Table 12.5 Line Status Register Bits
ULSR (READ/WRITE) [cont’d] Description Default Indicates the parity error (PE) with a logic 1 indicating that the received data character does not have the correct even or odd parity, as selected by ULCR(4). It will be reset to “0” whenever the ULSR is read by the CPU. Overrun Error (OE) bit which indicates by a logic 1 that the URBR has been overwritten by the next character before it had been read by the CPU.
Page 185: Table 12.6 Modem Status Register Bits
(2) UMSR (READ/WRITE) This 8-bit register provides current state of the control lines from modems or peripheral devices. In addition to this current state information; bits 7~ 4 can provide change information when a modem control input changes state. It will be reset to low when the Host reads the UMSR. Description Default Data Carrier Detect (DCD#): Indicates the complement status of Data Carrier Detect...
Page 186: Reset
12.4 Reset Reset of UART should be held to an idle mode reset high for 500ns until initialization, which causes the following: 1. Initialization of the transmitter and receiver internal clock counters. 2. Resetting all bits of ULSR, (except ULSR(5) and ULSR(6), THRE and TEMT (they are set only by a hardware reset), all bits of UMCR and all corresponding discrete lines, memory and logic elements.
Page 187: Programming
12.5 Programming Serial channel is programmed by control registers whose contents define the character length, number of stop bits, parity, baud are modem interface. Even though the control register can be written in any order, the UIER should be the last because it controls the interrupt enables. After the port is programmed, these registers can still be updated whenever the port is not transferring data.
Page 188: Fifo Interrupt Mode Operation
12.8 FIFO Interrupt Mode Operation (1) RCVR Interrupt When bit 0 of UFCR and bit 0 of UIER are set to 1, the RCVR FIFO and receiver interrupts are enabled. The RCVR interrupt occurs under the following conditions: a. The receive data available interrupt and the UIIR, receive data available indication, will be issued only if the FIFO has reached its programmed trigger level.
Page 189: Caution
FIFO Polled Mode Operation [ bit 0 of UFCR is 1, and bits 0, 1, 2, 3 of UIER or all are zero]. Either one or both XMIT and RCVR can be in this operation mode which the user program will check RCVR and XMIT status via the ULSR as described below: LSR(0): Will be high whenever the RCVR FIFO contains at least one byte.
Page 190: Section 13 Parallel Port
Section 13 Parallel Port 13.1 Overview The Parallel Port module supports an IBM AT, PS/2 compatible bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP). But NO DMA transfers are supported in this module. 13.2 Features •...
Page 191: Table 13.1 The Register List Of Parallel Port
Table 13.1 The Register List of Parallel Port SPP/EPP Mode Name Address Register Size(Bit) Access Size(Bit) Data Port Register H'1000A000 Status Port Register H'1000A002 Control Port Register H'1000A004 EPP Address Port Register(*) H'1000A006 EPP Data Port0 Register(*) H'1000A008 EPP Data Port1 Register(*) H'1000A00A EPP Data Port2 Register(*) H'1000A00C...
Page 192: Spp And Epp Modes
13.3.1 SPP and EPP Modes (1) Data Port Register This is a bi-directional 8-bit data register. The direction of data flow is determined by bit 5 of the control register. It forwards directions when the bit is low and reverses when the bit is high. (2) Status Port Register Table 13.3 Status Port Register Description Description...
Page 193: Ecp Mode
(5) EPP Data Port 0 - 3 The EPP Data Port 0 - 3 are only available in EPP mode. When the host writes to these ports, the contents of D0 - D7 are buffered and output to PD0 - PD7 as an EPP DATA Write cycle. When the host reads from these ports, the contents of PD0 - PD7 are buffered and output to D0-D7, and causes an EPP DATA Read Cycle.
Page 194: Table 13.6 Ecp Register Definition
Table 13.6 ECP Register Definition Name Address ECP Mode Function data H'1000A000 000-001 Data Register ecpAFifo H'1000A000 ECP FIFO (Address) H'1000A002 Status Register H'1000A004 Control Register cFifo H'1000A010 Parallel Port Data FIFO ecpDFifo H'1000A010 ECP FIFO (DATA) tFifo H'1000A010 Test FIFO cnfgA H'1000A010 Configuration Register A...
Page 195 (2) ECP Address FIFO Register (ecpAFifo) Any data byte written to this port is placed in the FIFO and tagged as an ECP Address/RLE. The hardware then sends this data automatically to the peripheral. The operation of this port is only valid in forward direction (dcr(5)=0).
Page 196 (5) Parallel Port Data FIFO (cFifo) (Address H'1000A010, Mode 010) Bytes written to this FIFO are sent by a hardware handshake to the peripheral according to the standard parallel port protocol. This operation is only defined for the forward direction. (6) ECP Data FIFO (ecpDFifo) (Address H'1000A010, Mode 011) When the direction bit dcr(5) is “0”, bytes written to this FIFO are sent by a hardware handshaking to the peripheral according to the ECP parallel port protocol.
Page 197 (10) Extended Control Register (ECR) (Address H'1000A014, Mode All) Address: H'1000A014, Mode All Bit Name MODEB2 MODEB1 MODEB0 Reserved Full Empty nErrIntrEn ServiceIntr Initial Value Description Default 7 - 5 Mode: These bits are used for READ/WRITE and Mode selection. NerrIntrEn: 1: Disables the interrupt generated on the asserting edge of the nFault input.
Page 198 (12) Software Operation (ECP) Before ECP operation can begin, it is first necessary for the Host to switch the mode to 000 to negotiate with the parallel port. Host determines whether peripheral supports ECP protocol during the process. After the negotiation is completed, the mode is set to 011 (ECP). To enable the drivers, direction must be set to “0”.
Page 199 Rev. 3.0, 03/01, page 180 of 390...
Page 200: Section 14 Serial Codec Interface
Section 14 Serial CODEC Interface 14.1 Overview This serial CODEC interface provides an interface between the system and the CODEC that is CS4218 or CS4271 or compatible with AC97. The major functions of the interface are transmitting D/A data from system to CODEC and receiving A/D data from CODEC to system. 14.1.1 Features •...
Page 201: Block Diagram
14.1.2 Block Diagram Chip Internal Bus Internal Bus Interface CSxx CSxx AC97 AC97 Ckgen Controller Controller Controller Controller MISC ACCLK SIBCLK ACIRQ#/ SDOUT SDIN SSYNC ACRST# ACPD# CODEC Figure 14.1 The Block Diagram of Serial CODEC Interface Rev. 3.0, 03/01, page 182 of 390...
Page 202: Register Description
Table 14.1 Pin Function of Serial CODEC Interface Module Name Pin Function ACCLK Master Clock SIBCLK Serial Port Bit Clock SIBDIN Serial interface data input: Data is transferred from CODEC to this module SIBDOUT Serial interface data output: Data is transferred from this module to CODEC SIBSYNC Serial interface sync: This high active pin indicates that a frame starts from the rising edge of the next SCLK.
Page 203: Transmit Data Register (Tdr)
Table 14.2 Registers of SCDI (cont’d) Register or Buffer Function Access Size Address PCMLFE PCM Low Frequency Enhance 32 bits H'1000C040 LINE2 Line 2 data Register 32 bits H'1000C044 HSET HSET Data Register 32 bits H'1000C048 IOCS IO Control or Status register 32 bits H'1000C04C ATIER...
Page 204: Receive Data Register (Rdr)
Transmit Data Register (TDR) [cont’d] Bit Name Initial Value Description Default 31 - 0 TX Data (TD): MSB is the first bit to be transmitted to Serial Data Output Port. 14.2.2 Receive Data Register (RDR) RDR, a 32-bit Read only register, is used as a channel to read data from RX FIFO. RDR is not initialized.
Page 205: Control Register (Cr)
Receive Data Register (RDR) [con’d] Description Default 31 - 0 Receive Data (RD): MSB is the first bit to be received from Serial Data Input Port. 14.2.3 Control Register (CR) CR is a 16-bit Read/Write register that is used to control Serial CODEC Interface. Bits 15 - 14 of this register are reserved.
Page 206: Status Register (Sr)
Control Register (CR) [cont’d] Description Default Mode Select: (MS): ( for CS4218 or CS4271) 1:the serial CODEC interface is master. 0:the serial CODEC interface is slave. MS must be 1 for CS4271 Start Transfer (ST): ( for SM3-slave mode or AC97): Writing 1 to this bit will start transmitting or receiving data.
Page 207 Status Register (SR) [cont’d] Description Default Reserved IRQ from CS4271 (IR71): This bit 1 indicates that CS4271 issues interrupt request. TX FIFO Not Full Flag (TNF) 0: TX FIFO is full. 1: TX FIFO is not full. 12 - 11 TX FIFO Status(TFS) RFS[1:0] FIFO-1...
Page 208: Frequency Select Register
14.2.5 Frequency Select Register FSR, a 16-bit Read/Write register, is used to select frequency-sampling rate of CS4218 when SM3 slave mode is selected. Bits 15 - 3 in this register are reserved. The other bits in this register are initialized to 0 at reset. FSR is not initialized in STANDBY mode. Bit Name reserved reserved reserved reserved reserved reserved reserved reserved Initial Value...
Page 209: Command/Status Address Register (Csar)
14.2.6 Command/Status Address Register (CSAR) CSAR, a 32-bit Read/Write register, is a channel via which the system can write command address to CODEC or read status address from CODEC. Bits 31-20 and bits 11-0 are reserved. The other bits are initialized to 0 at reset. CAR is not initialized in STANDBY mode. Bit Name Initial Value Bit Name...
Page 210: Command/Status Data Register (Csdr)
14.2.7 Command/Status Data Register (CSDR) CSDR, a 32-bit Read/Write register, is a channel via which the system can write command data to CODEC or read status data from CODEC. Bits 31-20 and bits 3-0 are reserved. The other bits are initialized to 0 at reset.
Page 211: Pcm Playback/Record Left Channel (Pcml)
14.2.8 PCM Playback/Record Left Channel (PCML) PCML, a 32-bit Read/Write register, is a channel via which the system can write PCM Playback Left Channel data to CODEC or read PCM Record Left Channel data from CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset. PCML is not initialized in STANDBY mode. Bit Name Initial Value Bit Name...
Page 212: Pcm Playback/Record Right Channel (Pcmr)
14.2.9 PCM Playback/Record Right Channel (PCMR) PCMR, a 32-bit Read/Write register, is a channel via which system can write PCM Playback Right Channel data to CODEC or read PCM Playback Right Channel data from CODEC. Bits 31-20 are reserved. Bits 19-0 are initialized to 0 at reset. PCMR is not initialized in STANDBY mode. Bit Name Initial Value Bit Name...
Page 213: Line 1 Data Register (Line1)
14.2.10 Line 1 Data Register (LINE1) LINE1, a 32-bit Read/Write register, is a channel via which the system can write Line1 DAC data to CODEC or read Line1 ADC data from CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset.
Page 214: Pcm Center Playback/Mic Adc Channel (Pcmc)
14.2.11 PCM Center Playback/MIC ADC Channel (PCMC) PCMC, a 32-bit Read/Write register, is a channel via which the system can write PCM Center Playback data to CODEC or read MIC ADC data from CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset.
Page 215: Pcm Left Surround Channel Data Register (Pcmls)
14.2.12 PCM Left Surround Channel Data Register (PCMLS) PCMLS, a 32-bit Write Only register, is a channel via which the system can write PCM Left Surround Playback data to CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset.
Page 216: Pcm Right Surround Channel Data Register (Pcmrs)
14.2.13 PCM Right Surround Channel Data Register (PCMRS) PCMRS, a 32-bit Write Only register, is a channel via which the system can write PCM Right Surround Playback data to CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset.
Page 217: Pcmlfe Data Register (Pcmlfe)
14.2.14 PCMLFE Data Register (PCMLFE) PCMLFE, a 32-bit Write Only register, is a channel via which the system can write PCMLFE data to CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset. PCMLFE is not initialized in STANDBY mode.
Page 218: Line 2 Channel Data Register (Line2)
14.2.15 Line 2 Channel Data Register (LINE2) LINE2, a 32-bit Read/Write register, is a channel via which the system can write Line 2 DAC data to CODEC or read Line2 ADC data from CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset.
Page 219: Hset Data Register (Hset)
14.2.16 HSET Data Register (HSET) HSET, a 32-bit Read/Write register, is a channel via which the system can write HSET DAC data to CODEC or read HSET ADC data from CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset. HSET is not initialized in STANDBY mode. Bit Name Initial Value Bit Name...
Page 220: Io Control/Status Data Register (Iocs)
14.2.17 IO Control/Status Data Register (IOCS) IOCS, a 32-bit Read/Write register, is a channel via which the system can write IO Control data to CODEC or read IO Status data from CODEC. Bits 31-20 are reserved. The other bits are initialized to 0 at reset.
Page 221: Ac97 Transmit Interrupt Enable Register (Atier)
14.2.18 AC97 Transmit Interrupt Enable Register (ATIER) ATIER, a 32-bit Read/Write register, is used to enable or disable AC97 TX Interrupt. Bits 31-30 are reserved. The other bits are initialized to 0 at reset. ATIER is not initialized in STANDBY mode.
Page 222 AC97 Transmit Interrupt Enable Register (ATIER) [cont’d] Description Default Line 1 TX FIFO REQUEST Interrupt Enable (L1TFRQIE): When this bit is 1, Line 1 TX FIFO Request is enabled. When this bit is 0, Line 1 TX FIFO Request is disabled. PCMC TX FIFO REQUEST Interrupt Enable (PCTFRQIE): When this bit is 1, PCMC TX FIFO Request is enabled.
Page 223 AC97 Transmit Interrupt Enable Register (ATIER) [cont’d] Description Default PCMLS TX FIFO OVERRUN Interrupt Enable (PLSTFOVIE): When this bit is 1, PCMLS TX FIFO OVERRUN Interrupt is enabled. When this bit is 0, PCMLS TX FIFO OVERRUN Interrupt is disabled. PCMRS TX FIFO OVERRUN Interrupt Enable (PRSTFOVIE): When this bit is 1, PCMRS TX FIFO OVERRUN Interrupt is enabled.
Page 224: 14.2.19 Ac97 Tx Fifo Status Register
AC97 Transmit Interrupt Enable Register (ATIER) [cont’d] Description Default PCMLFE TX FIFO UNDERRUN Interrupt Enable (PLFETFUNIE): When this bit is 1, PCMLFE TX FIFO UNDERRUN Interrupt is enabled. When this bit is 0, PCMLFE TX FIFO UNDERRUN Interrupt is disabled. Line2 TX FIFO UNDERRUN Interrupt Enable (L2TFUNIE): When this bit is 1, Line 2 TX FIFO UNDERRUN Interrupt is enabled.
Page 225 Bit Name L1TFUN PCTFUN PLSTFU PRSTFU PLFETFU L2TFUN HTTFUN IOCTFUN Initial Value Description Default 31 - 30 Reserved PCML TX FIFO REQUEST (PLTFRQ): 1 indicates that half of PCML TX FIFO is empty and must be filled by the system. PCMR TX FIFO REQUEST (PRTFRQ): 1 indicates that half of PCMR TX FIFO is empty and must be filled by the system.
Page 226 AC97 TX FIFO Status Register [cont’d] Description Default PCMRS TX FIFO OVERRUN (PRSTFOV): 1 indicates that PCMRS FIFO is overrun. PCMLFE TX FIFO OVERRUN (PLFETFOV): 1 indicates that PCMLFE FIFO is overrun. Line2 TX FIFO OVERRUN (L2TFOV): 1 indicates that Line2 FIFO is overrun. HSET TX FIFO OVERRUN (HTTFOV): 1 indicates that HSET TX FIFO is overrun.
Page 227: Ac97 Rx Fifo Interrupt Enable Register (Arier)
14.2.20 AC97 RX FIFO Interrupt Enable Register (ARIER) ARIER, a 32-bit Write only register, is used to enable or disable AC97 RX Interrupt. Bits 31-23are reserved. The other bits are initialized to 0 at reset. ARIER is not initialized in standby mode. Bit Name Initial Value Bit Name...
Page 228 AC97 RX FIFO Interrupt Enable Register (ARIER) [cont’d] Description Default PCML RX FIFO REQUEST Interrupt Enable (PLRFRQIE): When this bit is set to 1, PCML RX FIFO Request Interrupt is enabled. When this bit is reset to 0, PCML RX FIFO Request Interrupt is disabled. PCMR RX FIFO REQUEST Interrupt Enable (PRRFRQIE): When this bit is set to 1, PCMR RX FIFO Request Interrupt is enabled.
Page 229 AC97 RX FIFO Interrupt Enable Register (ARIER) [cont’d] Description Default HSET RX FIFO OVERRUN Interrupt Enable (HTRFOVIE): When this bit is set to 1, HSET RX FIFO OVERRUN Interrupt is enabled. When this bit is reset to 0, HSET RX FIFO OVERRUN Interrupt is disabled. IO CTRL/STA RX FIFO OVERRUN Interrupt Enable (IOCSRFOVIE): When this bit is set to 1, IO CTRL/STA RX FIFO OVERRUN Interrupt is enabled.
Page 230: Ac97 Rx Status Register (Arsr)
14.2.21 AC97 RX Status Register (ARSR) ARSR, a 32-bit Read Only register, is used to reflect the status of AC97 RX controller. Bits 31-23 are reserved. The other bits are initialized to 0 at reset. ARSR is not initialized in STANDBY mode.
Page 231 AC97 RX Status Register (ARSR) [cont’d] Description Default PCMR RX FIFO REQUEST (PRRFRQ): When this bit is set to 1, it indicates that half of PCMR RX FIFO is full and must be cleared by the system. Line 1 RX FIFO REQUEST (L1RFRQ): When this bit is set to 1, it indicates that half of Line 1 RX FIFO is full and must cleared by the system.
Page 232: Ac97 Control Register (Acr)
AC97 RX Status Register (ARSR) [cont’d] Description Default Line2 RX FIFO UNDERRUN (L2RFUN): When this bit is set to 1, it indicates that Line 2 RX FIFO is underrun HSET RX FIFO UNDERRUN (HTRFUN): When this bit is set to 1, it indicates that HSET RX FIFO is underrun IO CTRL/STA RX FIFO UNDERRUN (IOCSRFUN): When this bit is set to 1, it indicates that IO CTRL/STA RX FIFO is underrun 14.2.22 AC97 Control Register (ACR)
Page 233 AC97 Control Register (ACR) [cont’d] Description Default Version Select (VS): If this bit is set to 1, this module supports AC97 Ver2.0. Otherwise, this module supports AC97 Ver1.03 30 - 21 Reserved RX DMA Enable (RXDMA_EN): If this bit is set to 1, RX DMA function is enabled. Otherwise, RX DMA function is disabled.
Page 234: Ac97 Tag Register (Atagr)
14.2.23 AC97 TAG Register (ATAGR) ATAGR, a 32-bit Read/Write register, is used to write TX tag or read RX tag. Bits 18-13 are reserved. The other bits are initialized to 0 at reset. ATAGR is not initialized in STANDBY mode. Bit Name RXVS1 RXVS2...
Page 235: Slot Request Active Register (Srar)
14.2.24 Slot Request Active Register (SRAR) SRAR, a 16-bit Read/Write register, is used to set the active level of the solt request of slot3-12. Bits 15-13 and 2-0 are reserved. The other bits are initialized to 0 at reset. SRAR is not initialized in STANDBY mode.
Page 236: Function Description
Slot Request Active Register (SRAR) [cont’d] Description Default Slot Request 5 Active (SL5RA): When this bit is set to 1, slot 5 request is high active. Otherwise, slot 5 request is low active. Slot Request 4 Active (SL4RA): When this bit is set to 1, slot 4 request is high active. Otherwise, slot 4 request is low active.
Page 237: Cs4218 Or Cs4271 Tx Controller
14.3.3 CS4218 or CS4271 TX Controller This module, as shown in Fig14-2, contains a TX FIFO, a 32-bit buffer (BUF), a parallel-to-serial shift register (PSR) and an inferred control circuit. This TX FIFO has two blocks and each block has 4 32-bit entries. When TX transaction begins, the data stored in TX FIFO will be written to BUF whenever BUF is empty.
Page 238: Ac97 Rx Controller
DMA transfer only supports PCML (slot3) and PCMR (slot4) at the same time. Sound data must be prepared as stereo sound data. Only PCML (slot3) register is used for stereo data transfer with automatic register switching. 14.3.6 AC97 RX Controller This module, as shown in Fig14-5, contains several RX FIFOs, a SLOTREQ register, a 20-bit buffer, a serial-to-parallel shift register and an inferred control circuit.
Page 239: Program Flow
14.4 Program Flow Figure14-7 on page 171 illustrates the program flow of CS4218 or CS4271 in PIO mode. Figure14-8 on page 172 illustrates the program flow of AC97 in DMA mode. The flows under the other conditions including that of CS42xx in DMA mode and that of AC97 in PIO mode are analogous to these flows.
Page 240: Figure 14.5 Ac97 Tx Controller
SLOTREQ from AC97 RX controller ATAGR CARTX CDR TX PCML TX PCMR TX SDOUT IOCS TX Figure 14.5 AC97 TX Controller Rev. 3.0, 03/01, page 221 of 390...
Page 241: Figure 14.6 Ac97 Rx Controller
AC97 TX SLOTREQ Controller STA RX STD RX PCML RX SDIN IOCS RX Figure 14.6 AC97 RX Controller Rev. 3.0, 03/01, page 222 of 390...
Page 242: Figure 14.7 Tx Flow In Pio Mode For Cs4218 Or Cs4271
1.Software Reset 1.SDOUT=0 2.Pre write data to fill TX FIFO 2.TXEN=1 3.write TXEN=1 (refer to HW step 3.Enable TX FIFO control 4.Transmitting Data in 4.Interrupt FIFO 5. One block FIFO empty 5.Software read status and TDI=1 6. INTERRUPT (refer to SW step 4) 6.Write data to fill the empty block of TX FIFO and clear interrupt(refer...
Page 243: Figure 14.8 Rx Flow In Pio Mode For Cs4218 Or Cs4271
1.Hardware does 1.Software Reset not read SDIN 2.write RXEN=1 (go to HW step 2) 2.RXEN=1 3.Interrupt 3.Enable RX FIFO control 6.RDI=1 4.Receving data 7.Read one block data 5. One block from RX FIFO and clear FIFO full interrupt (go to HW step 4) 6.
Page 244: Figure 14.9 Ac97 Dma Program Flow
CPU DMA Setting Initial Setting Select AC97 Interface, Version 2.0, TX DMA (AC97S=1,VS=1,TXDMA_EN=1) Reset AC97 CODEC (Warm reset or cold reset) Start Transfer (ST=1,CRE=1, TXEN=1,RXEN=1) Check CODEC Ready (Read ATAGR) CR=1? Normal Operation Write Command or Read Status Write Power Down Command if all data has been transfer Figure 14.9 AC97 DMA Program Flow Rev.
Page 245: Figure 14.10 Warm/Cold Reset Timing
Trst_low RESET# SIBCLK Tsync_high SYNC SIBCLK Figure 14.10 Warm/Cold Reset Timing Tsetup SIBCLK SIBDIN Tsod Thold SIBSYNC SIBDOUT Figure 14.11 Serial Data Setup, Hold and Output Delay Timing Rev. 3.0, 03/01, page 226 of 390...
Page 246: Table 14.3 Ac97 Timing
Table 14.3 AC97 Timing Item Symbol Unit RESET# Active Low Pulse Width Trst_low µs SYNC Active High Pulse Width Tsync_high µs Setup to Falling Edge of SIBCLK Tsetup Hold to Falling Edge of SIBCLK Thold Output Delay to Rising Edge of SIBCLK Tsod Rev.
Page 247 Rev. 3.0, 03/01, page 228 of 390...
Page 248: Section 15 Afe Interface
Section 15 AFE Interface 15.1 Overview An AFE interface is a circuit to interface with Modem AFE (SGS-Thomson STLC7546/7550); and is capable of performing a serial data transfer function. A divider is also incorporated to transmit a master clock to Modem AFE. 15.1.1 Features •...
Page 249: Block Diagram
15.1.2 Block Diagram Chip Internal BUS AFE Interface Module Internal Bus RXDB1 TXDB1 RXDB0 TXDB0 (48Word) (48Word) Control Block RXDR TXDR RSFTR TSFTR 1/6,1/7,1/8 Rx Block Tx Block Figure 15.1 AFE Interface Block Diagram Rev. 3.0, 03/01, page 230 of 390...
Page 250: Register Description
Table 15.1 Pin Function of AFE Interface Module Name Pin Function DOUT(RxD) Serial Receive Data Input Pin, from AFE module Frame Sync Signal Input Pin SCLK Shift Clock Input Pin DIN(TxD) Serial Transmit Data Output Pin, to AFE module RESETO# (CNT1) External Chip Control Signal 1 Output Pin (RESETO#) PWRDWNO#(CNT2) External Chip Control Signal 2 Output Pin (PWRDWNO#)
Page 251: Control Register (Ctr)
15.2.1 Control Register (CTR) CTR, a 16-bit READ/WRITE register, is used to control an AFE interface. All the bits on this register are initialized to 0 at RESET. CTR is not initialized in the STANDBY mode. Bit Name Div2 Div1 RLYCNT CNT2 CNT1 Initial Value...
Page 252: Status Register (Str)
Control Register (CTR) [cont’d] Description Default Receive Error Interrupt (RERI) enable 1: enable 0: disable Transmit Data Empty Interrupt (TDEI) enable 1: enable 0: disable Receive Data Full Interrupt (RDFI) enable 1: enable 0: disable Buffer Disable 1: data is transferred with register (TXDB and RXDB). 0: data is transferred with buffers (TXDB and RXDB).
Page 253 Status Register [cont’d] Description Default Indicates the transmit buffer is accessible 1: READ/WRITE can be performed to TXDB1. 0: READ/WRITE can be performed to TXDB0. This bit will be set when the following two conditions are met. 1) When only transmit data buffer 1 is empty 2) When the TE bit is set to 1 The bit will be cleared when either one of the following conditions is met.
Page 254 Status Register [cont’d] Description Default Receive error indication 1: indicates that a receive error has occurred. 0: indicates that a receive error does not occur. This bit will be set when the next data receive is completed while both receive data buffers are full.
Page 255: Transmit Data Register (Txdr)
15.2.3 Transmit Data Register (TXDR) TXDR, a 16-bit READ/WRITE register, is used to transmit the stored data. All the bits in this register are initialized to 0 at RESET. TXDR is not initialized in the STANDBY mode. RESET 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TXDR functions as a transmit data register when the BUFD bit (bit 15) in CTR is 1, and an AFE control data transmit register when the BUFD bit is 0.
Page 256: Receive Data Buffers (Rxdb0,1)
RESET - 15.2.7 Receive Data Buffers (RXDB0,1) RXDB0 and RXDB1 are receive data storage buffers, and are able to store 48-word data. The hardware configuration determines the buffer, where the data are received. Users can access only one buffer that is not used to receive data. RDB0 and RDB1 are not initialized in the STANDBY mode.
Page 257: Data Receive
Data Transmit with Register When data are transmitted via TXDR, data stored in TXDR are used as the transmitted data. When data transmission starts in TXDR, TDEI is output. TERI is output when the next FX is received before the transmitted data are written to TXDR. Before 1 Data Transmit in Buffer Use Mode In an AFE-interface module, it is defined that both transmit data buffers are empty when the TE bit...
Page 258: Divider
Data Receive with Register When data are received in RXDR, the received data are stored in RXDR. When data are stored in RXDR, RDFI is output. A receive data error interrupt is output when the next data are received in the receive data full status. When Both Receive Data Buffers Are Full If both receive data buffers become full, the RDF bit must be cleared (clearing to 0 after reading 1) twice in the same way as described in section 15.1.3.1.3 on the last page.
Page 259: External Chip Control Signal
15.5 External Chip Control Signal An AFE interface is capable of transmitting the three external chip control signals of RESETO#, PWRDWNO# and HC1. The output for each of the signals is individually controlled by the corresponding bits in CRT. For the two signals of CNT1 (RESETO#) and CNT2 (PWRDWNO#), the values set in CTR are output without delay.
Page 260: Interrupt
15.6 Interrupt An AFE interface is capable of generating five interrupts. Among these interrupts, four interrupts of TDEI, RDFI, TERI, and RERI are issued by setting the enable bits in CTR to 1. On the other hand, an interrupt of RDWT is masked by setting the RDETM bit to 1. Interrupt Source Issuance Condition...
Page 261: How To Use The Special Pin (Rlycnt, Ring)
DOUT data1 data2 data47 data48 (RxD) RDFI Figure 15.5 RDFI Output Timing 15.7 How to Use the Special Pin (RLYCNT, RING) An AFE interface contains two special pins: RLYCNT and RING. 15.7.1 How to use the RLYCNT pin The RLYCNT pin is used for relay control and dial pulse generation. Relay control is achieved by writing a value to the RLYCNT bit in CTR while the TSW bit in CTR is 0.
Page 262: Section 16 Keyboard Controller Interface
Section 16 Keyboard Controller Interface 16.1 Overview The keyboard controller interface provides an ISA-like interface to connect CPU and keyboard controller. 16.1.1 Features • Power management function of keyboard controller is supported Rev. 3.0, 03/01, page 243 of 390...
Page 263: Block Diagram
PWM/DAC output as digital VR to control LCD and Audio Power SW PowerOn# HDB0-7 Smart IRQ1 KBIRQ0 Battery KBIRQ1 IRQ12 IOW# XIOW# Keyboard IOR# XIOR# HD64465 Controller PS/2 Keyboard KBCS# CS1# CS2# PS/2 KBRESUME# IRQ11 Mouse KBWAKEUP# NMI# Scan0-15 Sense0-7 Wait#...
Page 264: Register Description
Table 16.1 Pin Function of Keyboard Controller Interface Module Name Pin Function KBCS# Keyboard Controller Chip Select XIOW# Keyboard Controller Write Enable XIOR# Keyboard Controller Read Enable KBIRQ0 Keyboard Controller interrupt 0 KBIRQ1 Keyboard Controller interrupt 1 KBRESUME# Keyboard Controller Resume KBWAKEUP# Keyboard Controller wakes up the STANDBY system via signal KBWAKEUP#.
Page 265: Status Register (Sr)
Control Register (CR) [cont’d] Description Default KCRESUME Trigger Type Select 0 (KCRTTS0): 1: edge trigger is selected. 0: level trigger is selected. IRQ1 Trigger Type Select 1 (IRQ1TTS1): 1: If edge trigger is selected, falling edge trigger is selected. If level trigger is selected, low level trigger is selected. 0: If edge trigger is selected, rising edge trigger is selected.
Page 266: H8 Control 1 Register (H8C1R)
16.2.3 H8 Control 1 Register (H8C1R) H8C1R is an 8-bit read/write register. System can write data to IDR1 of H8 via this register and read the data of ODR1 of H8 via this register. 16.2.4 H8 Control 2 Register (H8C2R) H8C2R is an 8-bit read/write register.
Page 267: Table 16.2 Keyboard Controller Interface Read Cycle Ac Timing
Table 16.2 Keyboard Controller Interface Read Cycle AC Timing Item Symbol Unit XIOR# delay time tIORD KBCS#/A2 delay time tRCSD XIOR# pulse width tIORPW HD0-7 setup time tHDS HD0-7 hold time tRHDH Table 16.3 Keyboard Controller Interface Write Cycle AC Timing Item Symbol Unit...
Page 268: Section 17 Ps/2 Interface
Section 17 PS/2 Interface 17.1 Overview The PS/2 interface is implemented as a Register Interface peripheral. All protocols and timing conform to IBM-PC PS/2 specifications. The interface supports two emulation channels to be connected PS/2 keyboard and PS/2 mouse individually. 17.2 Pin Configuration Pin Number...
Page 269: Keyboard Control/Status Register (Kbcsr)
17.3.1 Keyboard Control/Status Register (KBCSR) This keyboard control register contains receive data shift register and keyboard interface control/status bits. Address: H'1000DC00 Bit Name KBCIE KBCOE KBDOE KBCD KBDD KBCS KBDS KBDP Initial Value Bit Name KBD7 KBD6 KBD5 KBD4 KBD3 KBD2 KBD1 KBD0...
Page 270: Keyboard Interrupt Status Register (Kbisr)
Keyboard Control/Status Register (KBCSR) [cont’d] Description Default KBCK Pin Status (KBCS) 1: KBCK pin is high level. 0: KBCK pin is low level. KBDATA Pin Status (KBDS) 1: KBDATA pin is high level. 0: KBDATA pin is low level. Parity Bit (KBDP) This bit indicates the parity bit of the received data.
Page 271: Mouse Control/Status Register (Mscsr)
17.3.3 Mouse Control/Status Register (MSCSR) This mouse control register contains receive data shift register and mouse interface control/status bits. Address: H'1000DC10 Bit Name MSCIE MSCOE MSDOE MSCD MSDD MSCS MSDS MSDP Initial Value Bit Name MSD7 MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0...
Page 272: Mouse Interrupt Status Register (Msisr)
Mouse Control/Status Register (MSCSR) [cont’d] Description Default MSCK Pin Status (MSCS) 1: MSCK pin is high level. 0: MSCK pin is low level. MSDATA Pin Status (MSDS) 1: MSDATA pin is high level. 0: MSDATA pin is low level. Parity Bit (MSDP) This bit indicates the parity bit of the received data.
Page 273: Block Diagram
17.4 Block Diagram Figure 17-1 shows a block diagram of the PS/2 keyboard or mouse interface. When one byte of data is received from the external keyboard or mouse, the interface generates an interrupt to the CPU. Key buffer (reciver data shift register) KBCSR (MSCSR) 0 Parity...
Page 274: Operation
17.5 Operation The PS/2 interface module supports some registers and hardware circuit to implement standard PS/2 interface. At the following sections, they describe the serial data format, software operational sequence and communication protocol. These descriptions take the keyboard operation as principal thing.
Page 275: Communication Protocol
Transferring Data to the Keyboard: 1. Clear the KBCIE bit to 0, set the KBCOE bit to 1, and clear the KBCD bit to 0. This drives KBCK signal to low level. The keyboard will be inhibited by detecting a low level of KBCK pin.
Page 276: Table 17.2 Data Receive Timing Parameters
10th 11th DATA Parity bit Start bit bit 0 Stop bit Figure 17.3 Data Receive Timing Table 17.2 Data Receive Timing Parameters Timing Parameter Explanation Min (us) Max (us) Time from DATA transition to falling edge of CLK Time from rising edge of CLK to DATA transition t4-5 Duration CLK inactive Duration of CLK active...
Page 277: Caution
10th 11th inhibit DATA Start bit bit 0 Parity bit Stop bit Figure 17.4 Data Send Timing Table 17.3 Data Send Timing Parameters Timing Parameter Explanation Min (us) Max (us) Duration of CLK inactive Duration of CLK active Time from inactive to active CLK transmission, used to time when the keyboard samples DATA 17.6 CAUTION...
Page 278: Section 18 Usb Host Controller
Section 18 USB Host Controller 18.1 Introduction 18.1.1 Device Description / Purpose This USB Host Controller is a PCI-based implementation of the Universal Serial Bus (USB) 1.0 specification utilizing the OpenHCI standard developed by Compaq, Microsoft, and National Semiconductor. It contains an integrated Root Hub with two USB ports, PCI interface, and USB Host Controller.
Page 279: Function Description
The following diagram shows the whole system architecture, which relates the Host CPU(Hitachi SH4 CPU) and HD64465 USB Host Controller by built-in Host/PCI bridge and SRAM Controller. It means that the internal SRAM memory space is the communication channel between Host CPU and USB Host Controller.
Page 280: Usb Host Controller
18.2.2 USB Host Controller USB States The Host Controller has four USB states visible to the Host Controller Driver via the Operational Registers: U , and U . These states define the PERATIONAL ESET USPEND ESUME Host Controller responsibilities relating to USB signaling and bus states. The USB states are reflected in the HostControllerFunctionalState field of the HcControl register.
Page 281 USB OPERATIONAL When in the U state, the Host Controller may process lists and will generate SOF PERATIONAL Tokens. The U state may be entered from the U or U states. It PERATIONAL ESUME ESET may be exited to the U or U states.
Page 282 USB RESUME When in the U state, the Host Controller forces resume signaling on the bus. While in ESUME , the Root Hub is responsible for propagating the USB Resume signal to downstream ESUME ports as specified in the USB Specification. The Host Controller's list processing and SOF Token generation are disabled while in U .
Page 283: Figure 18.2 List Priority Within A Usb Frame
List Control Block 1) Priority The list priorities are modified as endpoints are serviced and at periodic intervals. In each frame, an interval of time is reserved for processing of items in the Control and Bulk lists. This interval is at the beginning of each frame. The Host Controller Driver limits this time by writing HcPeriodicStart with a bit time after which periodic transfers (Interrupt and Isochronous) have priority for use of the bus.
Page 284: Figure 18-3. Example Of Control/Bulk Service Ratio Of 4:1
a) List Priority The lists built up by the Host Controller Driver are classified as either periodic or non- periodic. The Interrupt list and the Isochronous list are periodic because the endpoints on those lists require service at specific times in a deterministic manner. The Control list and the Bulk list are non-periodic because endpoints on those lists can tolerate latency and expect service only on a time-available basis.
Page 285 The Host Controller enforces the Control Bulk Service Ratio regardless of the number of Control and Bulk Endpoint Descriptors present on their respective lists. If there is only 1 CTRL ED (Control Endpoint Descriptor) on the Control list and the Control Bulk Ratio is 4:1, that CTRL ED is serviced 4 times before a BULK ED (Bulk Endpoint Descriptor) is serviced.
Page 286 ED Block The ED Block is responsible for processing Endpoint Descriptors. This includes reading EDs from memory, servicing an active TD if necessary, and writing back information if necessary. 1) List Service Flow This section describes the actions required of the Host Controller during list processing. These actions are taken after the Host Controller has determined which particular list is to be serviced.
Page 287: Figure 18.4 List Service Flow
SERVICE LIST List Read Peridoc List? FINISHED Enabled? HEAD pointer HEAD pointer Hc _ _ _ _ CurrentED = 0? = 0? _ _ _ _Filled = 1? Hc _ _ _ _ CurrentED = (Bulk or Control) Hc _ _ _ _ HeadED _ _ _ _Filled = 0 ISOCHRONOUS Hc_ _ _ _CurrentED =...
Page 288  Locating Endpoint Descriptors After determining a list is enabled, the Host Controller locates the first Endpoint Descriptor requiring service. The first time the Host Controller services a list after entering the state, it uses the lists Head Pointer to locate the first Endpoint Descriptor PERATIONAL on the list.
Page 289 3. If the current list is the Control List, the Host Controller next action is dependent on whether or not the number of Control Endpoint Descriptors dictated by the Control/Bulk Service Ratio have been serviced. If the Control/Bulk Service Ratio has been satisfied, the Host Controller moves on to the Bulk list;...
Page 290: Figure 18.5 Endpoint Descriptor Service Flow
2) Endpoint Description Processing During the processing of a list, the Host Controller is required to interpret and service the Endpoint Descriptors present on that list. The flow for service of an Endpoint Descriptor is shown in Figure 18-5. SERVICE ENDPOINT DESCRIPTOR HALT = 1...
Page 291  Transfer Description Priority The priority of Transfer Descriptors on a queue is first-come-first-serve. The Transfer Descriptors the Host Controller services are always part of a queue attached to an Endpoint Descriptor. The Host Controller services the first Transfer Descriptor on the queue which is pointed to by the NextTransferDescriptor field of the Endpoint Descriptor.
Page 292: Figure 18.6 Endpoint Descriptor
5) Description Registers The ED Block maintains 4 32-bit registers to hold requested Endpoint Descriptors. These registers are used as temporary storage for Endpoint Descriptors being serviced and are not addressable by software. Figure 18-6 shows the fields present in each of the 4 Endpoint Descriptor registers.
Page 293: Figure 18.7 Transfer Description Service Flow
1) Transfer Description Processing Transfer Descriptor processing is the fundamental operation performed by a Host Controller. The service flow for servicing a Transfer Descriptor is shown in Figure 18-7 below. The rest of this section describes the steps necessary for completing service of a Transfer Descriptor. SERVICE TRANSFER DESCRIPTOR...
Page 294: Table 18.1 Example Calculation Of R And Host Controller Action
a) Isochronous Relative Frame Number Calculation When processing an Isochronous Transfer Descriptor, the Host Controller must calculate the relative frame number. This calculation determines which, if any, packet will be sent during the current frame. An Isochronous TD may contain buffers for 1 to 8 consecutive frames of data (FrameCount+1) with the first (0th) data packet of an Isochronous TD sent in the frame for which FrameNumber match the StartingFrame field of the Isochronous TD.
Page 295: Table 18.2 Itd Packet Offset Location
b) Isochronous Packet Begin and End Address Calculation When processing an Isochronous Transfer Descriptor, the RelativeFrame (R) is used to select two offset values, BeginAddrOffset and EndAddrOffset. EndAddrOffset is the lower 12 bits of the last byte of the packet +1. The source of these offsets is shown in Table 18-2. Refer to next section for a description of the Descriptor Registers used.
Page 296 d) General Packet Begin and End Address Calculation When the Host Controller fetches a General Transfer Descriptor, it gets the address of the next memory location to be accessed from CurrentBufferPage and CurrentBufferOffset. If these values are both 0, then the packet size will be zero, regardless of the setting of MaximumPacketSize in the Endpoint Descriptor.
Page 297 If the CurrentBufferPointer requires an update and is not the last packet, the number of bytes transmitted in the packet should be added to the current value of the CurrentBufferPointer field. If the packet crossed a page boundary, the upper 20 bits of the CurrentBufferPointer should be updated with the BufferEndPage field to reflect the change in page base address.
Page 298: Table 18.3 Completion Codes
Table 18.3 Completion Codes Code Meaning Description 0000 General TD or isochronous data packet processing completed RROR with no detected errors 0001 Last data packet from endpoint contained a CRC error. 0010 Last data packet from endpoint contained a bit stuffing violation TUFFING 0011 Last packet from endpoint had data toggle PID that did not...
Page 299 g) Transfer Description Retirement When a transfer descriptor is complete (all data sent/received), the ErrorCount reaches 3 for a GTD, a fatal error condition occurs for a GTD, or an ITD is late, the Transfer Descriptor must be retired. A fatal error is classified as the new CompletionCodes of Stall, DataOverrun, DataUnderrun, and UnexpectedPID.
Page 300 h) Done Queue Occasionally (as determined by the Done Queue Interrupt Counter = 0), when the Done Queue contains one or more Transfer Descriptors, the Host Controller writes the current value of HcDoneHead into the HccaDoneHead immediately following a frame boundary and generates an interrupt.
Page 301: Table 18.4 Dword0 Gtd Fields
a) Dword0 Dword0 contains the status information for the Transfer Descriptor. • Field Table 18.4 Dword0 GTD Fields Bit Range Field 31 - 28 CompletionCode 27 - 26 ErrorCount 25 - 24 DataToggle 23 - 21 DelayInterrupt 20 - 19 Direction BufferRounding Table 18.5 Dword0 ITD Fields...
Page 302: Table 18.7 Dword1 Itd Fields
Table 18.7 Dword1 ITD Fields Bit Range Field 31 - 12 BufferPage0 (BP0) • Load Condition Dword1 is loaded with pci_Data[31:0] when LoadDescriptorDword[1] is asserted. • Update Condition Dword1 is updated with the new CBP only for a GTD when the fm_TransactionServiced and UpdateTD are asserted, and the completion code is DataOverrun, DataUnderrrun, or NoError.
Page 303: Table 18.11 Offset0 Field Description
BEOffset is the buffer end address +1. Offset1 is used for ITDs under certain circumstances to store begin address of the next packet. • Load Condition There are two load conditions for Dword3. The first condition occurs for every TD that is loaded.
Page 304: Table 18.12 List Processor Control Signals
Request Block The system request portion of the List Processor is the top level coordinator of all activity. It arbitrates the master requests, multiplexes the data and control signals to the Host Controller Bus Master. 1) Master Arbitration There are three sources of master requests from the List Processor: HCCA Writeback request (HCCAWBReq), ED request (EDReq), and TD request (TDReq).
Page 305 Frame Management The frame management block is responsible for managing the frame specific tasks required by the USB specification and the OpenHCI specification. These tasks are: 1. Management of the OpenHCI frame specific Operational Registers 2. Operation of the Largest Data Packet Counter 3.
Page 306 The FrameRemainingToggle field (bit) is loaded with FrameIntervalToggle coinciding with FrameRemaining being loaded with FrameInterval. FrameRemainingToggle and FrameIntervalToggle are used by the HCD to determine which value of FrameInterval is being used in the current frame. If the toggle fields match when read, the Host Controller loaded the current value of FrameInterval into FrameRemaining at the beginning of the current frame (current frame is using a newly programmed value).
Page 307 Packet Size Check When a TD is loaded, the packet size must be guaranteed to complete within the remaining frame time. The sections below discuss FS and LS transaction frame requirements. 1) Full speed Check The full speed packet size check is accomplished by comparing the value of a data transactions data packet size (in bits) with the current value of the Largest Data Packet Counter.
Page 308 Interrupt Processing Interrupts are the communication method for HC-initiated communication with the Host Controller Driver. There are several events which may trigger an interrupt from the Host Controller. Each specific event sets a specific bit in the HcInterruptStatus register. The Host Controller requests an interrupt when all three of the following conditions are met: •...
Page 309 ResumeDetected Event A resume detected event occurs when the Root Hub detects resume signaling on the USB bus. The Host Controller will set the ResumeDetected bit when resume signaling is detected. A ResumeDetected interrupt is only possible in the U state.
Page 310 OwnershipChange Event The OwnershipChange bit is set by the Host Controller when the Host Controller Driver sets the OwnershipChangeRequest bit in the HcCommandStatus register. This ensures that an interrupt is generated (unless it is masked) whenever ownership of the Host Controller is passed to and from the operating system Host Controller Driver and any SMM-based Host Controller Driver in the system.
Page 311 The Bus Master Controller maintains the address of the next PCI cycle to be requested. The address is initialized with a value from the List Processor when it initiates a request. The address is updated after each burst transfer completes. This is needed for data transfers that require more than a single burst cycle.
Page 312: Usb Interface
Page Crossing Controller The Page Crossing Controller is responsible for controlling the page address of data transfers. If it receives a request from the Data Buffer Engine that crosses a page boundary, it will break up the request into two separate requests to the Bus Master Controller. The first request will contain the data from the first page, the second request will contain the data from the second page.
Page 313: Table 18.13 Transaction Control Information
Serial Interface Engine (SIE) The SIE is responsible for managing all transactions to the USB. It controls the bus protocol, packet generation/extraction, data parallel-to-serial conversion, CRC coding, bit stuffing, and NRZI encoding. All transactions on the USB are requested by the List Processor and Frame Manager. After the List Processor retrieves all information necessary to initiate communication to a USB device, it generates a request to the SIE accompanied by endpoint specific control information required to generate proper protocol and packet formats to establish the desired communication pipe.
Page 314: Table 18.14 Pid Encoding
2) End of Packet (EOP) Every packet is terminated by an end of packet (EOP) consisting of 2 transmitted single-ended zeros (SE0) followed by a driven idle state for another bit time. 3) Packet Identifier (PID) Each packet contains a packet identifier (PID) declaring the packet function. The PID is transmitted as a 4-bit encoding followed by the bitwise inversion of the PID as an error check.
Page 315: Figure 18.8 Standard Token Packet Format
Packet Bit 7 Bit 0 Byte Sync Pattern[7:0] ~PID[3:0] PID[3:0] Endpoint Address[7:0] Endpoint[3:1] ~CRC[0:4] High-Z Idle Figure 18.8 Standard Token Packet Format Packet Bit 7 Bit 0 Byte Sync Pattern[7:0] ~PID[3:0] PID[3:0] FrameNumber[7:0] ~CRC[0:4] FrameNumber[10:8] High-Z Idle Figure 18.9 SOF Token Packet Format Rev.
Page 316: Figure 18.10 Data Packet Format
5) Data Packet The data packet contains the actual data transfer between the host and endpoint specified in the token packet. DATA0 and DATA1 identify the packet as a data packet. The 0/1 tag on the PID provides a mechanism for data synchronization from one data packet to the next to the same endpoint.
Page 317: Figure 18.12 Preamble Packet Format
7) Preamble Packet The preamble packet is used to inform downstream hubs that a low speed packet is coming. This allows the low speed drivers to be enabled by all ports connected to low speed devices. This is repeated for all packets within the transaction and not just preceding the token packet. This procedure applies only to packets from the host and not packets received from the device.
Page 318: Figure 18.13 Serializer
Serializer The Serializer performs the parallel/serial conversion for both transmitting and receiving. The logic consists of a packet control state machine, 8-bit parallel-load/serial-shift register, 8-bit data latch, PID encoder/decoder, CRC generator/checker, bit stuff counter, NRZI encoder, and data receiver circuit. Data paths of transmitted and received paths share logic since the bus only operates one direction at a time and the path's logical organizations are simply reversed.
Page 319: Figure 18.14 Crc Logic
1) Data Data fields of the token packets are provided by the List Processor and Frame Manager. For a transmitted data packet, the Data Buffer Engine provides the data. Each time a byte is loaded into the shifter the buffer pointer is incremented. The data buffer marks the data byte enabling the CRC remainder into the data stream.
Page 320 1. Token - All data following the PIDs are included in the CRC generation. Equation 18-1 is the polynomial used to generate the token packet CRC: G(X) = X 5 + X 2 + 1 = 10101b Equation 18.1 Token Packet CRC Generator Polynomial After the token data is finished the source of the transmitted bit stream is switched to the CRC (MSb first).
Page 321 3) Bit Stuffing A data rate phase lock requires frequent bus transitions to maintain the lock before the drift potential threaten to corrupt the data stream. To guarantee transitions occur before the data rate drifts to far to maintain the phase lock, bit stuffing is employed to force transitions after 6 bit times without a transition.
Page 322 The phase lock function is required regardless of the data rate, FS or LS, though timing requirements differ.  EOP A valid EOP is identified by the receiver by sampling a SE0 for three consecutive 48 MHz clock periods following by a J-state. This allows for an approximate minimum SE0 pulse width of 40 ns.
Page 323: Figure 18.15 Non-Isochronous Bus Transaction
Bus Protocol 1) Non-Isochronous Transactions Figure 18-15 shows the valid packet sequencing of a non-isochronous transfer. From From IDLE Host Device LS = Low Speed Transaction Token SETUP Data DATA DATA Handshake STALL Figure 18.15 Non-Isochronous Bus Transaction Rev. 3.0, 03/01, page 304 of 390...
Page 324: Table 18.15 Bus Time-Out Periods
2) Isochronous Transfers Figure 18-16 shows the valid packet sequence of an isochronous transfer. An isochronous transfer is characterized by the lack of a handshake phase after a data phase. Note that a handshake is still permitted following the token phase, if a handshake condition is present which supersedes the data phase.
Page 325: Table 18.16 Sie Eof Timing Requirements
a) Back to Back Host Packets During back to back host packets of the same transaction (e.g. token to data packet), a minimum of 2 idle bit times are required from the end of the EOP's SE0 to the SOP of the next packet.
Page 326 5) Data Toggle Synchronization The data toggle PIDs, DATA0 and DATA1, are the final check to ensure the device received a valid ACK handshake. The data packet receiver is responsible for maintaining data toggle bit synchronization. Therefore, the HC is required to correct the IN data toggle synchronization only, while the device corrects OUT data synchronization.
Page 327: Table 18.17 Sie Completion Status
When a transaction completes, the completion status is reported to the List Processor. The SIE can compile all error information to create the CompletionCode field for the TD writeback, but may be overridden by the List Processor. Table 18-17 shows the transaction status (nearly identical to the CompletionCode) definitions generated by the SIE to the List Processor.
Page 328: Table 18.18 In Transaction Error Response
Table 18.18 IN Transaction Error Response IN Transaction / Fdata Phase Data Data Packet Packet Buffer Toggle NAK/ Overrun/ Status Violation Time-out Error Overrun Mismatch STALL Underrun Code Action 1110 Retire transaction. 0101 Retire transaction. 0001 Retire transaction. 0010 0110 0111 1100 Retire transaction.
Page 329: Table 18.20 Hub / Port Commands
Root Hub The Root Hub is a collection of ports which are individually controlled and a hub which maintains control/status over functions common to all ports. The typical command request interface to the hub is emulated by the HCD which communicates directly through the system bus (PCI) to the hub and port controls.
Page 330: Table 18.21 Power Switching Configurations
Hub Control The HC states defined in HC Register Summary section also reflect the hub state. For example, when the HC is suspended, U , the Root Hub is suspended. When the HC is in USPEND , the hub generates the appropriate bus signaling. U resets the Root Hub.
Page 331 5) Resume When the HC is in U , the resume signal, K-state, is broadcast to all enabled ports, ESUME but not selectively suspended ports. Signaling is maintained until the HC leaves U ESUME A trailing LS EOP is used to terminate the resume. After the Resume is removed, bus activity returns to normal.
Page 332 If DeviceRemoveable is set for the port, which means not removable (yes, it is backwards), CurrentConnectStatus is always read a ‘1’. After power is enabled to the port or a hardware reset when no power switching is implemented, a connect event will be detected through the previously defined method resulting in ConnectStatusChange being set and LowSpeedDeviceAttached being configured.
Page 333 If the hub is suspended, i.e. U , while the port is also suspended, the port does not USPEND respond to a U transition. However, an upstream resume at the port forces a ESUME transition. ESUME Interrupts A Root Hub interrupt, RootHubStatusChange, is generated by setting any of the XXXXChange fields in the HcRhStatus and HcRhPortStatus registers.
Page 334: Power Management
18.2.4 Power Management At this time, USB Host Controller supports minimal system level power management features. Each system has its own requirements which makes it impossible to satisfy. The only power management feature implemented is the disabling of the USB clock generator in U USPEND state.
Page 335: Register/Address Summary
18.2.5 Register/Address Summary OpenHCI Registers Although USB Host Controller has a PCI interface, however the configuration cycle is not needed to perform on it. From the point of view of CPU, the access of these registers is transparent just like the memory access. The base address of HC registers is 0x1000B000. HC Register Summary Table 18.22 HC Operational Register Summary Offset...
Page 336: Table 18.23 Hcrevision Register
HcRevision Table 18.23 HcRevision Register Register: HcRevision Offset: 00-03 Bits Reset Description 31 - 8 Reserved. Read/Write 0's 7 - 0 Revision Indicates the OpenHCI Specification revision number implemented by the Hardware. (X.Y = XYh) USB Host Controller supports the 1.0 specification. Rev.
Page 337: Table 18.24 Hccontrol Register
HcControl Table 18.24 HcControl Register Register: HcControl Offset: 04-07 Bits Reset Description 31 - 11 Reserved. Read/Write 0's RemoteWakeupConnectedEnable If a remote wakeup signal is supported, this bit is used to enable that operation. Since there is no remote wakeup signal supported, this bit is ignored.
Page 338: Table 18.25 Hccommandstatus Register
Table 18.24 HcControl Register (cont’d) Register: HcControl Offset: 04-07 Bits Reset Description PeriodicListEnable When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame. 1 - 0 ControlBulkServiceRatio Specifies the number of Control Endpoints serviced for every...
Page 339: Table 18.26 Hcinterruptstatus Register
HcInterruptStatus All bits are set by hardware and cleared by software. Table 18.26 HcInterruptStatus Register Register: HcInterruptStatus Offset: 0C-0F Bits Reset Description Reserved. Read/Write 0's OwnershipChange This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. 29 - 7 Reserved.
Page 340: Table 18.27 Hcinterrutpenable Register
HcInterruptEnable Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ to a bit leaves the bit unchanged. Table 18.27 HcInterrutpEnable Register Register: HcInterruptEnable Offset: 10-13 Bits Reset Description MasterInterruptEnable This bit is a global interrupt enable. A write of ‘1’ allows interrupts to be enabled via the specific enable bits listed above.
Page 341: Table 18.28 Hcinterruptdisable Register
HcInteruptDisable Writing a ‘1’ to a bit in this register clears the corresponding bit, while writing a ‘0’ to a bit leaves the bit unchanged. Table 18.28 HcInterruptDisable Register Register: HcInterruptDisable Offset: 14-17 Bits Reset Description MasterInterruptEnable This bit is a global interrupt disable. A write of ‘1’ disables all interrupts.
Page 342: Table 18.29 Hchcca Register
HcHCCA Table 18.29 HcHCCA Register Register: HcHCCA Offset: 18-1B Bits Reset Description 31 - 8 HCCA Pointer to HCCA base address. (Within SRAM memory space) 7 - 0 Reserved. Read/Write 0's HcPeriodCurrntED Table 18.30 HcPeriodCurrentED Register Register: HcPeriodCurrentED Offset: 1C-1F Bits Reset Description...
Page 343: Table 18.32 Hccontrolcurrented Register
HcControlCurrentED Table 18.32 HcControlCurrentED Register Register: HcControlCurrentED Offset: 24-27 Bits Reset Description 31 - 4 ControlCurrentED Pointer to the current Control List ED. (Within SRAM memory space) 3 - 0 Reserved. Read/Write 0's HcBulkHeadED Table 18.33 HcBulkHeadED Register Register: HcBulkHeadED Offset: 28-2B Bits Reset...
Page 344: Table 18.35 Hcdonehead Register
HcDoneHead Table 18.35 HcDoneHead Register Register: HcDoneHead Offset: 30-33 Bits Reset Description 31 - 4 DoneHead Pointer to the current Done List Head ED. (Within SRAM memory space) 3 - 0 Reserved. Read/Write 0's HcFmInterval Table 18.36 HcFmInterval Register Register: HcFmInterval Offset: 34-37 Bits Reset...
Page 345: Table 18.37 Hcframeremaining Register
HcFrameRemaining Table 18.37 HcFrameRemaining Register Register: HcFrameRemaining Offset: 38-3B Bits Reset Description FrameRemainingToggle This bit is loaded with FrameIntervalToggle when FrameRemaining is loaded. 30 - 14 Reserved. Read/Write 0's 13 - 0 FrameRemaining This field is a 14 bit decrementing counter used to time a frame. When the Host Controller is in the U state the PERATIONAL...
Page 346: Table 18.40 Hclsthreshold Register
HcLSThreshold Table 18.40 HcLSThreshold Register Register: HcLSThreshold Offset: 44-47 Bits Reset Description 31 - 12 Reserved. Read/Write 0's 11 - 0 LSThreshold This field contains a value used by the Frame Management block to determine whether or not a low speed transaction can be started in the current frame.
Page 347: Table 18.41 Hcrhdescriptora Register
HcRhDescriptorA This register is only reset by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub. These bit should not be written during normal operation. Table 18.41 HcRhDescriptorA Register Register: HcRhDescriptorA Offset: 48-4B Bits Reset Description 31 - 24...
Page 348: Table 18.42 Hcrhdescriptorb Register
HcRhDescriptorB This register is only rest by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub. These bit should not be written during normal operation. Table 18.42 HcRhDescriptorB Register Register: HcRhDescriptorB Offset: 4C-4F Bits Reset Description 31 - 16...
Page 349: Table 18.43 Hcrhstatus Register
HcRhStatus This register is reset by the U state. ESET Table 18.43 HcRhStatus Register Register: HcRhStatus Offset: 50-53 Bits Reset Description (write) ClearRemoteWakeupEnable Writing a '1' to this bit clears DeviceRemoteWakeupEnable. Writing a '1' has no effect. 30 - 18 Reserved.
Page 350: Table 18.44 Hcrhportstatus Register
HcRhPortStatus[1:2] This register is reset by the U state. ESET Table 18.44 HcRhPortStatus Register Register: HcRhPortStatus[1:2] Offset: 54-57,58-5B Bits Reset Description 31 - 21 Reserved. Read/Write 0's PortResetStatusChange This bit indicates that the port reset signal has completed. 0 = Port reset is not complete. 1 = Port reset is complete.
Page 351 Register: HcRhPortStatus[1:2] Offset: 54-57,58-5B Bits Reset Description (read) PortPowerStatus This bit reflects the power state of the port regardless of the power switching mode. 0 = Port power is off. 1 = Port power is on. Note: If NoPowerSwitching is set, this bit is always read as '1'. (write) SetPortPower Writing a '1' sets PortPowerStatus.
Page 352: Section 19 A/D Converter
Section 19 A/D Converter 19.1 Overview The controller includes a 10-bit successive-approximations A/D converter with a wide selection of up to four analog input channels. 19.1.1 Features • A/D converter features are listed below: • 10-bit resolution • Four input channels •...
Page 353: Block Diagram
19.1.2 Block Diagram Module data bus AVcc 10-bit D/A AVss Sample-and- 1.8MHz hold circuit A/D conversion control circuit Comparator 1/2 VDD TMOUT# interrupt signal Figure 19.1 A/D Converter Block Diagram 19.1.3 Input Pins Four analog input pins from AN0 to AN3 are provided. AVcc and AVss are the power supply pins and ground pin respectively for the analog circuits in the A/D converter.
Page 354: Register Configuration
19.1.4 Register Configuration Table 19.2 A/D Converter Registers Address Name Abbreviation Initial Value H'1000E000 A/D data register A ADDRA H’0000 H'1000E002 A/D data register B ADDRB H’0000 H'1000E004 A/D data register C ADDRC H’0000 H'1000E006 A/D data register D ADDRD H’0000 H'1000E008 A/D control/status register...
Page 355: Register Descriptions
19.2 Register Descriptions 19.2.1 A/D Data Registers A to D (ADDRA to ADDRD, ADCAL) The five A/D data registers (ADDRA to ADDRD, ADCAL) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register in correspondence to the selected channel.
Page 356: A/D Control/Status Register (Adcsr)
19.2.2 A/D Control/Status Register (ADCSR) ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H’0000 by a reset and is in STANDBY mode. Bit Name ADF* ADST ADIS* TRGE ADIE SCAN Initial Value *NOTE: Only 0 can be written to clear the flag bits.
Page 357: A/D Calibration Sample Control Register (Adcalcr)
19.2.3 A/D Calibration Sample Control Register (ADCALCR) ADCALCR is a 16-bit write-only register that enables A/D calibration sample conversion. When the calibration sample is enabled, the A/D conversion produces 10-bit data which corresponds to the calibration analog value (½ VDD = ½ x 3.3 Volt). The 10-bit data will be stored into ADCAL register.
Page 358: Operation
19.3 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.3.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion in one channel is required. The A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 359: Figure 19.2 Example Of A/D Converter Operation (Single Mode, Channel 1 Selected)
Set* A D I E A/D conversion Set* Set* starts A D S T Clear* Clear* A D F State of channel 0 Idle (AN0) State of channel 1 Idle Idle Idle (AN1) conversion (1) conversion (2) State of channel 2 Idle (AN2) State of channel 3...
Page 360: Scan Mode (Scan = 1)
19.3.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel (AN0). When two or more channels are selected, the conversion of the second channel (AN1) starts immediately after the first channel finishes the conversion.
Page 361: Figure 19.3 Example Of A/D Converter Operation (Scan Mode, Channels An0 To An2 Selected)
Continuous A/D converison Set* Clear* ADST Clear* A/D conversion time State of channel 0 Idle Idle Idle (AN0) conversion (1) conversion (4) State of channel 1 Idle Idle Idle (AN1) conversion (2) conversion (5) State of channel 2 Idle Idle (AN2) conversion (3) State of channel 3...
Page 362: Input Sampling And A/D Conversion Time
19.3.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts the conversion. Figure 19-4 shows the A/D conversion timing.
Page 363: A/D External Trigger Input Timing
unit: µ µ µ µ s Table 19.4 A/D Conversion Time (Single Mode) Symbol Synchronization delay Input sampling time A/D conversion time CONV 19.3.4 A/D External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, the external trigger input is enabled by TMOUT#.
Page 364: Usage Notes
19.5 Usage Notes When using the A/D converter, note the following points: Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ANn should be in the range 0 ≤ ANn ≤ 3.3V. (n = 0 to 3) AVcc and AVss Input Voltages: AVss should have the following value: AVss = Vss.
Page 365: Analog Input Pin Characteristics
19.7 Analog Input Pin Characteristics 1.0K TSMX, TSMY, TSPX, TXPY Figure 19.6 Analog Input Pin RC Equivalent Circuit Table 19.6 Analog Input Pin Characteristics Item Min. Max. Unit Analog Input Capacitance Analog Input Impedance KΩ Rev. 3.0, 03/01, page 346 of 390...
Page 366: Section 20 Electrical Characteristics
Section 20 Electrical Characteristics (VCC =3.3V±0.3V, VCCA, VCCB, VCC5=5.0V±0.5V, Ta=0°C to 70°C, unit : ns) 20.1 DC Electrical Characteristics Absolute Maximum Ratings* • Applied Voltage of VCC ............-0.3V to +4.6V • Applied Voltage of VCC5 ............-0.3V to +7.0V • Applied Voltage of VCCA and VCCB ........-0.3V to +7.0V •...
Page 367 Table 20.1 DC Electrical Characteristics (Ta=0° ° ° ° C to 70° ° ° ° C) [cont’d] Symbol Parameter Min. Typ. Max. Conditions 3.3V Interface Input Low Voltage - 0.3V VCC x 0.2 VCC=3.0 ~ 3.6V Input High Voltage VCC x 0.7 VCC+ 0.3V VCC=3.0 ~ 3.6V Output Low Voltage = -2mA...
Page 368: Ac Characteristics
20.2 AC Characteristics Table 20.2 CPU Interface AC Timing Spec. (unit : ns) Symbol Parameter Min. Comment BS# delay time Figure 20.1 BS# setup time Figure 20.1 BS# hold time Figure 20.1 CS4# setup time Figure 20.1 CS4S Address setup time Figure 20.1 RDWR# setup time Figure 20.1...
Page 369: Table 20-5. I/O Port Interrupt Ac Timing Spec
Table 20.5 I/O Port Interrupt AC Timing Spec. (unit : ns) Symbol Parameter Min. Comment PB0/TMO0# delay time 1 Figure 20.6 TM0D1 PB0/TMO0# delay time 2 Figure 20.6 TM0D2 PB1/TMO1# delay time 1 Figure 20.7 TM1D1 PB1/TMO1# delay time 2 Figure 20.7 TM1D2 IRQ0# delay time 1...
Page 370: Table 20-8. Parallel Port Ac Timing Spec
Table 20.8 Parallel Port AC Timing Spec. (unit : ns) Symbol Parameter Min. Comment Delay from ACK# asserted to IRQ0# asserted Figure 20.13 PPIRQD1 Delay from ACK# deasserted to IRQ0# deasserted Figure 20.13 PPIRQD2 SLIN# deassert to BUSY asserted (EPP write Figure 20.14 PPSLIND1 address cycle)
Page 371: Table 20-10. Afe Interface Ac Timing Spec
Table 20.10 AFE Interface AC Timing Spec. (unit : ns) Symbol Parameter Min. Comment MCLKO Period Figure 20.22 MCKCYC MCLKO Width Low Figure 20.22 MCKL MCLKO Width High Figure 20.22 MCKH MCLKO Falling Time Figure 20.22 MCKF MCLKO Rising Time Figure 20.22 MCKR FS setup Time...
Page 372: Table 20-14. Afeck Clock Input Ac Timing Spec. (Pll1 : Operating)
Table 20.14 AFECK clock input AC Timing Spec. (PLL1 : operating) (unit : ns) Symbol Parameter Comment AFECK clock input cycle time 81.38 Figure 20.26 ACKcyc AFECK clock input high level pulse width Figure 20.26 ACKH AFECK clock input low level pulse width Figure 20.26 ACKL AFECK clock input rise time...
Page 373: Figure 20.1 Cpu Write Cycle Timing Diagram
CKIO CS4# CS4S A [ 25 : 0 ] RDWR# WE0#, WE1#, WE2#, WE3# WTD1x RDY#/WAIT# WTD2x D [ 31 : 0 ] * : x : HS or LS Figure 20.1 CPU Write Cycle Timing Diagram CKIO CS4# A [ 25 : 0 ] RDWR# WE0# WE1#...
Page 374: Figure 20.3 Crystal/Oscillator And Pll Settle Timing Diagrams
*Power-On Reset AFECK, UCK PLL1, PLL2 RESET# PORST RESETPO# *Crystal Standby AFECK, UCK AFEOSC, UCKOSC *PLL Standby PLL1, PLL2 PLL1SB, PLL2SB Figure 20.3 Crystal/Oscillator and PLL Settle Timing Diagrams A [ 25 : 1 ] GPIO pin ( Interrupt ) PxQDF IRQ0# Figure 20.4 I/O Port Interrupt Timing (Falling Edge Trigger)
Page 375: Figure 20.5 I/O Port Interrupt Timing (Rising Edge Trigger)
A [ 25 : 1 ] GPIO pin ( Interrupt ) PxQDR IRQ0# Figure 20.5 I/O Port Interrupt Timing (Rising Edge Trigger) CKIO IRQ0# TMQD1 TMQD2 TMO0# TM0D2 TM0D1 Figure 20.6 IRQ0#/TMO0# Timing For Timer CKIO IRQ0# TMQD1 TMO1# TMQD2 TM1D1 TM1D2 Figure 20.7 IRQ0#/TMO1# Timing For Timer...
Page 376: Figure 20.9 Pcmcia I/O Bus Cycle (No Wait)
CKIO A25-A0 PCCnA25-A0 * CEmx# * PCCnCEmx# * ICIORD#/ ICRSD WE2# ICRSD PCCnIORDx# * ICIOWR#/ ICWSD WE3# ICWSD PCCnIOWRx# * D15-D0 PCCnD15-D0 * : m : 1 or 2 n = 0 or 1 x = A or B Figure 20.9 PCMCIA I/O Bus Cycle (NO Wait) Rev.
Page 377: Figure 20.10 Pcmcia Memory Bus Cycle (No Wait)
CKIO A25-A0 PCCnA25-A0 CEmx# PCCnCEmx# RDx# WEx# D15-D0 PCCnD15-D0 m : 1 or 2 n = 0 or 1 x = A or B Figure 20.10 PCMCIA Memory Bus Cycle (No Wait) CKIO DTR0#, RTS0# URDTRD1 URDTRD2 Figure 20.11 UART DTR, RTS Timing Rev.
Page 378: Figure 20.12 Uart Rx Timing
RXD0 START DATA BITS PARITY STOP URIRQD IRQ0# Figure 20.12 UART Rx Timing ACK# PPIRQD1 PPIRQD2 IRQ0# Figure 20.13 Control Signal Delay Time of Parallel Port Timing A [ 25 : 0 ] D [ 31 : 0 ] RDWR# STB# AFD#(data write cycle) , PPSLIND1...
Page 379: Figure 20.15 Epp Address Or Data Read Timing
A [ 25 : 0 ] D [ 31 : 0 ] AFD#(data read cycle) PPSLIND2 SLIN#(address read cycle) BUSY PPD [ 7 : 0 ] Figure 20.15 EPP Address or Data Read Timing PPD [ 7 : 0 ] AFD# STB# PPSTBD2...
Page 380: Figure 20.18 Scdi Dma Request Timing
CKIO DREQ1D2 DREQ1# DREQ1D1 Figure 20.18 SCDI DMA Request Timing ACRST# RST_LOW SIBCLK Figure 20.19 Cold Reset Timing SIBSYNC SYN_HIGH SIBCLK Figure 20.20 Warm Reset Timing Rev. 3.0, 03/01, page 361 of 390...
Page 381: Figure 20.21 Scdi Sync And Data Timing
SDINSU SIBCLK SIBDIN SDOUTD SDINHD SIBDOUT SYNCD1 SYBSYNC SYNCD2 Figure 20.21 SCDI Sync and Data Timing MCKcyc MCLKO 1/2Vcc 1/2Vcc VIL VIL MCKH MCKL MCKF MCKR SCLK RX Data (DIN) TX Data (DOUT/RLY*) * case TSW = 1 Figure 20.22 AFE Interface Access Timing Rev.
Page 382: Figure 20.23 Keyboard Controller Interface Read Timing
WAIT# KBCS# RCSD IORD IORPW XIOR# Figure 20.23 Keyboard Controller Interface Read Timing WAIT# KBCS# WCSD IOWD IOWPW XIOW# Figure 20.24 Keyboard Controller Interface Write Timing USBOVR# USBPEN# Figure 20.25 USB Over-Current Detect to Power Down Timing ACKcyc ACKH ACKL 1/2Vcc 1/2Vcc ACKf...
Page 383: Figure 20.27 Uck Clock Input Timing
UCKcyc UCKH UCKL 1/2Vcc 1/2Vcc UCKf UCKr Figure 20.27 UCK Clock Input Timing Rev. 3.0, 03/01, page 364 of 390...
Page 384: Section 21 Recommended Reflow Condition
Section 21 Recommended Reflow Condition Time (seconds) Lead Soldering Profile in the IR Oven Limits for IR Reflow Profile Characteristics of Package Leads Characteristics # Characteristic Description Limits Initial Heating Rate of Leads 0.8-1.2°C / Sec. Peak Lead Temperature in Preheat Zone 125°C±20°C Time above 150°C 400 Secs Max...
Page 385 Rev. 3.0, 03/01, page 366 of 390...
Page 386: Section 22 Package Information
Section 22 Package Information unit: mm φ 0.10 φ 0.30 φ ± 0.75 0.15(387X) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 - B- 1.27 31.75 - A- ± 0.15 C 35.00 0.20 0.20(4X) 2.33 ±...
Page 387: Figure 22.2 Hd64465Bq Package Dimensions
unit: mm φ 0.10 φ 0.30 φ ± 0.75 0.15(387X) 20 19 18 17 16 15 14 13 12 11 10 9 - B- 1.27 24.13 - A- ± 27.00 0.20 0.20(4X) 0.15 C 2.33 ± 0.15 24.00 REF. φ 1.00(3X) REF.
Page 388: Section 23 Ordering Information
Section 23 Ordering Information Product Type Mark Code Package 387-pin BGA (35 mm × 35 mm) HD64465 HD64465BP 387-pin BGA (27 mm × 27 mm) HD64465BQ Rev. 3.0, 03/01, page 369 of 390...
Page 389 Rev. 3.0, 03/01, page 370 of 390...
Page 399 On Reset / Active / Standby). (4) Others PCB layout information can be prepared as IBIS model file and Boundary Scan Description Language file by Hitachi Ltd. without any kind of guarantee to work correctly. Rev. 3.0, 03/01, page 380 of 390...
Page 400 (5) HD64465 PIN status list Pin Name Sink Source Destination Sys. Function Type (mA) Req. I - SYSTEM BOARD D D Test Mode U - SYSTEM BOARD - - U - SYSTEM BOARD - - TRST# U - SYSTEM BOARD - -...
Page 401 Pin Name Sink Source Destination Sys. Function Type (mA) Req. PCC0RDY/IRQ0# d d PCC0 RDY(IREQ#) Z Z PCC0BVD1/STSCHG0#I d d PCC0 BVD1(STSCHG#) PCC0BVD2/SPKR0 d d PCC0 BVD2 (SPKR#) PCC0CD1# I I PCC0 CD1# PCC0CD2# I I PCC0 CD2# PCC0VS1# I I PCC0 VS1# PCC0VS2# I I PCC0 VS2# PCC0A25-A0...
Page 402 Pin Name Sink Source Destination Sys. Function Type (mA) Req. VCC1SEL0 POWER SWITCH CONTROLLER VCC1SEL1 POWER SWITCH CONTROLLER VCC1VPP0 POWER SWITCH CONTROLLER VCC1VPP1 POWER SWITCH CONTROLLER TXD0 MAX3243 UART 0 (VCC) RXD0 d d MAX3243 RTS0# MAX3243 CTS0# d d MAX3243 DTR0# MAX3243 DSR0#...
Page 403 Pin Name Sink Source Destination Sys. Function Type (mA) Req. ACCLK Codec CKIN CODEC Interface ACRST# Codec RESET# d d U (VCC) ACPD#/ACIRQ O/I 4 d x Codec IRQ O O Codec PD# d d U/- (4: The I/O SIBCLK d x Codec SCLK Z Z Codec SCLK direction is...
Page 404 Pin Name Sink Source Destination Sys. Function Type (mA) Req. IO Port C (VCC) IO Port D (VCC) IO Port E (VCC) RESETPI# I I SYSTEM BOARD O O System Reset Interface(VCC) RESETMI# I I SYSTEM BOARD O O RESETPO# SYSTEM BOARD RESETMO# SYSTEM BOARD...
Page 405 Note : H : output high state L : output low state Z : high impedance state I : input state U : pull-up state D : pull-down state P : The state is programmed by system software C : input/output function is selected by module. When it is input pin, the state is disable state.
Page 406 (6) HD64465BP Module Clock & Clock Source Relationship Signal Name Description Clock Source Microprocessor Reset Interface RESETPO# Power-On Reset AFECK RESETMO# Manual Reset AFECK AFE Module AFE_clk AFE Interface Clock AFECK AFE_cmd_clk AFE Bus Interface Clock Serial Codec Module SCDI_clk Serial Codec Interfece Clock AFECK/UCK (SCDICKS bit in SCONFR)
Page 407 Driver looses synchronization with the message stream. Description: With a current production version of the Logitech or Microsoft PS/2 mouse connected the HD64465 will set the CLOCK line low before the falling edge of the tenth clock. Rev. 3.0, 03/01, page 388 of 390...
Page 408 When the HD64465 sets the CLOCK line low before the falling edge of the tenth clock it indicates that a complete byte has been received. The mouse sees this as a host request to abort the byte being transmitted. When the host allows the CLOCK line to go high the mouse will send the aborted byte again.
Page 409 Rev. 3.0, 03/01, page 390 of 390...
Page 410 Publication Date: 1st Edition, February 1999 3rd Edition, March 2001 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

Hitachi HD64465 User Manual

Section 1 Features

Section 2 General Description

System Block Diagram

Section 4 Pin Description

Tables

Section 5 Internal CPU Interface

Figures

Section 6 Power Management and System Configuration

Section 7 General Purpose I/O Port

Interrupt Controller (INTC)

Section 9 Timer

Section 10 PC Card Controller (PCC)

Section 11 FIR Module

Section 12 UART

Section 13 Parallel Port

Section 14 Serial CODEC Interface

Section 15 AFE Interface

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Summary of Contents for Hitachi HD64465