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Philips LPC214 Series User Manual

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UM10139
Volume 1: LPC214x User Manual
Rev. 01 — 15 August 2005
Document information
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Content
Keywords
LPC2141, LPC2142, LPC2144, LPC2146, LPC2148, LPC2000, LPC214x,
ARM, ARM7, embedded, 32-bit, microcontroller, USB 2.0, USB device
Abstract
An initial LPC214x User Manual revision
User manual

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Summary of Contents for Philips LPC214 Series

  • Page 1 UM10139 Volume 1: LPC214x User Manual Rev. 01 — 15 August 2005 User manual Document information Info Content Keywords LPC2141, LPC2142, LPC2144, LPC2146, LPC2148, LPC2000, LPC214x, ARM, ARM7, embedded, 32-bit, microcontroller, USB 2.0, USB device Abstract An initial LPC214x User Manual revision...
  • Page 2 Date Description 20050815 Initial version Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 3: Chapter 1: General Information

    Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package. • Up to nine edge or level sensitive external interrupt pins available. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 4: Applications

    ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 5: Arm7Tdmi-S Processor

    ARM processor connected to a 16-bit memory system. The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 6: On-Chip Flash Memory System

    SRAM after a subsequent Reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 7: Block Diagram

    (3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/8 only. (4) LPC2142/4/6/8 only. Fig 1. LPC2141/2/4/6/8 block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 8: Chapter 2: Lpc2141/2/4/6/8 Memory Addressing

    TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2142) 0x0000 8000 0x0000 7FFF TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY 0.0 GB (LPC2141) 0x0000 0000 Fig 2. System memory map © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 9 Both the AHB and VPB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
  • Page 10 VPB peripheries and base addresses VPB peripheral Base address Peripheral name 0xE000 0000 Watchdog timer 0xE000 4000 Timer 0 0xE000 8000 Timer 1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 11: Lpc2141/2142/2144/2146/2148 Memory Re-Mapping And Boot Block

    Table 4. Re-mapping of the interrupts is accomplished via the Memory Mapping Control feature (Section 3.7 “Memory mapping control” on page 26). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 12: Memory Map Concepts And Operating Modes 11 Memory Re-Mapping

    1. To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 13 Details on re-mapping and examples can be found in Section 3.7 “Memory mapping control” on page © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 14 Note: Memory regions are not drawn to scale. Fig 5. Map of lower memory is showing re-mapped and re-mappable areas (LPC2148 with 512 kB Flash) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 15: Prefetch Abort And Data Abort Exceptions

    This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 16: Chapter 3: System Control Block

    More details on ISP and Serial Boot Loader can be found in "Flash Memory System and Programming" chapter on page 291. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 17: Register Description

    Power Control for Peripherals 0x03BE 0xE01F C0C4 VPB Divider VPBDIV VPB Divider Control 0xE01F C100 Reset RSID Reset Source Identification Register 0xE01F C180 Code Security/Debugging © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 18: Crystal Oscillator

    Choosing an oscillation mode as an on-board oscillator mode of operation limits F clock selection to 1 MHz to 30 MHz. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 19 < 130 Ω 25 MHz - 30 MHz 10 pF 18 pF, 18 pF < 50 Ω 20 pF 38 pF, 38 pF 30 pF © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 20: External Interrupt Inputs

    Access Reset Address value EXTINT The External Interrupt Flag Register contains 0xE01F C140 interrupt flags for EINT0, EINT1, EINT2 and EINT3. See Table © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 21: External Interrupt Flag Register (Extint - 0Xe01F C140)

    The same goes for external interrupt handling. More details on power-down mode will be discussed in the following chapters. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 22: Interrupt Wakeup Register (Intwake - 0Xe01F C144)

    (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 23: External Interrupt Mode Register (Extmode - 0Xe01F C148)

    Symbol Value Description Reset value EXTMODE0 0 Level-sensitivity is selected for EINT0. EINT0 is edge sensitive. EXTMODE1 0 Level-sensitivity is selected for EINT1. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 24: External Interrupt Polarity Register (Extpolar - 0Xe01F C14C)

    EXTMODE3). 7:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 25: Multiple External Interrupt Pins

    (one bit of EXTINT) to VIC EXTMODEi VPB Read of EXTINT PCLK PCLK Reset Write 1 to EXTINTi Fig 8. External interrupt logic © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 26: Other System Controls

    Table 3 “ARM exception vector locations” on page 12. The MEMMAP register determines the source of data that will fill this table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 27: Memory Mapping Control Usage Notes

    Watchdog Timer, are dependent on the PLL0 when it is providing the chip clock, accidental changes to the PLL setup could result in unexpected behavior of © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 28: Register Description

    PLL operation. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 29: Pll Control Register (Pll0Con - 0Xe01F C080, Pll1Con - 0Xe01F C0A0)

    Section 3.8.7 “PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED - 0xE01F C0AC)” Section 3.8.3 “PLL Configuration register (PLL0CFG - 0xE01F C084, PLL1CFG - 0xE01F C0A4)” on page 30). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 30: Pll Configuration Register

    3.8.9 “PLL frequency calculation” on page Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 31: Pll Status Register (Pll0Stat - 0Xe01F C088, Pll1Stat - 0Xe01F C0A8)

    PLL interrupt is available only in PLL0, i.e. the PLL that generates the CCLK. USB dedicated PLL1 does not have this capability. 3.8.6 PLL Modes The combinations of PLLE and PLLC are shown in Table © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 32: Pll Feed Register (Pll0Feed - 0Xe01F C08C, Pll1Feed - 0Xe01F C0Ac)

    However, in case USBWAKE = 1 and USB_need_clock = 1 it is not possible to go into Power-down mode and any attempt to set the PD bit will fail, leaving the PLLs in the current state. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 33: Pll Frequency Calculation

    48 MHz clock required by the USB. This limits the selection of F to either 12 MHz, 16 MHz or 24 MHz. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 34: Pll0 And Pll1 Configuring Examples

    Example 2 has illustrated the way PLL1 should be configured. Since PLL0 and PLL1 are independent, the PLL0 can be configured using the approach described in Example 1. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 35: Power Control

    The PCON register contains two bits. Writing a one to the corresponding bit causes entry to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 36: Power Control For Peripherals Register (Pconp - 0Xe01F Coc4)

    These peripherals may contain a separate disable control that turns off © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 37 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. PUSB USB power/clock control bit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 38: Power Control Usage Notes

    The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 39: Reset Source Identification Register (Rsir - 0Xe01F C180)

    Assertion of the RESET signal sets this bit. This bit is cleared by POR, see text but is not affected by WDT or BOD reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 40: Vpb Divider

    Reset value reflects the data stored in used bits only. It does not include reserved bits content. 3.11.2 VPBDIV register (VPBDIV - 0xE01F C100) The VPB Divider register contains two bits, allowing three divider values, as shown in Table © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 41: Wakeup Timer

    The Wakeup Timer design then ensures that any other required chip functions will be operational prior to the beginning of program execution. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 42: Brown-Out Detection

    Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 43: Code Security Vs. Debugging

    Details on the way Code Read Protection works can be found in the "Flash Memory System and Programming" chapter on page 291. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 44: Chapter 4: Memory Acceleration Module (Mam)

    If the same branch is taken again, the next instruction is taken from the Branch Trail Buffer. When a branch outside the contents of © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 45: Mam Blocks

    Memory Address Flash Memory Bank ARM Local Bus INTERFACE BUFFERS Memory Data Fig 12. Simplified block diagram of the Memory Accelerator Module (MAM) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 46: Instruction Latches And Data Latches

    Instruction prefetch is enabled. Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 47: Mam Configuration

    4.6 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 48: Mam Control Register

    3 - MAM fetch cycles are 3 CCLKs in duration 4 - MAM fetch cycles are 4 CCLKs in duration 5 - MAM fetch cycles are 5 CCLKs in duration © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 49: Mam Usage Notes

    20 MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 50: Chapter 5: Vectored Interrupt Controller (Vic)

    Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell™ Vectored Interrupt Controller (PL190) documentation. 5.3 Register description The VIC implements the registers shown in Table 35. More detailed descriptions follow. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 51 0xFFFF F120 VICVectAddr9 Vector address 9 register. 0xFFFF F124 VICVectAddr10 Vector address 10 register. 0xFFFF F128 VICVectAddr11 Vector address 11 register. 0xFFFF F12C © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 52: Vic Registers

    Table 36: Software Interrupt register (VICSoftInt - address 0xFFFF F018) bit allocation Reset value: 0x0000 0000 Symbol Access © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 53: 0Xffff F01C)

    Writing a 1 clears the corresponding bit in the Software Interrupt r bit allocation register, thus releasing the forcing of this request. table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 54: 0Xffff F008)

    Symbol Access Symbol I2C1 EINT3 EINT2 Access Symbol EINT1 EINT0 SPI1/SSP SPI0 I2C0 PWM0 Access Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 Access © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 55: Interrupt Enable Clear Register (Vicintenclear - 5.6.2

    FIQ or IRQ. Table 46: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit allocation Reset value: 0x0000 0000 Symbol Access © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 56: Irq Status Register (Vicirqstatus -

    31:0 A bit read as 1 indicates a corresponding interrupt request being enabled, VICIRQStatus classified as IRQ, and asserted bit allocation table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 57: Fiq Status Register (Vicfiqstatus - 0Xffff F004)

    IRQ, and asserted. 31:6 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 58: Vector Address Registers 0-15 (Vicvectaddr0-15 - 0Xffff F100-13C)

    The VIC registers can only be accessed in privileged mode. 31:1 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 59: Interrupt Sources

    External Interrupt 2 (EINT2) 0x0001 0000 External Interrupt 3 (EINT3) 0x0002 0000 ADC0 A/D Converter 0 end of conversion 0x0004 0000 SI (state change) 0x0008 0000 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 60 Priority2 Vector interrupt 15 Priority14 VECTIRQ15 DEFAULT VECTORADDR VECTADDR15[31:0] [31:0] Priority15 nVICIRQIN VICVECTADDRIN[31:0] Fig 13. Block diagram of the Vectored Interrupt Controller (VIC) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 61: Spurious Interrupts

    If an IRQ interrupt is received during execution of the MSR instruction, then the behavior will be as follows: • The IRQ interrupt is latched. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 62: Workaround

    LDMNEFD sp!, {..., pc}^ ; If so, just return immediately. ; The interrupt will remain pending since we haven’t ; acknowledged it and will be reissued when interrupts © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 63: Solution 2: Disable Irqs And Fiqs Using Separate Writes To The Cpsr

    Therefore, if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 64 IRQ’s the following instruction could be placed at 0x0000 0018: LDR pc, [pc,#-0xFF0] This instruction loads PC with the address that is present in VICVectAddr register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 65 UART0 nor SPI0 have generated IRQ request but UART1 and/or I C were the reason, content of VICVectAddr will be identical to VICDefVectAddr. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 66: Lpc2141/2142/2144/2146/2148 Pinout

    P0.14/EINT1/SDA1 LPC2141 P0.25/AD0.4 P1.22/PIPESTAT1 P0.13/MAT1.1 D− P0.12/MAT1.0 P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 P0.8/TXD1/PWM4 002aab733 Fig 14. LPC2141 64-pin package © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 67 P0.14/EINT1/SDA1 LPC2142 P0.25/AD0.4/AOUT P1.22/PIPESTAT1 P0.13/MAT1.1 D− P0.12/MAT1.0 P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 P0.8/TXD1/PWM4 002aab734 Fig 15. LPC2142 64-pin package © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 68: Pin Description For Lpc2141/2/4/6/8

    Fig 16. LPC2144/6/8 64-pin package 6.2 Pin description for LPC2141/2/4/6/8 Pin description for LPC2141/2/4/6/8 and a brief explanation of corresponding functions are shown in the following table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 69 SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave PWM2 — Pulse Width Modulator output 2 EINT2 — External interrupt 2 input © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 70 EINT2 — External interrupt 2 input. AD1.5 — A/D converter 1, input 5. This analog input is always connected to its pin. Available in LPC2144/6/8 only. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 71 AD0.4 — A/D converter 0, input 4. This analog input is always connected to its pin. Aout — D/A converter output. Available in LPC2142/4/6/8 only. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 72 Trace port after reset P1.21/ P1.21 — General purpose digital input/output pin PIPESTAT0 PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 73 , but should be isolated to minimize noise and error. 23, 43, 51 3.3 V Power Supply: This is the power supply voltage for the core and I/O ports. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 74 Low-speed mode only). 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only. Pad provides special analog functionality. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 75: Features

    Table 62 0xE002 C014 register 2. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 76: Pin Function Select Register 0 (Pinsel0 - 0Xe002 C000)

    AD1.0 15:14 P0.7 GPIO Port 0.7 SSEL0 (SPI0) PWM2 EINT2 17:16 P0.8 GPIO Port 0.8 TXD UART1 PWM4 [1][2] Reserved or AD1.1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 77: Pin Function Select Register 1 (Pinsel1 - 0Xe002 C004)

    The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 78 P0.23 GPIO Port 0.23 Reserved Reserved 17:16 P0.24 Reserved Reserved Reserved Reserved 19:18 P0.25 GPIO Port 0.25 AD0.4 [2][3] Reserved or Aout(DAC) Reserved © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 79: Pin Function Select Register 2 (Pinsel2 - 0Xe002 C014)

    0 to bit 2 and/or bit 3 results in loss of debug and/or trace functionality! Changing of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution! © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 80: Pin Function Select Register Values

    Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 81: Chapter 8: General Purpose Input/Output Ports (Gpio)

    Table 65 allow backward compatibility with earlier family devices, using existing code. The functions and relative timing of older GPIO implementations is preserved. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 82 IOSET register. Writing zeroes has no effect. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 83: Gpio Port Direction Register

    Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30. 0x0000 0000 Controlled pin is input. Controlled pin is output. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 84 Fast GPIO Port 0 Direction control Upper half-word register. Bit 0 in 0x0000 (half-word) FIO0DIRU register corresponds to P0.16 ... bit 15 to P0.31. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 85: Fast Gpio Port Mask Register (Fiomask, Port 0: Fio0Mask - 0X3Fff C010 And Port 1:Fio1Mask - 0X3Fff C030)

    Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN registers. When the FIOPIN register is read, this bit will not be updated with the state of the physical pin. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 86: Gpio Port Pin Value Register

    GPIO input, GPIO output, UART receive, and PWM output as selectable functions. Any configuration of that pin will allow its current logic state to be read from the IOPIN register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 87 82, too. Next to providing the same functions as the FIOPIN register, these additional registers allow easier and faster access to the physical port pins. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 88: 0X3Fff C038)

    IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 89 0x3FFF C01A Fast GPIO Port 0 output Set Upper half-word register. Bit 0 in 0x0000 (half-word) FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 90: 0X3Fff C03C)

    Fast GPIO output value Clear bits. Bit 0 in FIO0CLR corresponds to P0.0 ... Bit 0x0000 0000 31 in FIO0CLR corresponds to P0.31. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 91 0x3FFF C03E Fast GPIO Port 1 output Clear Upper half-word register. Bit 0 in 0x0000 (half-word) FIO1CLRU register corresponds to P1.16 ... bit 15 to P1.31. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 92: Gpio Usage Notes

    Solution 2: using 16-bit (half-word) accessible fast GPIO registers FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Solution 3: using 8-bit (byte) accessible fast GPIO registers FIO0PIN1 = 0xA5; © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 93: Writing To Ioset/Ioclr .Vs. Iopin

    /*IO1SET -- slow port1 register*/ r4,=0xE002801C /*IO1CLR -- slow port1 register*/ r5,=0x00100000 /*select slow port 1.20 for toggle*/ /*Generate 2 pulses on the fast port*/ r2,[r0] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 94 MEMCR = 2 and MEMTIM = 3, and VPBDIV = 1 (PCLK = CCLK). Fig 17. Illustration of the fast and slow GPIO access and output showing 3.5 x increase of the pin output frequency © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 95: Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (Uart0)

    UART0 contains registers organized as shown in Table 96. The Divisor Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 96 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 96: UART0 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...

  • Page 97: Uart0 Receiver Buffer Register (U0Rbr - 0Xe000 C000, When Dlab = 0, Read Only)

    (DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches. Details on how to select the right value for U0DLL and U0DLM can be found later on in this chapter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 98: Uart0 Fractional Divider Register (U0Fdr - 0Xe000 C028)

    The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 0 < MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 15 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 99: Uart0 Baudrate Calculation

    0.0640 9/(9+1) 0.0000 2000 0271 0.0000 1/(1+0) 0.0000 2400 0209 0.0320 12/(12+13) 0.0000 3600 015B 0.0640 5/(5+2) 0.0064 4800 0104 0.1600 12/(12+13) 0.0000 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 100: Uart0 Interrupt Enable Register (U0Ier - 0Xe000 C004, When Dlab = 0)

    Enable the RX line status interrupts. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 101: Uart0 Interrupt Identification Register (U0Iir - 0Xe000 C008, Read Only)

    The U0IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 102 These initialization conditions are intended to give the UART0 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 103: Uart0 Fifo Control Register

    Value Description Reset value Word Length 5 bit character length Select 6 bit character length 7 bit character length 8 bit character length © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 104: Uart0 Line Status Register

    Note: A parity error is associated with the character at the top of the UART0 RBR FIFO. Parity error status is inactive. Parity error status is active. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 105: Uart0 Scratch Pad Register

    U0SCR has occurred. Table 109: UART0 Scratch pad register (U0SCR - address 0xE000 C01C) bit description Symbol Description Reset value A readable, writable byte. 0x00 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 106: Uart0 Auto-Baud Control Register (U0Acr - 0Xe000 C020)

    In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UART0 Rx pin (the length of the start bit). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 107: Uart0 Transmit Enable Register (U0Ter - 0Xe000 C030)

    XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 108: Auto-Baud Modes

    After setting the U0DLM/U0DLL the end of auto-baud interrupt U0IIR ABEOInt will be set, if enabled. The U0RSR will now continue receiving the remaining bits of the ”A/a" character. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 109: Architecture

    U0RSR, it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
  • Page 110 Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 111 RXD0 U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 19. UART0 block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 112: Features

    Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external modem. The complement value of this signal is stored in U1MCR[1]. LPC2144/6/8 only. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 113: Register Description

    UART1 contains registers organized as shown in Table 76. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 114 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 113: UART1 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...

  • Page 115: Uart1 Transmitter Holding Register (U1Thr - 0Xe001 0000, When Dlab = 0 Write Only)

    (DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later on in this chapter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 116: Uart1 Fractional Divider Register (U1Fdr - 0Xe001 0028)

    The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 0 < MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 15 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 117: Uart1 Baudrate Calculation

    0.0640 9/(9+1) 0.0000 2000 0271 0.0000 1/(1+0) 0.0000 2400 0209 0.0320 12/(12+13) 0.0000 3600 015B 0.0640 5/(5+2) 0.0064 4800 0104 0.1600 12/(12+13) 0.0000 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 118: Uart1 Interrupt Enable Register (U1Ier - 0Xe001 0004, When Dlab = 0)

    U1IER[3] enables the modem interrupt. The status Status of this interrupt can be read from U1MSR[3:0]. Interrupt Disable the modem interrupt. Enable Enable the modem interrupt. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 119: Uart1 Interrupt Identification Register (U1Iir - 0Xe001 0008, Read Only)

    Note that U1IIR[0] is active low. The pending Pending interrupt can be determined by evaluating U1IIR[3:1]. At least one interrupt is pending. No interrupt is pending. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 120 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 121: Uart1 Fifo Control Register (U1Fcr - 0Xe001 0008)

    U1MSR[3:0]. A U1MSR read will clear the modem interrupt. 10.3.8 UART1 FIFO Control Register (U1FCR - 0xE001 0008) The U1FCR controls the operation of the UART1 RX and TX FIFOs. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 122: Uart1 Line Control Register (U1Lcr - 0Xe001 000C)

    Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. Forced "1" stick parity. Forced "0" stick parity. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 123: Uart1 Modem Control Register (U1Mcr - 0Xe001 0010), Lpc2144/6/8 Only

    UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will only start transmitting if the CTS1 input signal is asserted. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 124 CTS Interrupt Enable bit is set, Delta CTS bit in the U1MSR will be set though. Table 126 lists the conditions for generating a Modem Status interrupt. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 125: Uart1 Line Status Register (U1Lsr - 0Xe001 0014, Read Only)

    U1LSR[0] is set when the U1RBR holds an unread character and is cleared when Ready the UART1 RBR FIFO is empty. (RDR) U1RBR is empty. U1RBR contains valid data. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 126 UART1 FIFO. U1RBR contains no UART1 RX errors or U1FCR[0]=0. UART1 RBR contains at least one UART1 RX error. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 127: Uart1 Modem Status Register (U1Msr - 0Xe001 0018), Lpc2144/6/8 Only

    The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 128: Auto-Baud

    The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn is set and the auto-baud rate measurement counter overflows). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 129: Auto-Baud Modes

    After setting the U1DLM/U1DLL the end of auto-baud interrupt U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the remaining bits of the ”A/a" character. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 130: Uart1 Transmit Enable Register (U1Ter - 0Xe001 0030)

    As soon as TXEn becomes 0, UART1 transmission will stop. Table 131 describes how to use TXEn bit in order to achieve software flow control. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 131: Architecture

    Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 132 RXD1 U1RBR U1RSR U1IER U1INTR U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 23. UART1 block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 133: Chapter 11: I 2 C Interfaces I 2 C0 And I 2 C1

    C-bus (see "The I C-bus specification" description under the heading "Fast-Mode", and notes for the table titled "Characteristics of the SDA and SCL I/O stages © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 134: Pin Description

    1 to enable the I C function. If the AA bit is 0, the I C interface will not © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 135: Master Receiver Mode

    C Data register (I2DAT), and then clear the SI bit. In this case, the data direction bit (R/W) should be 1 to indicate a read. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 136: Slave Receiver Mode

    C function. AA bit must be set to 1 to acknowledge its own slave address or the general call address. The STA, STO and SI bits are set to 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 137: Slave Transmitter Mode

    A = Not acknowledge (SDA high) From Slave to Master S = START Condition P = STOP Condition Fig 29. Format of Slave Transmitter mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 138: I 2 C Implementation And Operation

    Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. The output for I C is a special pad designed to conform to the I C specification. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 139 CONTROL REGISTER & SCL DUTY I2CONCLR I2SCLH CYCLE REGISTERS I2SCLL STATUS STATUS Staus REGISTER DECODER I2STAT Fig 30. I C serial interface block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 140: Address Register, I2Addr

    C will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration. Fig 31. Arbitration procedure © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 141: Serial Clock Generator

    C control register contains bits used to control the following I C block functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 142: Status Decoder And Status Register

    I C control register. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 143: C Control Set Register (I2Conset: I2C0, I2C0Conset - 0Xe001 C000 And I2C1, I2C1Conset - 0Xe005 C000)

    START condition thereafter. If the I interface is in slave mode, an internal STOP condition is generated, but is not transmitted on the bus. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 144: C Control Clear Register (I2Conclr: I2C0, I2C0Conclr - 0Xe001 C018 And I2C1, I2C1Conclr - 0Xe005 C018)

    C interrupt Clear bit. Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 145: (I2Stat: 2 C Status Register

    - address 0xE005 C008) bit description Bit Symbol Description Reset value 7:0 Data This register holds data values that have been received, or are to be transmitted. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 146: I 2 C Slave Address Register

    0 through 400 kHz. Each register value must be greater than or equal to 4. Table 143 gives some examples of I C-bus rates based on PCLK frequency and I2SCLL and I2SCLH values. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 147: Details Of I C Operating Modes

    For each status code, the required software action and details of the following serial transfer are given in tables from Table 148 Table 152. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 148: Master Transmitter Mode

    149. After a repeated start condition (state 0x10), the I C block may switch to the master transmitter mode by loading I2DAT with SLA+W. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 149: Slave Receiver Mode

    AA. This means that the AA bit may be used to temporarily isolate the I C block from the I C-bus. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 150 This number (contained in I2STA) corresponds to a defined state of the I C bus Fig 33. Format and States in the Master Transmitter mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 151 This number (contained in I2STA) corresponds to a defined state of the I C bus Fig 34. Format and States in the Master Receiver mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 152 This number (contained in I2STA) corresponds to a defined state of the I C bus Fig 35. Format and States in the Slave Receiver mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 153: Slave Transmitter Mode

    AA. This means that the AA bit may be used to temporarily isolate the I C block from the I C-bus. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 154 C-bus will be released; not addressed SLA+R/W or Data slave will be entered. bytes. No I2DAT action A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 155 STOP condition will be transmitted; STO flag will be reset. Read data byte STOP condition followed by a START condition will be transmitted; STO flag will be reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 156 DATA byte has been Read data byte Data byte will be received and ACK will received; ACK has be returned. been returned. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 157 Own SLA will be recognized; General call address will be recognized if I2ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 158 Own SLA will be recognized; General call address will be recognized if I2ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 159: Miscellaneous States

    STO flag (no other bits in I2CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 160: Some Special Cases

    In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 161: C-Bus Obstructed By A Low Level On Scl Or Sda

    Table 152. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 162: C State Service Routines

    This section provides examples of operations that must be performed by various I C state service routines. This includes: • Initialization of the I C block after a Reset. • C Interrupt Service © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 163: Initialization

    11.9.2 Start Master Transmit function Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then initiating a Start. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 164: Start Master Receive Function

    ACK bit will be received. 1. Write Slave Address with R/W bit to I2DAT. 2. Write 0x04 to I2CONSET to set the AA bit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 165: State: 0X10

    1. Decrement the Master data counter, skip to step 5 if not the last data byte. 2. Write 0x14 to I2CONSET to set the STO and AA bits. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 166: State: 0X30

    1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 167: State: 0X50

    2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 168: State: 0X70

    1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 169: State: 0X90

    1. Load I2DAT from Slave Transmit buffer with first data byte. 2. Write 0x24 to I2CONSET to set the STA and AA bits. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 170: State: 0Xb8

    1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 171: Chapter 12: Spi Interface (Spi0)

    SSEL signal. When CPHA = 1, the SSEL signal will always go inactive between data transfers. This is not guaranteed when CPHA = 0 (the signal can remain active). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
  • Page 172 At this point, the master can activate the clock, and begin the transfer. The transfer ends when the last clock cycle of the transfer is complete. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 173: General Information

    6. Read the received data from the SPI data register (optional). 7. Go to step 3 if more data is required to transmit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 174: Slave Operation

    SPIF status is active. If the SPI data register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the status register will be activated. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 175: Mode Fault

    This signal is not directly driven by the master. It could be driven by a simple general purpose I/O under software control. On the LPC2141/2/4/6/8 (unlike earlier Philips ARM devices) the SSEL0 pin can be used for a different function when the SPI0 interface is only used in Master mode. For example, pin hosting the SSEL0 function can be configured as an output digital GPIO pin and used to select one of the SPI0 slaves.

  • Page 176: Spi Control Register

    SCK is active high. SCK is active low. MSTR Master mode select. The SPI operates in Slave mode. The SPI operates in Master mode. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 177: Spi Status Register

    Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 178: Spi Data Register (S0Spdr - 0Xe002 0008) 178 Spi Clock Counter Register (S0Spccr - 0Xe002 000C)

    CCLK /VPB divider rate as determined by the VPBDIV register contents. 12.4.5 SPI Interrupt register (S0SPINT - 0xE002 001C) This register contains the interrupt flag for the SPI0 interface. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 179: Architecture

    GENERATOR & DETECTOR SPI Interrupt SPI REGISTER INTERFACE VPB Bus SPI STATE CONTROL SCK_OUT_EN MOSI_OUT_EN OUTPUT MISO_OUT_EN ENABLE LOGIC Fig 41. SPI block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 180: Chapter 13: Ssp Controller (Spi1)

    Any other time, the SSP either holds it in its inactive state, or does not drive it (leaves it in high impedance state). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 181: Bus Description

    13.3.1 Texas Instruments Synchronous Serial (SSI) frame format Figure 42 shows the 4-wire Texas Instruments synchronous serial frame format supported by the SSP module. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 182: Spi Frame Format

    SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is placed on the CLK pin when data is not being transferred. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 183: Spi Format With Cpol=0,Cpha=0

    SCK master clock pin goes HIGH after one further half SCK period. The data is now captured on the rising and propagated on the falling edges of the SCK signal. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 184: Spi Format With Cpol=0,Cpha=1

    For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 185: Spi Format With Cpol = 1,Cpha = 0

    CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 186: Spi Format With Cpol = 1,Cpha = 1

    13.3.8 Semiconductor Microwire frame format Figure 47 shows the Microwire frame format for a single frame. Figure 44 shows the same format when back-to-back frames are transmitted. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 187 SK, after the LSB of the frame has been latched into the SSP. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 188: Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode

    Fig 49. Microwire frame format (continuos transfers) - details 13.4 Register description The SSP contains 9 registers as shown in Table 162. All registers are byte, half word and word accessible. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 189: Ssp Control Register 0 (Sspcr0 - 0Xe006 8000)

    14 bit transfer 1110 15 bit transfer 1111 16 bit transfer Frame Format. Microwire This combination is not supported and should not be used. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 190: Ssp Control Register 1 (Sspcr1 - 0Xe006 8004)

    (MISO). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 191: Ssp Data Register (Sspdr - 0Xe006 8008)

    CPSDVSR This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 192: Ssp Interrupt Mask Set/Clear Register (Sspimsc - 0Xe006 8014)

    This bit is 1 if the Tx FIFO is at least half empty. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 193: Ssp Masked Interrupt Register (Sspmis - 0Xe006 801C)

    Writing a 1 to this bit clears the Receive Timeout interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 194: Chapter 14: Usb Device Controller

    Light Emitting Diode Low Speed Maximum Packet Size Phase Locked Loop Random Access Memory Start of Frame Serial Interface Engine 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 195: Features

    1 to 64 Bulk 8, 16, 32, 64 Bulk 8, 16, 32, 64 Isochronous 1 to 1023 Isochronous 1 to 1023 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 196: Architecture

    Interface Interface Control Engine Register Interface EP_RAM USB Device (2K) (AHB slave) Block Fig 50. USB Device Controller Block Diagram 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 197: Data Flow

    OUT isochronous endpoints, the data will always be written irrespective of the buffer status. There will be no interrupt generated specific to OUT isochronous endpoints other than the frame interrupt. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 198: Dma Mode Transfer (Lpc2146/8 Only)

    DMA related registers are located in the address region 0xE009 0050 to 0xE009 00FC. All unused address in this region reads invalid data. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 199 USB New DD Request Interrupt Status 0x0000 0000 0xE009 00AC USBNDDRIntClr USB New DD Request Interrupt Clear 0x0000 0000 0xE009 00B0 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 200: Usb Device Register Definitions

    Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 201: Usb Device Interrupt Status Register (Usbdevintst - 0Xe009 0000)

    The command code register is empty (New command can be written). CDFULL Command data register is full (Data can be read now). 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 202: Usb Device Interrupt Enable Register (Usbdevinten - 0Xe009 0004)

    The USBDevIntClr is a write only register. Table 180: USB Device Interrupt Clear register (USBDevIntClr - address 0xE009 0008) bit allocation Reset value: 0x0000 0000 Symbol 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 203: Usb Device Interrupt Set Register (Usbdevintset - 0Xe009 000C)

    If the software attempts to set both bits to 1, none of them will be routed to the high priority interrupt line. All enabled endpoint 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 204: Usb Endpoint Interrupt Status Register (Usbepintst - 0Xe009 0030)

    Endpoint 4, Data Received Interrupt bit. EP4TX Endpoint 4, Data Transmitted Interrupt bit or sent a NAK. EP5RX Endpoint 5, Data Received Interrupt bit. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 205: Usb Endpoint Interrupt Enable Register (Usbepinten - 0Xe009 0034)

    EP8TX EP8RX Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 206: Usb Endpoint Interrupt Clear Register (Usbepintclr - 0Xe009 0038)

    '1'). Then hardware will do the following: 1. Clears CDFULL bit of Device Interrupt Status register. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 207: Usb Endpoint Interrupt Set Register (Usbepintset - 0Xe009 003C)

    Table 193: USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xE009 0040) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX EP14TX E14RX EP13TX EP13RX EP12TX EP12RX 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 208: Usb Realize Endpoint Register (Usbreep - 0Xe009 0044)

    Realization of endpoints is a multi-cycle operation. The pseudo code of endpoint realization is shown below. for every endpoint to be realized, 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 209: Ep_Ram Requirements

    Then again, under the above mentioned 3 request sources, write request has got higher priority than read request. Typically, CPU does single word 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 210: Usb Endpoint Index Register (Usbepin - 0Xe009 0048)

    The value read from a reserved bit is not defined. MPS*_EP0 Endpoint index MPS*_EP31 * MPS - Maximum Packet Size Fig 51. USB MaxPacket register array indexing 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 211: Usb Receive Data Register (Usbrxdata - 0Xe009 0018)

    Packet Length register followed by the data write(s) to the Transmit Data register. This register counts the number of bytes transferred from the CPU to the EP_RAM. The 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 212: Usb Control Register (Usbctrl - 0Xe009 0028)

    Section 14.9.13 “Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))” on page 230) command. The endpoint is now ready to accept the next packet. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 213: Usb Command Code Register (Usbcmdcode - 0Xe009 0010)

    See Section 14.9 “Protocol engine command description” on page 222 for details. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 214: Usb Dma Request Status Register (Usbdmarst - 0Xe009 0050)

    DMA Request Status register. The USBDMARClr is a write only register. The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 206). 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 215: Usb Dma Request Set Register (Usbdmarset - 0Xe009 0058)

    DMA is programmed no interrupts are generated to "activate" it. In this case the usage of the DMA Request Set register is useful to manually start the DMA transfer. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 216: Usb Udca Head Register (Usbudcah - 0Xe009 0080)

    DD-EP2-c NULL UDCA Head Register NULL DDP-EP16 Next_DD_pointer Next_DD_pointer DD-EP16-a DD-EP16-b DDP-EP31 Fig 52. UDCA Head register and DMA descriptors 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 217: Usb Ep Dma Status Register (Usbepdmast - 0Xe009 0084)

    Writing 1 to this register will disable the DMA operation for the corresponding endpoint. Writing 0 will have the effect of resetting the DMA_PROCEED flag. The USBEpDMADis is a write only register. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 218: Usb Dma Interrupt Status Register (Usbdmaintst - 0Xe009 0090)

    Setting the bit in this register will cause external interrupt to happen for the bits set in the interrupt status register. The USBDMAIntEn is a read/write register. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 219: Usb End Of Transfer Interrupt Status Register (Usbeotintst - 0Xe009 00A0)

    31) End of Transfer Interrupt request. 0 Ne effect. Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 220: Usb End Of Transfer Interrupt Set Register (Usbeotintset - 0Xe009 00A8)

    Writing 1 into the register will set the corresponding interrupt from the New DD Request Interrupt Status register. Writing 0 will not have any effect. The USBNDDRIntSet is a write only register. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 221: Usb System Error Interrupt Status Register (Usbsyserrintst - 0Xe009 00B8)

    Writing 1 into the register will set the corresponding interrupt from the System Error Interrupt Status register. Writing 0 will not have any effect. The USBSysErrIntSet is a write only register. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 222: Protocol Engine Command Description

    Read 1 byte - 00 FF 02 00 Read Error Status Device 00 FB 05 00 Read 1 byte - 00 FB 02 00 Endpoint Commands 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 223: Set Address

    Control endpoints are always enabled and respond even if the device is not configured, in the default state. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 224: Set Mode

    This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints. This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 225: Read Current Frame Number (Command: 0Xf5, 14.11 Data: Read 1 Or 2 Bytes)

    This bit is set to 1 when the device hasn’t seen any activity on its upstream port for more than 3 ms. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 226: Get Device Status (Command: 0Xfe, Data: Read 1 Byte)

    Different error conditions can arise inside the protocol engine. The Get Error Code command returns the error code which last occurred. The 4 least significant bits form the error code. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 227: Read Error Status (Command: 0Xfb, Data: Read 1 Byte)

    End of packet error. B_OVRN Buffer Overrun. BTSTF Bit stuff error. TGL_ERR Wrong toggle bit in data PID, ignored data. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 228: Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))

    Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 229: Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)

    Unstalls both control endpoints. Stall both control endpoints, unless the Setup Packet bit is set. It is defined only for control OUT endpoints. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 230: Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))

    DD for non-isochronous endpoints are four-word long and isochronous endpoints are five-word long. Total USB RAM required for DD is: Total_USBDDRAM = (No.of_non-ISOendpoints × 4 + No.of_ISOendpoints × 5) 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 231: Next_Dd_Pointer

    Write only in ATLE mode 14.10.1 Next_DD_pointer Pointer to the memory location from where the next DMA descriptor has to be fetched. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 232: Dma_Mode

    Not serviced - No packet has been transferred yet. DD is in the initial position itself. • Being serviced - This status indicates that at least one packet is transferred. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 233: Packet_Valid

    The memory buffer address where the packet size information along with the frame number has to be transferred or fetched. See Figure 55. This is applicable to isochronous endpoints only. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 234: Dma Operation

    (word 0) of the DD and load it to the DDP. The new DDP is written to the UDCA area. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 235: Transferring The Data

    EP DMA Disable register will cause only resetting of the DMA_PROCEED flag without disabling DMA for any endpoint. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 236: Ending The Packet Transfer

    USB packet in Normal mode, but these two transfers may be concatenated in the last USB packet of the first DMA transfer in ATLE mode. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 237 LS byte in position (23:16) of "DMA_buffer_length" field, sets the flag "LS_byte_extracted" to 1 and updates the DD in System memory (since the packet transfer is over). 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 238 DD are sent as a short packet on USB, which marks the End Of Transfer for the Host. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 239: Setting Up The Dma Transfer

    (since this situation is the end of transfer). Also, when the linked DD is valid and buffer length is 0, a short packet will be sent. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 240: Isochronous Endpoint Operation

    An Isochronous endpoint can have only ‘normal completion’ since there is no short packet on Isochronous endpoint and the transfer continues infinitely till a system error occurs. Also, there is no data_over_run detection. 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 241: Isochronous Out Endpoint Operation Example

    0x000A0010 0x80000035 Empty Frame Number Packet_Valid PacketLength 0x60000010 Data memory Packet size memory Fig 55. Isochronous OUT Endpoint operation example 9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 242: Features

    15.4 Pin description Table 236 gives a brief summary of each of the Timer/Counter related pins. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 243: Register Description

    • MAT1.3 (2 pins): P0.18 and P0.20 15.5 Register description Each Timer/Counter contains the registers shown in Table 237. More detailed descriptions follow. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 244 Capture Register 1. See CR0 description. 0xE000 4030 0xE000 8030 T0CR1 T1CR1 Capture Register 2. See CR0 description. 0xE000 4034 0xE000 8034 T0CR2 T1CR2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 245: Interrupt Register (Ir,

    15.5.2 Timer Control Register (TCR, TIMER0: T0TCR - 0xE000 4004 and TIMER1: T1TCR - 0xE000 8004) The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 246: Count Control Register (Ctcr, Timer0: T0Ctcr - 0Xe000 4070 And Timer1: T1Tcr - 0Xe000 8070)

    Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 247: Timer Counter (Tc, Timer0: T0Tc - 0Xe000 4008 And Timer1: T1Tc - 0Xe000 8008)

    Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 248: Match Control Register (Mcr, Timer0: T0Mcr - 0Xe000 4014 And Timer1: T1Mcr - 0Xe000 8014)

    Feature disabled. 15:12 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 249: Capture Registers (Cr0 - Cr3)

    Capture on CAPn.3 rising edge: a sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC. This feature is disabled. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 250: External Match Register (Emr, Timer0: T0Emr - 0Xe000 403C; And Timer1: T1Emr - 0Xe000 803C)

    15:12 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 251: Example Timer Operation

    TCR[0] (counter enable) Iterrupt Fig 57. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 252: Architecture

    MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER * Note: that the capture register 3 cannot be used on TIMER0 Fig 58. Timer block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 253: Chapter 16: Pulse Width Modulator (Pwm)

    (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. It also © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 254 PWM. The portions that have been added to the standard timer block are on the right hand side and at the top of the diagram. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
  • Page 255 Note: this diagram is intended to clarify the function of the PWM rather than to suggest a specific design implementation. Fig 59. PWM block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 256: Rules For Single Edge Controlled Pwm Outputs

    1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 257: Rules For Double Edge Controlled Pwm Outputs

    Output from PWM channel 6. 16.4 Register description The PWM function adds new registers and registers bits as shown in Table 247 below. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 258 PWMTC. In addition, a match between PWMMR5 and the PWMTC clears PWM5 in either single-edge mode or double-edge mode, and sets PWM6 if it is in double-edge mode. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 259: Pwm Interrupt Register (Pwmir - 0Xe001 4000)

    The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter. The function of each of the bits is shown in Table 249. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 260: Pwm Timer Counter

    Counter is reset on the next PCLK. This causes the PWM TC to increment on every PCLK when PWMPR = 0, every 2 PCLKs when PWMPR = 1, etc. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 261: Pwm Match Registers

    PWMTC. This interrupt is disabled. PWMMR3R 1 Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. This feature is disabled © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 262: Pwm Control Register (Pwmpcr - 0Xe001 404C)

    Selects single edge controlled mode for PWM2. PWMSEL3 Selects double edge controlled mode for the PWM3 output. Selects single edge controlled mode for PWM3. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 263: Pwm Latch Enable Register (Pwmler - 0Xe001 4050)

    Write to the PWMLER, setting bits 1 and 2 at the same time. • The altered values will become effective at the next reset of the timer (when a PWM Match 0 event occurs). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 264 Control Register (PWMMCR - 0xE001 4014)”. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 265: Chapter 17: Analog-To-Digital Converter (Adc)

    Analog Power and Ground. These should be nominally the same voltages as V and V , but should be isolated to minimize noise and error. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 266: Register Description

    AD0DR7 AD1DR7 channel 7. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 267: A/D Control Register

    The A/D converter is in power-down mode. 23:22 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 268: A/D Global Data Register (Ad0Gdr - 0Xe003 4004 And Ad1Gdr - 0Xe006 0004)

    ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 269: A/D Global Start Register (Adgsr - 0Xe003 4008)

    The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found in ADSTAT. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 270: A/D Interrupt Enable Register (Adinten, Adc0: Ad0Inten - 0Xe003 400C And Adc1: Ad1Inten - 0Xe006 000C)

    Completion of a conversion on ADC channel 3 will not generate an interrupt. Completion of a conversion on ADC channel 3 will generate an interrupt. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 271: A/D Data Registers

    DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. NA © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 272: Operation

    ADC readings. An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 273: Features

    350 µA. 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 274: Operation

    A pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 275: Features

    CLK1 CCLK TIME ALARM COMPARATORS COUNTERS REGISTERS COUNTER INCREMENT ALARM MASK Counter INTERRUPT ENABLE enables REGISTER INTERRUPT GENERATOR Fig 61. RTC block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 276: Register Description

    RTC is enabled. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 277: Rtc Interrupts

    Writing a zero has no effect. This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 278: Clock Tick Counter Register (Ctcr - 0Xe002 4004)

    If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler, as on earlier devices in the Philips Embedded ARM family. If this bit is 1, the CTC takes its clock from the 32 kHz oscillator that’s connected to the RTCX1 and RTCX2 pins (see Section 19.7 “RTC external 32 kHz...

  • Page 279: Alarm Mask Register (Amr - 0Xe002 4010)

    19.4.9 Consolidated Time register 0 (CTIME0 - 0xE002 4014) The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes, Hours, and Day of Week. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 280: Consolidated Time Register 1 (Ctime1 - 0Xe002 4018)

    The time value consists of the eight counters shown in Table 273 Table 274. These counters can be read or written at the locations shown in Table 274. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 281: Leap Year Calculation

    The interrupt is cleared when a one is written to bit one of the Interrupt Location Register (ILR[1]). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 282: Rtc Usage Notes

    The result is not a continuous output at a constant frequency, some clock periods will be one PCLK longer than others. However, the overall result can always be 32,768 counts per second. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 283: Prescaler Integer Register (Preint - 0Xe002 4080)

    With this prescaler setting, exactly 32,768 clocks per second will be provided to the RTC by counting 2 PCLKs 32,767 times, and 3 PCLKs once. In a more realistic case, the PCLK frequency is 10 MHz. Then, © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 284: Prescaler Operation

    Logic associates each bit in PREFRAC with a combination in the 15-bit Fraction Counter. These associations are shown in the following Table 279. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 285: Rtc External 32 Khz Oscillator Component Selection

    63. Since the feedback resistance is integrated on chip, only a crystal, the capacitances C and C need to be connected externally to the microcontroller. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 286 < 100 kΩ 18 pF, 18 pF 13 pF < 100 kΩ 22 pF, 22 pF 15 pF < 100 kΩ 27 pF, 27 pF © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 287: Chapter 20: Watchdog Timer

    The Watchdog Time-Out Flag (WDTOF) can be examined to determine if the watchdog has caused the reset condition. The WDTOF flag must be cleared by software. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 288: Register Description

    Once the watchdog interrupt is serviced, it can be disabled in the VIC or the watchdog interrupt request will be generated indefinitely. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 289: Watchdog Timer Constant Register (Wdtc - 0Xe000 0004)

    Reset value 31:0 Count Counter timer value. 0x0000 00FF 20.5 Block diagram The block diagram of the Watchdog is shown below in the Figure © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 290 2. WDEN and WDRESET are sticky bits. Once set they can’t be cleared until the watchdog underflows or an external reset occurs. Fig 64. Watchdog block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 291: Chapter 21: Flash Memory System And Programming

    0x7FFF D000. The flash boot loader is designed to run from this © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 292: Criterion For Valid User Code

    ASCII string ("Synchronized<CR><LF>") to the Host. In response to this host should send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 293: Communication Protocol

    Data flow is resumed by sending the ASCII control character DC1 (start). The host should also support the same flow control scheme. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 294: Isp Command Abort

    The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. he user could use this area if RealMonitor based debug is not required. The Flash boot loader does not initialize the stack for RealMonitor. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 295: Boot Process Flowchart

    LPC2141/2/4/6/8 devices containing 32, 64, 128, 256 and 512K bytes of Flash respectively. IAP, ISP, and RealMonitor routines are located in the boot block. The © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 296: Flash Content Protection Mechanism

    Secondly, it encodes data words to be written to the memory. The error correction capability consists of single bit error correction with Hamming code. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 297: Code Read Protection (Crp)

    ISP command can be given by the host. Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go" commands. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 298: Unlock

    CMD_SUCCESS return code. Example "B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 299: Echo

    If the check-sum does not match, the ISP command handler responds with "RESEND<CR><LF>". In response the host should retransmit the bytes. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 300: Read Memory

    "R 1073741824 4<CR><LF>" reads 4 bytes of data from address 0x4000 0000. 21.8.6 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two step process. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 301: Copy Ram To Flash

    Example "C 0 1073774592 512<CR><LF>" copies 512 bytes from the RAM address 0x4000 8000 to the flash address 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 302: Go

    Example "E 2 3<CR><LF>" erases the flash sectors 2 and 3. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 303: Blank Check Sector(S)

    Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>. Description This command is used to read the boot code version number. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 304: Compare

    Command to prepare sector for write operation was WRITE_OPERATION not executed. COMPARE_ERROR Source and destination data not equal. BUSY Flash programming hardware interface is busy. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 305: Iap Commands

    Define pointer to function type, which takes two parameters and returns void. Note the IAP returns the result with the base address of the table residing in R1. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 306 Blank check sector(s) Table 309 Read Part ID Table 310 Read Boot code version Table 311 Compare Table 312 Reinvoke ISP Table 313 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 307: Prepare Sector(S) For Write Operation

    Sector(s)" command causes relevant sectors to be protected again. The boot sector can not be prepared by this command. To prepare a single sector use the same "Start" and "End" sector numbers. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 308: Copy Ram To Flash

    The boot sector can not be erased by this command. To erase a single sector use the same "Start" and "End" sector numbers. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 309: Blank Check Sector(S)

    Result0: 2 bytes of boot code version number in ASCII format. It is to be interpreted as <byte1(Major)>.<byte0(Minor)> Description This command is used to read the boot code version number. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 310: Compare

    Command is executed successfully. INVALID_COMMAND Invalid command. SRC_ADDR_ERROR Source address is not on a word boundary. DST_ADDR_ERROR Destination address is not on a correct boundary. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 311: Jtag Flash Programming Interface

    Debug tools can write parts of the flash image to the RAM and then execute the IAP call "Copy RAM to Flash" repeatedly with proper offset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 312: Chapter 22: Embeddedice Logic

    An example of this would be to set the first breakpoint to 1.For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary Scan Architecture. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 313: Pin Description

    GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 314: Register Description

    JTAG PORT Serial parallel EMBEDDEDICE interface EMBEDDED INTERFACE PROTOCOL CONVERTER Host running ARM7TDMI-S debugger TARGET BOARD Fig 68. EmbeddedICE debug environment block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 315: Chapter 23: Embedded Trace Macrocell (Etm)

    Table 317: ETM configuration Resource number/type Small Pairs of address comparators Data Comparators 0 (Data tracing is not supported) Memory Map Decoders Counters Sequencer Present © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 316: Pin Description

    P1.20/TRACESYNC, and ensure that any external driver connected to P1.20/TRACESYNC is either driving high, or is in high-impedance state, during Reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 317: Register Description

    External Output 1 to 4 Holds the controlling events for each output. WO 110 10xx Reserved 110 11xx Reserved 111 0xxx Reserved 111 1xxx © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 318: Block Diagram

    CONNECTOR TRACE TRACE PORT ANALYZER TRIGGER PERIPHERAL PERIPHERAL CONNECTOR Host running JTAG debugger INTERFACE UNIT EMBEDDEDICE Fig 69. ETM debug environment block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 319: Chapter 24: Realmonitor

    Multi-ICE must place the core into a debug state. While the processor is in this state, which can be millions of cycles, normal program execution is suspended, and interrupts cannot be serviced. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 320: Realmonitor Components

    It uses the EmbeddedICE logic, and communicates with the host using the DCC. For more details on RMTarget functionality, see the RealMonitor Target Integration Guide (ARM DUI 0142A). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 321: How Realmonitor Works

    – Data and Prefetch aborts caused by user foreground application. This indicates an error in the application being debugged. In both cases the host is notified and the user application is stopped. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 322: How To Enable Realmonitor

    A stack for this mode is always required. RealMonitor uses 12 words while processing an undefined instruction exception. 24.4.4 SVC mode RealMonitor makes no use of this stack. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 323: Prefetch Abort Mode

    Interrupt Controller. The easiest way to do this is to write a branch instruction (<address>) into the vector table, where the target of the branch is the start address of the relevant RealMonitor exception handler. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 324: Rmtarget Initialization

    LDR pc, Reset_Address LDR pc, Undefined_Address LDR pc, SWI_Address LDR pc, Prefetch_Address LDR pc, Abort_Address NOP ; Insert User code valid signature here. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 325 ; Return to the original mode. CPSR_c, r0 ; Initialize the stack for user application ; Keep 256 bytes for IRQ mode stack sp,r2,#0x17F ; /********************************************************************* © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 326 ;user interrupt did not happen so call rm_irqhandler2. This handler ;is not aware of the VIC interrupt priority hardware so trick ;rm_irqhandler2 to return here © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...

  • Page 327: Realmonitor Build Options

    I/O. RM_OPT_SAVE_FIQ_REGISTERS=TRUE This option determines whether the FIQ-mode registers are saved into the registers block when RealMonitor stops. RM_OPT_READBYTES=TRUE RM_OPT_WRITEBYTES=TRUE RM_OPT_READHALFWORDS=TRUE © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 328 This option specifies the size, in words, of the data logging FIFO buffer. CHAIN_VECTORS=FALSE This option allows RMTarget to support vector chaining through µHAL (ARM HW abstraction API). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 329 Pulse Width Modulator Random Access Memory SRAM Static Random Access Memory UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus Vector Interrupt Controller VLSI Peripheral Bus © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 330 Philips Semiconductors for any damages resulting from such application. 25.3Trademarks Right to make changes —...
  • Page 331 0xFFFF F100-13C) bit description . 58 Table 29: VPB Divider register (VPBDIV - address Table 54: Default Vector Address register (VICDefVectAddr continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 332 ... . .88 (UOIIR - address 0xE000 C008, read only) continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 333 Table 150:Slave Receiver mode ....156 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 334 Table 198:USB MaxPacketSize register (USBMaxPSize - Table 179:USB Device Interrupt Enable register address 0xE009 004C) bit description ..210 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 335 Table 247:Pulse Width Modulator (PWM) register map . 258 (USBNDDRIntClr - address 0xE009 00B0) bit Table 248:PWM Interrupt Register (PWMIR - address continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 336 0xE002 401C) bit description ... . .280 Table 309:IAP Blank check sector(s) command ..309 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 337 Table 321:Abbreviations ......329 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
  • Page 338 ....... . .153 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...

  • Page 339: Table Of Contents

    PLL Status register (PLL0STAT - 0xE01F C088, PLL1STAT - 0xE01F C0A8) ....31 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 340 0xE002 C004)......77 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
  • Page 341 DLAB = 1) ......115 0xE001 0000, when DLAB = 0 Read Only) . 115 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 342 Initialization routine ....163 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 343 - 0xE006 8014) ..... . 192 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 344 0xE009 004C)......210 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 345 TIMER1: T1IR - 0xE000 8000) ... 245 TIMER1: T1TC - 0xE000 8008) ..247 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 346 Operation ......274 Chapter 19: Real Time Clock continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 347 Sector numbers ..... . . 295 21.8.12 Read Boot code version number ..303 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 15 August 2005...
  • Page 348 Trademarks......330 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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