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Philips P89LPC920 User Manual

80c51 8-bit microcontroller with two-clock core
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INTEGRATED CIRCUITS
USER
MANUAL
P89LPC920/921/922
80C51 8-bit microcontroller with two-clock core
2 KB/4 KB/8 KB 3 V low-power Flash with 256 Byte RAM
2003 Dec 8

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Summary of Contents for Philips P89LPC920

  • Page 1 INTEGRATED CIRCUITS USER MANUAL P89LPC920/921/922 80C51 8-bit microcontroller with two-clock core 2 KB/4 KB/8 KB 3 V low-power Flash with 256 Byte RAM 2003 Dec 8...
  • Page 2 User Manual - Subject to Change Philips Semiconductors 80C51 8-bit microcontroller with two-cycle instructions P89LPC920/921/922 2KB/4KB/8KB Flash with 256 Byte RAM 2003 Dec 8...

  • Page 3: Table Of Contents

    User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 Table of Contents 1. General Description................... 9 Pin configuration...................... 9 20-Pin TSSOP, DIP Package .................. 9 Logic symbol......................9 Pin Descriptions....................... 11 Special Function Registers..................14 Memory organization ....................18 Data RAM arrangement................19 2.
  • Page 4 User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 Mode 0........................42 Mode 1........................42 Mode 2........................43 Mode 3........................43 Mode 6........................43 Timer overflow toggle output ................... 46 8. Real-Time Clock/System Timer..............47 Real-time Clock source ................... 47 Changing RTCS1-0 ....................
  • Page 5 Flash programming and erase................. 93 Using Flash as data storage: IAP-Lite ..............93 In-Circuit Programming (ICP) .................. 97 ISP and IAP capabilities of the P89LPC920/921/922..........97 Boot ROM........................ 98 Power-On reset code execution ................98 Hardware activation of the Boot Loader ..............98 In-System Programming (ISP).................
  • Page 6 User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 2003 Dec 8...
  • Page 7 P89LPC920/921/922 memory map ........
  • Page 8 Watchdog Timer Control Register ......... . . 87 P89LPC920/921/922 Watchdog Timeout Values....... . 88 Watchdog Timer in Watchdog Mode (WDTE = 1).

  • Page 9: General Description

    The P89LPC920/921/922 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC920/921/922 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC920/921/922 in order to reduce component count, board space, and system cost.
  • Page 10 Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Block diagram High Performance LPC920/921/922 CPU 256 Byte 2KB/ 4KB/ 8KB Data RAM Code Flash Internal Bus UART Port 3 Configurable I/Os Port 1 Real-Time Clock/ Configurable I/Os System Timer...

  • Page 11: Pin Descriptions

    Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Pin Descriptions Mnemonic Pin no. Type Name and function P0.0 - P0.7 1, 20, 19, Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset...
  • Page 12 Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Mnemonic Pin no. Type Name and function P1.0 - P1.7 12, 11, Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for 10, 9, 8, (for three pins as noted below.
  • Page 13 Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Mnemonic Pin no. Type Name and function P3.1 Port 3 bit 1. XTAL1 Input to the oscillator circuit and internal clock generator circuits (when selected via the FLASH configuration). It can be a port pin if internal...

  • Page 14: Special Function Registers

    Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Special Function Registers Note: Special Function Registers (SFRs) accesses are restricted in the following ways: 1. User must NOT attempt to access any SFR locations not defined. 2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
  • Page 15 Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Bit Functions and Addresses Reset Value Name Description Address Binary Serial Clock Generator/SCL Duty I2SCLL# 00H 00000000 Cycle Register Low I2STAT# C Status Register STA.4 STA.3 STA.2 STA.1 STA.0 F8H 11111000...
  • Page 16 Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Bit Functions and Addresses Reset Value Name Description Address Binary PSW* Program Status Wword 00H 00000000 PT0AD# Port 0 Digital Input Disable PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 xx00000x RSTSRC# Reset Source Register...
  • Page 17 Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 Notes: SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. Reserved bits, must be written with 0’s. § BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ’0’. If any of them is written if BRGEN = 1, result is unpredictable.

  • Page 18: Memory Organization

    Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. CODE 64 KB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC920/921/922 has 2 KB/ 4 KB/ 8 KB of on-chip Code memory.). 2003 Dec 8...

  • Page 19: Data Ram Arrangement

    Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 DATA RAM ARRANGEMENT The 256 bytes of on-chip RAM is organized as follows: Type Data RAM Size (Bytes) DATA Memory that can be addressed directly and indirectly IDATA Memory that can be addressed indirectly (includes DATA) Table 1-1: On-chip data memory usage.
  • Page 20 Philips Semiconductors User’s Manual - Preliminary - General Description P89LPC920/921/922 2003 Dec 8...

  • Page 21: Clocks

    2. CLOCKS Enhanced CPU The P89LPC920/921/922 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

  • Page 22: On-Chip Rc Oscillator Option

    On-chip RC oscillator option The P89LPC920/921/922 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1%. (Note: the initial value is better than 1%;...

  • Page 23: External Clock Input Option

    Oscillator Clock (OSCCLK) wakeup delay The P89LPC920/921/922 has an internal wakeup timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60-100µs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60-100µs.

  • Page 24: Low Power Select

    Low power select The P89LPC920/921/922 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a ‘1’ to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance.

  • Page 25: Interrupts

    P89LPC920/921/922 3. INTERRUPTS The P89LPC920/921/922 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC920/921/922’s 12 interrupt sources. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1.

  • Page 26: External Interrupt Pin Glitch Suppression

    It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level. If an external interrupt is enabled when the P89LPC920/921/922 is put into Power down or Idle mode, the interrupt occurance will cause the processor to wake up and resume operation.

  • Page 27: Interrupt Sources, Interrupt Enables, And Power Down Wake-Up Sources

    Philips Semiconductors User’s Manual - Preliminary - INTERRUPTS P89LPC920/921/922 BOPD Wakeup (if in RTCF KBIF Power down) ERTC EKBI (RTCCON.1) WDOVF EWDRT CMF2 CMF1 EA (IE0.7) TI & RI/RI ES/ESR Interrupt to CPU EI2C Figure 3-1: Interrupt sources, interrupt enables, and power down wake-up sources...
  • Page 28 Philips Semiconductors User’s Manual - Preliminary - INTERRUPTS P89LPC920/921/922 2003 Dec 8...

  • Page 29: I/O Ports

    4. I/O PORTS The P89LPC920/921/922 has 3 I/O ports: Port 0, Port 1, and Port 3. Ports 0 and 1 are 8-bit ports and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen (see Table 4-1) Table 4-1: .Number of I/O pins available...

  • Page 30: Open Drain Output Configuration

    The quasi-bidirectional port configuration is shown in Figure 4-1. Although the P89LPC920/921/922 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi- bidirectional mode, there will be a current flowing from the pin to V causing extra power consumption.

  • Page 31: Input-Only Configuration

    Port 0 analog functions The P89LPC920/921/922 incorporates two Analog Comparators. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled.

  • Page 32: Additional Port Features

    • Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open drain. Every output on the P89LPC920/921/922 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC920/921/922 Datasheet for detailed specifications.

  • Page 33: Power Monitoring Functions

    POWER MONITORING FUNCTIONS 5. POWER MONITORING FUNCTIONS The P89LPC920/921/922 incorporates power monitoring functions designed to prevent incorrect operation during initial power- on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect.

  • Page 34: Power-On Detection

    (UCFG1.5) is programmed, BOF (RSTSRC.5) will be set when POF is set. If BOE is unprogrammed, BOF is meaningless. Power reduction modes The P89LPC920/921/922 supports three different power reduction modes as determined by SFR bits PCON.1-0 (see Table 5-2): 2003 Dec 8...

  • Page 35: Power Reduction Modes

    Power down mode: The Power down mode stops the oscillator in order to minimize power consumption. The P89LPC920/921/922 exits Power down mode via any reset, or certain interrupts - external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and comparator trips.

  • Page 36: Power Control Register (Pcon)

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 POWER MONITORING FUNCTIONS PCON Address: 87h SMOD1 SMOD0 BOPD PMOD1 PMOD0 Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION PCON.7 SMOD1 Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud rate source.

  • Page 37: Power Control Register A (Pcona)

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 POWER MONITORING FUNCTIONS PCONA Address: B5H RTCPD VCPD I2PD Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION PCONA.7 RTCPD Real-time Clock Power down: When ‘1’, the internal clock to the Real-time Clock is disabled.
  • Page 38 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 POWER MONITORING FUNCTIONS 2003 Dec 8...

  • Page 39: Reset

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 RESET 6. RESET The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

  • Page 40: Reset Vector

    Reset vector Following reset, the P89LPC920//921/922 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address =00h. The Boot address will be used if a UART break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device has been...

  • Page 41: Timers 0 And 1

    7. TIMERS 0 AND 1 The P89LPC920/921/922 has two general-purpose counter/timers which are upward compatible with the 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters (see Figure 7-1). An option to automatically toggle the Tx pin upon timer overflow has been added.

  • Page 42: Mode 0

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 TIMERS 0 AND 1 TAMOD T1M2 T0M2 Address: 8Fh Not bit addressable Reset Source(s): Any reset Reset Value: xxx0xxx0B SYMBOL FUNCTION TAMOD.7-5 Reserved for future use. Should not be set to 1 by user programs.

  • Page 43: Mode 2

    TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P89LPC920/921/922 device can look like it has three Timer/Counters.

  • Page 44: Timer/Counter 0 Or 1 In Mode 0 (13-Bit Counter)

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 TIMERS 0 AND 1 TCON Address: 88h Bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION TCON.7 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt is processed, or by software (except in mode 6, see above, when it is cleared in hardware).

  • Page 45: Timer/Counter 0 Or 1 In Mode 1 (16-Bit Counter)

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 TIMERS 0 AND 1 Overflow C/T = 0 PCLK Interrupt (8-bits) (8-bits) Tn Pin Control C/T = 1 Toggle Gate Tn Pin INTn Pin ENTn Figure 7-5: Timer/Counter 0 or 1 in Mode 1 (16-bit counter)

  • Page 46: Timer Overflow Toggle Output

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 TIMERS 0 AND 1 C/T = 0 PCLK Overflow Interrupt (8-bits) Control Reload THn on falling transition and (256-THn) on rising transition Toggle Gate Tn Pin INTn Pin (8-bits) ENTn Figure 7-8: Timer/Counter 0 or 1 in Mode 6 (PWM auto-reload) Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs.

  • Page 47: Real-Time Clock/System Timer

    8. REAL-TIME CLOCK/SYSTEM TIMER The P89LPC920/921/922 has a simple Real-time Clock/System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The Real-time Clock can be an interrupt or a wake-up source (see Figure 8-1). The Real-time Clock is a 23-bit down counter.

  • Page 48: Real-Time Clock Interrupt/Wake Up

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 REAL-TIME CLOCK/SYSTEM TIMER Real-time Clock interrupt/wake up If ERTC (RTCCON.1), EWDRT (IEN1.0.6) and EA (IEN0.7) are set to ‘1’, RTCF can be used as an interrupt source. This interrupt vector is shared with the watchdog timer. It can also be a source to wake up the device.
  • Page 49 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 REAL-TIME CLOCK/SYSTEM TIMER RTCCON Address: D1h RTCF RTCS1 RTCS0 ERTC RTCEN Not bit addressable Reset Source(s): Power-up only Reset Value: 011xxx00B SYMBOL FUNCTION RTCCON.7 RTCF Real-time Clock Flag. This bit is set to ‘1’ when the 23-bit Real-time Clock reaches a count of ‘0’.
  • Page 50 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 REAL-TIME CLOCK/SYSTEM TIMER 2003 Dec 8...

  • Page 51: Uart

    UART 9. UART The P89LPC920/921/922 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC920/921/922 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator.

  • Page 52: Baud Rate Generator And Selection

    Baud Rate Generator and selection The P89LPC920/921/922 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a value programmed into the BRGR1 and BRGR0 SFRs. The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON.2-1 (see Figure 9-2).

  • Page 53: Framing Error

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART BRGCON Address: BDh SBRGS BRGEN Not bit addressable Reset Source(s): Any reset Reset Value: xxxxxx00B SYMBOL FUNCTION BRGCON.7-2 Reserved for future use. Should not be set to 1 by user programs.
  • Page 54 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART SCON Address: 98h SM0/FE Bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION SCON.7 SM0/FE The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit is read and written as SM0, which with SM1, defines the serial port mode.

  • Page 55: More About Uart Mode 0

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART SSTAT Address: BAh Not bit addressable DBMOD INTLO CIDIS DBISEL STINT Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION SSTAT.7 DBMOD Double buffering mode. When set = 1 enables double buffering. Must be ‘0’ for UART mode 0.

  • Page 56: More About Uart Mode 1

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 Write to SBUF Shift Transmit RxD (Data Out) TxD (Shift Clock) Write to SCON (Clear RI) Receive Shift...

  • Page 57: More About Uart Modes 2 And 3

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART More about UART Modes 2 and 3 Reception is the same as in Mode 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.

  • Page 58: Double Buffering

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART bit. The break detect bit is cleared in software or by a reset. The break detect can be used to reset the device and force the device into ISP mode. This occurs if the UART is enabled and the the EBRR bit (AUXR1.6) is set and a break occurs.

  • Page 59: The 9Th Bit (Bit 8) In Double Buffering (Modes 1, 2 And 3)

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART Write to SBUF Tx Interrupt Single Buffering (DBMOD/SSTAT.7 = 0), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown Write to SBUF Tx Interrupt Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown, No End- ing Tx Interrupt (DBISEL/SnSTAT.4 = 0)

  • Page 60: Multiprocessor Communications

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART 8. The CPU writes to SBUF again. Then: - If INTLO is ‘0’, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data cur- rently in the shifter.
  • Page 61 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000...
  • Page 62 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 UART 2003 Dec 8...

  • Page 63: I2C Interface

    STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I C-bus will not be released. The P89LPC920/921/922 device provides a byte-oriented I C interface. It has four operation modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter Mode and Slave Receiver Mode.

  • Page 64: I2C Data Register

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE C Data register I2DAT register contains the data to be transmitted or the data received. The CPU can read and write to this 8-bit register while it is not in the process of shifting a byte. Thus this register should only be accessed when the SI bit is set. Data in I2DAT remains stable as long as the SI bit is set.
  • Page 65 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE The STA bit is START flag. Setting this bit causes the I C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode.

  • Page 66: I2C Status Register

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE C Status register This is a read-only register. It contains the status code of I C interface. The least three bits are always 0. There are 26 possible status codes. When the code is F8H, there is no relevant information available and SI bit is not set. All other 25 status codes correspond to defined I C states.

  • Page 67: I2C Operation Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 1: I C clock rates selection Bit data rate (Kbit/sec) at f I2SCLL CRSEL 7.373 MHz 3.6865 MHz 1.8433 MHz 12 MHz 6 MHz I2SCLH 3.6 - 922 Kbps 1.8 - 461 Kbps...

  • Page 68: Master Receiver Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Slave Address DATA DATA Data Transferred “0” - Write (n Bytes + Acknowledge “1” - Read A = Acknowledge (SDA low) From Master to Slave A = Not Acknowledge (SDA high)

  • Page 69: Slave Receiver Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Slave Receiver Mode In the Slave Receiver Mode, data bytes are received from a master transmitter. To initialize the Slave Receiver Mode, the user should write the slave address to the Slave Address Register (I2ADR) and the I...
  • Page 70 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Slave Address DATA DATA Data Transferred “0” - Write (n Bytes + Acknowledge “1” - Read A = Acknowledge (SDA low) From Master to Slave A = Not Acknowledge (SDA high)
  • Page 71 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Address Register I2ADR P1.3 Input Comparator Filter P1.3/SDA Output Shift Register Stage I2DAT Bit Counter / Arbitration & CCLK Input Sync Logic Timing Filter P1.2/SCL & Control Logic Interrupt Output...

  • Page 72: Master Transmitter Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 2: Master Transmitter Mode Application software response Status code Status of the Next action taken by I (I2STAT) C-bus hardware hardware to/from I2DAT to I2CON A START condition SLA+W will be transmitted; ACK bit will be...

  • Page 73: Master Receiver Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 2: Master Transmitter Mode(Continued) Application software response Status code Status of the Next action taken by I (I2STAT) C-bus hardware hardware to/from I2DAT to I2CON Data byte will be transmitted;...

  • Page 74: Slave Receiver Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 3: Master Receiver Mode(Continued) Application software response Status code Status of the Next action taken by I (I2STAT) C-bus hardware hardware to/from I2DAT to I2CON No I2DAT action or Repeated START will be transmitted;...
  • Page 75 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 4: Slave Receiver Mode(Continued) Application software response Status code Status of the Next action taken by I (I2STAT) C-bus hardware hardware to/from I2DAT to I2CON Arbitration lost in Data byte will be received and NOT ACK will...
  • Page 76 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 4: Slave Receiver Mode(Continued) Application software response Status code Status of the Next action taken by I (I2STAT) C-bus hardware hardware to/from I2DAT to I2CON Switched to not addressed SLA mode; no...

  • Page 77: Slave Transmitter Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 5: Slave Transmitter Mode Application software response Status code Status of the Next action taken by I (I2STAT) C-bus hardware hardware to/from I2DAT to I2CON Last data byte will be transmitted and ACK...
  • Page 78 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 C INTERFACE Table 5: Slave Transmitter Mode(Continued) Application software response Status code Status of the Next action taken by I (I2STAT) C-bus hardware hardware to/from I2DAT to I2CON Switched to not addressed SLA mode; no...

  • Page 79: Analog Comparators

    11. ANALOG COMPARATORS Two analog comparators are provided on the P89LPC920/921/922. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage).

  • Page 80: Internal Reference Voltage

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 ANALOG COMPARATORS Comparator 1 (P0.4) CIN1A (P0.3) CIN1B CMP1 (P0.6) (P0.5) CMPREF Vref Change Detect CMF1 Interrupt Change Detect CMF2 Comparator 2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) Figure 11-2: Comparator input and output connections Internal reference voltage An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used.

  • Page 81: Comparator Configuration Example

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 ANALOG COMPARATORS Comparators consume power in Power down and Idle modes, as well as in the normal operating mode. This should be taken into consideration when system power consumption is an issue. To minimize power consumption, the user can Power down the comparators by disabling the comparators and setting PCONA.5 to ‘1’, or simply putting the device in Total Power down mode.
  • Page 82 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 ANALOG COMPARATORS ; Return to caller. The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning. 2003 Dec 8...

  • Page 83: Keypad Interrupt (Kbi)

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 KEYPAD INTERRUPT (KBI) 12. KEYPAD INTERRUPT (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks.

  • Page 84: Keypad Interrupt Mask Register (Kbm)

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 KEYPAD INTERRUPT (KBI) KBMASK Address: 86h KBMASK.7 KBMASK.6 KBMASK.5 KBMASK.4 KBMASK.3 KBMASK.2 KBMASK.1 KBMASK.0 Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION KBMASK.7 When set, enables P0.7 as a cause of a Keypad Interrupt.

  • Page 85: 13. Watchdog Timer

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 WATCHDOG TIMER 13. WATCHDOG TIMER The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. The watchdog timer can only be reset by a power-on reset.

  • Page 86: Feed Sequence

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 WATCHDOG TIMER Watchdog Oscillator ÷32 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 PCLK ÷32 ÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096 WDCLK after a watchdog feed sequence WATCHDOG DOWN COUNTER (after one...

  • Page 87: Watchdog Timer Control Register

    • WDL is the value of watchdog load register which can be the range of 0-255. The minimum number of tclks is: (5+0) tclks = (2 )(0+1)+1 = 33 The maximum number of tclks is: (5+7) tclks = (2 )(255+1)+1 = 1,048,577T The following table show sample P89LPC920/921/922 timeout values 2003 Dec 8...

  • Page 88: Watchdog Clock Source

    User’s Manual - Preliminary - Philips Semiconductors P89LPC920/921/922 WATCHDOG TIMER Table 13-2: P89LPC920/921/922 Watchdog Timeout Values. Watchdog Clock Source Timeout Period PRE2-PRE0 WDL in decimal) (in watchdog clock 400KHz Watchdog Oscillator Clock 12MHz CCLK (6MHz CCLK/2 cycles) (Nominal) Watchdog Clock) 82.5µs...

  • Page 89: Watchdog Timer In Timer Mode

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 WATCHDOG TIMER WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog 8-Bit Down Oscillator RESET PRESCALER ÷32 Counter PCLK Watchdog reset can also be caused by an invalid feed sequence, or by...

  • Page 90: Power Down Operation

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 WATCHDOG TIMER WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog 8-Bit Down Oscillator PRESCALER ÷32 Counter Interrupt SHADOW control register REGISTER FOR WDCON PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK WDCON(A7H) Figure 13-4: Watchdog Timer in Timer Mode (WDTE = 0)

  • Page 91: Additional Features

    Timer0 overflow rate. Refer to the Timer/Counters section for details. AUXR1.3 SRST Software Reset. When set by software, resets the P89LPC920/921/922 as if a hardware reset occurred. AUXR1.2 This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register.
  • Page 92 Also, any instruction that reads or manipulates the DPH and DPL registers (the upper and lower bytes of the current DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P89LPC920/921/922 since the part does not have an external data bus.

  • Page 93: 15. Flash Memory

    Flash programming and erase The P89LPC920/921/922 program memory consists 1 KB sectors. Each sector can be further divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.
  • Page 94 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY grammed in a single operation without the need to erase or program any other bytes in the page. IAP-Lite is performed in the application under the control of the microcontroller’s firmware using four SFRs and an internal 64-byte "page register" to facili- tate erasing and programing within unsecured sectors.
  • Page 95 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY similar C-language routine is shown in Figure 15-3. FMCON Address: E4h Not bit addressable Reset Source(s): Any reset Reset Value: SYMBOL FUNCTION FMCON.7-4 Reserved. FMCON.3 High voltage abort. Set if either an interrupt or a brown-out is detected during a program or erase cycle.
  • Page 96 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY ;* Inputs: R3 = number of bytes to program (byte) R4 = page address MSB(byte) R5 = page address LSB(byte) R7 = pointer to data buffer in RAM(byte) ;* Outputs:...

  • Page 97: In-Circuit Programming (Icp)

    The In-Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC920/921/922 through a two-wire serial interface. Philips has made in- circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area.

  • Page 98: Boot Rom

    The P89LPC920/921/922 contains two special Flash elements: the BOOT VECTOR and the Boot Status Bit. Following reset, the P89LPC920/921/922 examines the contents of the Boot Status Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the Boot Status Bit is set to a va one, the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H.

  • Page 99: In-System Programming (Isp)

    :NNAAAARRDD..DDCC<crlf> In the Intel Hex record, the “NN” represents the number of data bytes in the record. The P89LPC920/921/922 will accept up to 64 (40H) data bytes. The “AAAA” string represents the address of the first byte in the record. If there are zero bytes in the record, this field is often set to 0000.

  • Page 100: In-System Programming (Isp) Hex Record Formats

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-2: In-System Programming (ISP) hex record formats Record type Command/data function Program User Code Memory Page :nnaaaa00dd..ddcc Where: = number of bytes to program aaaa = page address dd..dd...
  • Page 101 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-2: In-System Programming (ISP) hex record formats Record type Command/data function Miscellaneous Write Functions :02xxxx02ssddcc Where: xxxx = required field but value is a “don’t care” = subfunction code...
  • Page 102 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-2: In-System Programming (ISP) hex record formats Record type Command/data function Miscellaneous Read Functions :01xxxx03sscc Where xxxx = required field but value is a “don’t care” = subfunction code...
  • Page 103 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-2: In-System Programming (ISP) hex record formats Record type Command/data function Erase Sector/Page :03xxxx04ssaaaacc Where: xxxx = required field but value is a “don’t care” aaaa = sector/page address...

  • Page 104: In-Application Programming Method

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-2: In-System Programming (ISP) hex record formats Record type Command/data function Reset MCU :00xxxx08cc Where: xxxx = required field but value is a “don’t care” = checksum Example: :00000008F8...

  • Page 105: Iap Function Calls

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-3: IAP error status Flag Description Operation Interrupted. Indicates that an operation was aborted due to an interrupt occuring during a program or erase cycle. Security Violation. Set if program or erase operation fails due to security settings. Cycle is aborted.Memory contents are unchanged.
  • Page 106 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-4: IAP function calls IAP function IAP call parameters Input parameters: = 02h = data to write = register address = UCFG1 = reserved = Boot Vector = Status Byte...
  • Page 107 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-4: IAP function calls IAP function IAP call parameters Input parameters: = 03h = register address = UCFG1 = reserved = Boot Vector = Status Byte = reserved = reserved...
  • Page 108 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY Table 15-4: IAP function calls IAP function IAP call parameters Input parameters: = 05h = sector address Return parameter(s): = CRC bits 31:24 Read Sector CRC = CRC bits 23:16...

  • Page 109: User Configuration Bytes

    User configuration bytes A number of user-configurable features of the P89LPC920/921/922 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of an Flash byte UCFG1 shown in Figure 15-...

  • Page 110: User Security Bytes

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY User security bytes This device has three security bits associated with each of its eight sectors, as shown in Figure 6. SECx Address: xxxxh EDISx SPEDISxMOVCDISx Unprogrammed value: 00h SYMBOL FUNCTION SECx.7-3...

  • Page 111: Boot Vector

    Reserved (should remain unprogrammed at zero). BOOTVEC.4-0 Boot Vector. If the Boot Vector is selected as the reset address, the P89LPC920/921/922 will start execution at an address comprised of 00H in the lower eight bits and this BOOTVEC as the upper bits after a reset. (See section "Reset vector" on page 40).
  • Page 112 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 FLASH MEMORY 2003 Dec 8...

  • Page 113: 16. Instruction Set

    Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 INSTRUCTION SET 16. INSTRUCTION SET Table 16-1: Instruction set summary Mnemonic Description Bytes Cycles code ARITHMETIC ADD A,Rn Add register to A 28-2F ADD A,dir Add direct byte to A ADD A,@Ri...
  • Page 114 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 INSTRUCTION SET Mnemonic Description Bytes Cycles code ANL dir,A AND A to direct byte ANL dir,#data AND immediate to direct byte ORL A,Rn OR register to A 48-4F ORL A,dir OR direct byte to A...
  • Page 115 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 INSTRUCTION SET Mnemonic Description Bytes Cycles code MOV dir,#data Move immediate to direct byte MOV @Ri,A Move A to indirect memory F6-F7 MOV @Ri,dir Move direct byte to indirect memory A6-A7 MOV @Ri,#data...
  • Page 116 Philips Semiconductors User’s Manual - Preliminary - P89LPC920/921/922 INSTRUCTION SET Mnemonic Description Bytes Cycles code ACALL addr 11 Absolute jump to subroutine 116F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11...

  • Page 117: 17. Revision History

    User’s Manual - Preliminary - Philips Semiconductors P89LPC920/921/922 REVISION HISTORY 17. REVISION HISTORY 2003 Dec 8 Initial release. 2003 Dec 8...
  • Page 118 User’s Manual - Preliminary - Philips Semiconductors P89LPC920/921/922 REVISION HISTORY 2003 Dec 8...

  • Page 119: 18. Index

    User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 INDEX 18. INDEX Analog comparators 31 configuration 79 configuration example 81 enabling 79 internal reference voltage 80 interrupt 80 power reduction modes 80, 81 Analog comparators and power reduction 31 Block diagram 10...
  • Page 120 User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 INDEX Data EEPROM block fill 9, 21, 25, 29, 33, 39, 41, 47, 51, 63, 79, 83, 85, 91, 93, 113, 117 hardware reset 9, 21, 25, 29, 33, 39, 41, 47, 51, 63, 79, 83, 85, 91, 93, 113, 117...
  • Page 121 User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 INDEX Low power (CLKP) 24 Memory Code 18 Data 18 FLASH code 93 IDATA 18 organization 18 Oscillator high speed option 21 low speed option 21 meduim speed option 21 RC option 22...
  • Page 122 User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 INDEX Real time clock clock sources 47 interrupt/wake up 48 Reset enabling the external reset input pin 39, 109 software reset 91 sources 39 UART break-detect, ISP entry 40 AUXR1 91...
  • Page 123 User Manual - Subject to Change Philips Semiconductors P89LPC920/921/922 INDEX Timer/counters mode 0 42 mode 1 42 mode 2 (8-bit auto reload) 43 mode 3 (seperates TL0 & TH0) 43 mode 6 (8-bit PWM) 43 toggle output 46 TRIM (SFR)
  • Page 124 Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

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