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Philips P89LPC938 User Manual

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UM10119
P89LPC938 User manual
Rev. 03 — 7 June 2005
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P89LPC938
Abstract
Technical information for the P89LPC938 device.
User manual

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  • Page 1 UM10119 P89LPC938 User manual Rev. 03 — 7 June 2005 User manual Document information Info Content Keywords P89LPC938 Abstract Technical information for the P89LPC938 device.
  • Page 2 20050111 Initial version Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 2 of 139...

  • Page 3: Introduction

    P89LPC938 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC938 in order to reduce component count, board space, and system cost.
  • Page 4 P1.5/RST P0.4/CIN1A/KBI4/AD03 P89LPC938FHN P0.5/CMPREF/KBI5 P3.1/XTAL1 P3.0/XTAL2/CLKOUT P0.6/CMP1/KBI6 P1.4/INT1 P0.7/T1/KBI7 P1.3/INT0/SDA 002aab073 Transparent top view Fig 3. P89LPC938 HVQFN28 pin configuration. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 4 of 139...

  • Page 5: Pin Description

    AD03 — ADC0 channel 3 analog input. P0.5/CMPREF/ P0.5 — Port 0 bit 5. KBI5 CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input 5. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 5 of 139...
  • Page 6 V falls below the minimum specified operating voltage. P1.6/OCB P1.6 — Port 1 bit 6. OCB — Output Compare B. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 6 of 139...
  • Page 7 34 for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 7 of 139...
  • Page 8 Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-Down modes. Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...
  • Page 9 OSCILLATOR DIVIDER clock POWER MONITOR (POWER-ON RESET, CRYSTAL ON-CHIP CONFIGURABLE BROWNOUT RESET) OSCILLATOR RESONATOR OSCILLATOR 002aab106 Fig 4. P89LPC938 block diagram. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 9 of 139...

  • Page 10: Special Function Registers

    – ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...
  • Page 11 Table 2: P89LPC938 Special function registers * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 12 Table 2: P89LPC938 Special function registers …continued * indicates SFRs that are bit addressable. Name Description...
  • Page 13 Table 2: P89LPC938 Special function registers …continued * indicates SFRs that are bit addressable. Name Description...
  • Page 14 Table 2: P89LPC938 Special function registers …continued * indicates SFRs that are bit addressable. Name Description...
  • Page 15 Table 2: P89LPC938 Special function registers …continued * indicates SFRs that are bit addressable. Name Description...
  • Page 16 Table 2: P89LPC938 Special function registers …continued * indicates SFRs that are bit addressable. Name Description...
  • Page 17 Table 3: P89LPC938 extended special function registers Name Description SFR addr. Bit functions and addresses...

  • Page 18: Memory Organization

    CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC938 has 8 kB of on-chip Code memory. Table 4: Data RAM arrangement...

  • Page 19: Clocks

    2. Clocks 2.1 Enhanced CPU The P89LPC938 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

  • Page 20: Clock Output

    TRIM register. 2.4 On-chip RC oscillator option The P89LPC938 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ±...

  • Page 21: External Clock Input Option

    (400 kHz −30 % TIMER 0 AND C-BUS UART (P89LPC932A1) TIMER 1 002aaa891 Fig 7. Block diagram of oscillator control. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 21 of 139...

  • Page 22: Oscillator Clock (Oscclk) Wake-Up Delay

    2.9 Low power select The P89LPC938 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further.

  • Page 23: A/D Operating Modes

    Input channels and result registers for fixed channel single, auto scan single, and auto scan continuous conversion modes Result register Input channel Result register Input channel AD0DAT0R/L AD00 AD0DAT4R/L AD04 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 23 of 139...

  • Page 24: Fixed Channel, Continuous Conversion Mode

    After all selected channels have been © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 25: Dual Channel, Continuous Conversion Mode

    Table 10: Conversion mode bits Burst0 SCC0 Scan0 ADC0 conversion mode Single step Fixed channel, single Auto scan, single © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 25 of 139...

  • Page 26: Conversion Start Modes

    8 MSBs have been converted. The boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 27: Clock Divider

    When used as digital I/O these pins are 5 V tolerant. If selected as input signals in ADINS, these pins will be 3V tolerant if the corresponding A/D is enabled and the device is not in power down. Otherwise the pin will remain 5V tolerant. Please refer to the P89LPC938 data sheet for specifications.
  • Page 28 When = 0, BNDI0 will be set only if the AD00 input exceeded the boundary limits. Reserved © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 28 of 139...
  • Page 29 Boundary status register 0 (BNDSTA0 - address FFEDh) bit allocation Symbol BST07 BST06 BST05 BST04 BST03 BST02 BST01 BST00 Reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 29 of 139...

  • Page 30: Interrupts

    This bit is cleared in software by writing a 1 to this bit. 4. Interrupts The P89LPC938 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC938’s 15 interrupt sources.

  • Page 31: Interrupt Priority Structure

    IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in Table The P89LPC938 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.
  • Page 32 IP0H.0, IP0.0 Data EEPROM 0073h EAD (IEN1.7) IP1H.7, IP1.7 A/D converter ADCI0, BNDI1 0083h EADC (IEN2.1) IP2H.1, IP2.1 16 (lowest) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 32 of 139...

  • Page 33: I/O Ports

    5. I/O ports The P89LPC938 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1, and 2 are 8-bit ports and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon...

  • Page 34: Port Configurations

    External RST pin supported Required for a clock frequency above 12 MHz. 5.1 Port configurations All but three I/O port pins on the P89LPC938 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 24.

  • Page 35: Open Drain Output Configuration

    The quasi-bidirectional port configuration is shown in Figure Although the P89LPC938 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V causing extra power consumption.

  • Page 36: Input-Only Configuration

    5.4 Input-only configuration The input port configuration is shown in Figure 12. It is a Schmitt-triggered input that also has a glitch suppression circuit. (Please refer to the P89LPC938 data sheet, Dynamic characteristics for glitch filter specifications). input port data...

  • Page 37: Port 0 And Analog Comparator Functions

    Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open drain. Every output on the P89LPC938 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded.

  • Page 38: Power Monitoring Functions

    P3M2.1 XTAL1 6. Power monitoring functions The P89LPC938 incorporates power monitoring functions designed to prevent incorrect operation during initial power-on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect. 6.1 Brownout detection The Brownout Detect function determines if the power supply voltage drops below a certain level.
  • Page 39 Brownout trip voltage, VBO (see P89LPC938 data sheet, Static characteristics), and is negated when V rises above VBO. If the P89LPC938 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device...

  • Page 40: Power-On Detection

    0 to the bit. Note that if BOE (UCFG1.5) is programmed, BOF (RSTSRC.5) will be set when POF is set. If BOE is unprogrammed, BOF is meaningless. 6.3 Power reduction modes The P89LPC938 supports three different power reduction modes as determined by SFR bits PCON[1:0] (see Table 27).
  • Page 41 Power-down mode: The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC938 exits Power-down mode via any reset, or certain interrupts - external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit (IEN0.7) is set.
  • Page 42 Power-down mode or Total Power-down mode, the I C clock will be disabled regardless of this bit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 42 of 139...

  • Page 43: Reset

    0 to the corresponding bit. More than one flag bit may be set: • During a power-on reset, both POF and BOF are set but the other flag bits are cleared. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 43 of 139...
  • Page 44 0 to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the other flag bits are cleared.) 6:7 - reserved © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 44 of 139...

  • Page 45: Reset Vector

    P89LPC938 User manual 7.1 Reset vector Following reset, the P89LPC938 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00h. The Boot address will be used if a UART break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device has...

  • Page 46: Mode 0

    TRn is a control bit in the Special Function Register TCON (Table 39). The TnGATE bit is in the TMOD register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 46 of 139...

  • Page 47: Mode 1

    Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P89LPC938 device can look like it has three Timer/Counters. Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3.
  • Page 48 C/T = 1 toggle Tn pin Gate INTn pin ENTn 002aaa920 Fig 16. Timer/counter 0 or 1 in mode 1 (16-bit counter). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 48 of 139...

  • Page 49: Timer Overflow Toggle Output

    The same device pins that are used for the T0 and T1 count inputs and PWM outputs are also used for the timer toggle outputs. This function is enabled by © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 50: Real-Time Clock System Timer

    PCLK as the clock source for the timer. 9. Real-time clock system timer The P89LPC938 has a simple Real-time Clock/System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The...

  • Page 51: Real-Time Clock Source

    Medium frequency crystal Medium frequency crystal /DIVM Medium frequency crystal /DIVM Medium frequency crystal Internal RC oscillator Internal RC oscillator © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 51 of 139...
  • Page 52 Internal RC oscillator Table 41: Real-time Clock Control register (RTCCON - address D1h) bit allocation Symbol RTCF RTCS1 RTCS0 ERTC RTCEN Reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 52 of 139...

  • Page 53: Capture/Compare Unit (Ccu)

    Seven interrupts with common interrupt vector (one Overflow, 2xCapture, 4xCompare), safe 16-bit read/write via shadow registers. • Two Capture inputs with event counter and digital noise rejection filter © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 53 of 139...

  • Page 54: Ccu Clock (Ccuclk)

    TL2(low byte) and TH2(high byte). A third 16-bit SFR, TOR2H:TOR2L, determines the overflow reload value. TL2, TH2 and TOR2H, TOR2L will be 0 after a reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...
  • Page 55 CCU prescaler control register, high byte (TPCR2H - address CBh) bit description Bit Symbol Description TPCR2H.0 Prescaler bit 8 TPCR2H.1 Prescaler bit 9 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 55 of 139...

  • Page 56: Output Compare

    Compare Output Action by setting the OCMx1:0 bits in the Capture Compare x Control Register – CCCRx (x = A, B, C, D). When a compare channel is enabled, the user © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.
  • Page 57 CCU Timer Compare/Overflow Update bit TCOU2, in the CCU Control Register 1 - TCR21. The function of this bit depends on whether the timer is running in PWM mode or © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 58: Input Capture

    (from the last ICRxL read) will be in the shadow register). Table 51: Event delay counter for input capture ICECx2 ICECx1 ICECx0 Delay (numbers of edges) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 58 of 139...

  • Page 59: Pwm Operation

    For example, if TOR contains 01FFH, CCU Timer will count: …01FEH, 01FFH, 01FEH,… The flag is set in the counter cycle after the change from TOR to TOR-1. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 60: Alternating Output Mode

    = A, B, C, D ‘ON’ means in the CCUCLK cycle after the event takes place. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 60 of 139...

  • Page 61: Synchronized Pwm Register Update

    Since N ranges in 0 to 15, the CCLK frequency can be in the range of PCLK to Table 53: CCU control register 1 (TCR21 - address F9h) bit allocation Symbol TCOU2 PLLDV.3 PLLDV.2 PLLDV.1 PLLDV.0 Reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 61 of 139...

  • Page 62: Ccu Interrupt Structure

    An interrupt service routine for the CCU can be as follows: 1. Read the priority-encoded value from the TISE2 register to determine the interrupt source to be handled. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...
  • Page 63 Fig 25. Capture/compare unit interrupts. Table 55: CCU interrupt status encode register (TISE2 - address DEh) bit allocation Symbol ENCINT.2 ENCINT.1 ENCINT.0 Reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 63 of 139...
  • Page 64 Cleared by software. TOIF2 CCU Timer Overflow Interrupt Flag bit. Set by hardware on CCU Timer overflow. Cleared by software. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 64 of 139...

  • Page 65: Uart

    CCU Timer Overflow Interrupt Enable bit. 11. UART The P89LPC938 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC938 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator.

  • Page 66: Mode 2

    Baud Rate Generator Control 11.6 Baud Rate generator and selection The P89LPC938 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a value programmed into the BRGR1 and BRGR0 SFRs. The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON[2:1]...

  • Page 67: Updating The Brgr1 And Brgr0 Sfrs

    SCON.7. If SMOD0 is 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are programmed when SMOD0 is logic 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 68: Break Detect

    Mode 1: 8-bit UART Variable (see Table ⁄ ⁄ CCLK CCLK Mode 2: 9-bit UART Mode 3: 9-bit UART Variable (see Table © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 68 of 139...

  • Page 69: More About Uart Mode 0

    When RI is cleared, the reception of the next character will begin. Refer to Figure 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 70: More About Uart Mode 1

    If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 71: More About Uart Modes 2 And 3

    11.13 Framing error and RI in Modes 2 and 3 with SM2 = 1 If SM2 = 1 in modes 2 and 3, RI and FE behaves as in the following table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 72: Break Detect

    4. If there is more data, go to 6, else continue. 5. If there is no more data, then: – If DBISEL is logic 0, no more interrupts will occur. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 73: The 9Th Bit (Bit 8) In Double Buffering (Modes 1, 2, And 3)

    SBUF is written, provided TB8 is updated before that TB8 is shifted out. TB8 must not be changed again until after TB8 shifting has been completed, as indicated by the Tx interrupt. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 74: Multiprocessor Communications

    Note that SM2 has no effect in Mode 0, and must be logic 0 in Mode 1. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 75: Automatic Address Recognition

    2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 76: C Interface

    C interface. It has four operation modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter Mode and Slave Receiver Mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 76 of 139...

  • Page 77: C Data Register

    1:7 I2ADR1:7 7 bit own slave address. When in master mode, the contents of this register has no effect. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 78: C Control Register

    Mode. (2) A data byte has been received while the I C interface is in the addressed Slave Receiver Mode. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 78 of 139...

  • Page 79: C Status Register

    PCLK cycles for SCL = low. The frequency is determined by the following formula: Bit Frequency = f / (2*(I2SCLH + I2SCLL)) PCLK Where f is the frequency of PCLK. PCLK © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 79 of 139...

  • Page 80: C Operation Modes

    STA, STO, and SI bits must be cleared to 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 81: Master Receiver Mode

    For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the possible status codes are 68H, 78H, or B0H. Refer to Table 85 for details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 81 of 139...

  • Page 82: Slave Receiver Mode

    SI bit is set and a valid status code can be read from the Status Register(I2STAT). Refer to Table 86 for the status codes and actions. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 82 of 139...

  • Page 83: Slave Transmitter Mode

    S = START condition from Slave to Master P = STOP condition 002aaa933 Fig 36. Format of Slave Transmitter mode. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 83 of 139...
  • Page 84 SCL DUTY CYCLE REGISTERS I2SCLL STATUS status bus DECODER I2STAT STATUS REGISTER 002aaa899 Fig 37. I C serial interface block diagram. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 84 of 139...
  • Page 85 STO flag will be reset no I2DAT action STOP condition followed by a START condition will be transmitted; STO flag will be reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 85 of 139...
  • Page 86 I2DAT action or 1 STOP condition followed by a START condition will be transmitted; STO flag will be reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 86 of 139...
  • Page 87 Data byte will be received; ACK bit Data has been will be returned received; ACK has been returned © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 87 of 139...
  • Page 88 General call address will be recognized if I2ADR.0 = 1. A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 88 of 139...
  • Page 89 ACK bit will be received transmitted; ACK load data byte Data byte will be transmitted; ACK has been received will be received © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 89 of 139...

  • Page 90: Serial Peripheral Interface (Spi)

    13. Serial Peripheral Interface (SPI) The P89LPC938 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode.
  • Page 91 Table 87: SPI Control register (SPCTL - address E2h) bit allocation Symbol SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 Reset © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 91 of 139...
  • Page 92 Section 13.4 “Mode change on SS”). The SPIF flag is cleared in software by writing a logic 1 to this bit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 92 of 139...
  • Page 93 (see Section 13.4 “Mode change on SS”) to slave. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 93 of 139...

  • Page 94: Configuring The Spi

    SS is selected and is driven low. The MSTR bit will be cleared to logic 0 when SS becomes low. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 95: Additional Considerations For A Slave

    (P2M2.4, P2M1.4 = 00) or quasi-bidirectional (P2M2.4, P2M1.4 = 01). In this case, another master can drive this pin low to select this device as an SPI © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 96: Write Collision

    The Clock Polarity bit, CPOL, allows the user to set the clock polarity. Figure 42 Figure 45 show the different settings of Clock Phase bit CPHA. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 96 of 139...
  • Page 97 SS (if SSIG bit = 0) 002aaa934 (1) Not defined Fig 42. SPI slave transfer format with CPHA = 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 97 of 139...
  • Page 98 SS (if SSIG bit = 0) 002aaa935 (1) Not defined Fig 43. SPI slave transfer format with CPHA = 1. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 98 of 139...
  • Page 99 SS (if SSIG bit = 0) 002aaa936 (1) Not defined Fig 44. SPI master transfer format with CPHA = 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 99 of 139...

  • Page 100: Spi Clock Prescaler Select

    88). 14. Analog comparators Two analog comparators are provided on the P89LPC938. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage).
  • Page 101 2 CMF2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) 002aaa904 Fig 46. Comparator input and output connections. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 101 of 139...

  • Page 102: Internal Reference Voltage

    14.2 Internal reference voltage An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used. Please refer to the P89LPC938 data sheet for specifications 14.3 Comparator input pins Comparator input and reference pins maybe be used as either digital I/O or as inputs to the comparator.

  • Page 103: Comparators Configuration Example

    ;Return to caller. The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 103 of 139...

  • Page 104: Keypad Interrupt (Kbi)

    Pattern in KBPATN to generate the interrupt. When clear, Port 0 has to be not equal to the value of KBPATN register to generate the interrupt. 2:7 - reserved © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 104 of 139...

  • Page 105: Watchdog Timer (Wdt)

    The Watchdog Safety Enable bit, WDSE (UCFG1.4) along with WDTE, is designed to force certain operating conditions at power-up. Refer to Table 101 for details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 105 of 139...

  • Page 106: Feed Sequence

    WDCON and WDL SFRs are loaded to the control register and the 8-bit down counter. Before the feed sequence, any new values written to © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.
  • Page 107 MOV WFEED2,#05Ah ;do watchdog feed part 2 SETB EA ;enable interrupt This sequence assumes that the P89LPC938 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence. If an interrupt was allowed to be serviced and the service routine contained any SFR writes, it would trigger a watchdog reset.
  • Page 108 10.9 ms 1.28 ms 85.5 µs 131,073 327.7 ms 21.8 ms 1,025 2.56 ms 170.8 µs 262,145 655.4 ms 43.7 ms © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 108 of 139...

  • Page 109: Watchdog Clock Source

    Otherwise, the watchdog could become disabled when CCLK turns off. The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 110: Watchdog Timer In Timer Mode

    SHADOW REGISTER WDCON (A7H) PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK 002aaa939 Fig 50. Watchdog Timer in Timer Mode (WDTE = 0). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 110 of 139...

  • Page 111: Power-Down Operation

    This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register. SRST Software Reset. When set by software, resets the P89LPC938 as if a hardware reset occurred. ENT0 When set the P1.2 pin is toggled whenever Timer 0 overflows.

  • Page 112: Software Reset

    18. Data EEPROM The P89LPC938 has 512 bytes of on-chip Data EEPROM that can be used to save configuration parameters. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill).

  • Page 113: Data Eeprom Read

    EIEE or EA is logic 0, the interrupt is disabled, only polling is enabled. 4. Read the Data EEPROM data from the DEEDAT SFR. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 114: Data Eeprom Write

    DEECON register prior to a write to the DEEDAT register. 18.6 Data EEPROM Row Fill A row (64 bytes) can be filled with a predetermined data pattern via polling or interrupt: © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 115: Data Eeprom Block Fill

    Five Flash programming methods are available. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC938 Flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms.

  • Page 116: Flash Programming And Erase

    10-year minimum data retention 19.3 Flash programming and erase The P89LPC938 program memory consists 1 kB sectors. Each sector can be further divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.
  • Page 117 Write the page address in user code memory to FMADRH and FMADRL[7:6], if not previously included when writing the page register address to FMADRL[5:0]. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...
  • Page 118 ;* R7 = pointer to data buffer in RAM(byte) ;* Outputs: ;* R7 = status (byte) ;* C = clear on no error, set on error ;************************************************** LOAD © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 118 of 139...
  • Page 119 FMCON = LOAD; //load command, clears page reg FMADRH = page_hi; // FMADRL = page_lo; //write my page address to addr regs for (i=0;i<64;i=i+1) FMDATA = dbytes[i]; © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 119 of 139...

  • Page 120: In-Circuit Programming (Icp)

    The P89LPC938 contains two special Flash elements: the BOOT VECTOR and the Boot Status Bit. Following reset, the P89LPC938 examines the contents of the Boot Status Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code.

  • Page 121: Hardware Activation Of Boot Loader

    The In-System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC938 through the serial port. This firmware is provided by Philips and embedded within each P89LPC938 device. The Philips In-System Programming facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area.

  • Page 122: Using The In-System Programming (Isp)

    Should an error occur in the checksum, the P89LPC938 will send an ‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed.
  • Page 123 0C= Security Byte 4 0D= Security Byte 5 0E= Security Byte 6 0F= Security Byte 7 10= Clear Configuration Protection Example: :020000020347cc © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 123 of 139...
  • Page 124 = required field but value is a ‘don’t care’ aaaa = sector/page address ss= 01 erase sector = 00 erase page cc = checksum Example: :03000004010000F8 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 124 of 139...

  • Page 125: In-Application Programming (Iap)

    PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H. The IAP calls are shown in Table 114. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 125 of 139...

  • Page 126: Iap Authorization Key

    These configuration bytes include UCFG1, BOOTVEC, and BOOTSTAT. This protection applies to both ISP and IAP modes and does not apply to ICP or parallel programmer modes. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...

  • Page 127: Iap Error Status

    MOVC protected can be programmed but will generate this error after the programming cycle has been completed. 4 to 7 - unused; reads as a logic 0 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 127 of 139...
  • Page 128 0F= Security Byte 7 10 = Clear Configuration Protection Return parameter(s): R7= status Carry= set on error, clear on no error © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 128 of 139...
  • Page 129 R7= 00H (erase page) or 01H (erase sector) R4= sector/page address (MSB) R5=sector/page address (LSB) Return parameter(s): R7= status Carry= set on error, clear on no error © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 129 of 139...

  • Page 130: User Configuration Bytes

    R7= data 19.17 User configuration bytes A number of user-configurable features of the P89LPC938 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of an Flash byte UCFG1 shown in...

  • Page 131: User Security Bytes

    'global' erase command using a commercial programmer. This bit and sector x CANNOT be erased in ISP or IAP modes. 3:7 - reserved © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 131 of 139...

  • Page 132: Boot Vector Register

    0:4 BOOTV[0:4] Boot vector. If the Boot Vector is selected as the reset address, the P89LPC938 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset.
  • Page 133 This bit is set by programming the BOOTSTAT register. This bit is cleared by writing the Clear Configuration Protection (CCP) command in either ICP or parallel programmer modes. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev.

  • Page 134: Instruction Set

    ORL A,#data OR immediate to A ORL dir,A OR A to direct byte ORL dir,#data OR immediate to direct byte © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 134 of 139...
  • Page 135 C8 to CF XCH A,dir Exchange A and direct byte XCH A,@Ri Exchange A and indirect memory C6 to C7 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 135 of 139...
  • Page 136 B6 to B7 DJNZ Rn,rel Decrement register, jnz relative D8 to DF DJNZ dir,rel Decrement direct byte, jnz relative MISCELLANEOUS No operation © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005 136 of 139...

  • Page 137: Disclaimers

    Philips Semiconductors for any the specified use without further testing or modification.

  • Page 138: Table Of Contents

    More about UART Mode 1 ....70 Open drain output configuration ... 35 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 03 — 7 June 2005...
  • Page 139 19.6 ISP and IAP capabilities of the P89LPC938 120 I2SCLL ......79 19.7...

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