Mitsubishi Electric MELSEC Q Series Structured Programming Manual page 69

(d) The following figure shows the examples of index setting and their actual processing
devices.
(With the setting of Z0=20 and Z1=5)
Ladder example
X0
MOV
EN ENO
K20 s
MOV
EN ENO
K-5 s
X1
MOV
EN ENO
s
K2X50Z0
X0
MOV
EN ENO
K20 s
MOV
EN ENO
K-5 s
X1
MOV
EN ENO
s
D0Z0
Figure. 4.6-1 Ladder examples and actual processing devices
(3) 32-bit index setting (for Universal model QCPU (excluding Q00UJCPU), LCPU, and
FXCPU)
For Universal model QCPU (excluding Q00UJCPU) and LCPU, either of the following two
methods can be selected to specify index registers used for a 32-bit index setting.
• Specify a range of index registers used for a 32-bit index setting.
• Specify a 32-bit index setting using 'ZZ'.
For FXCPU, combine index registers V (from V0) and Z (from Z0) for a 32-bit index setting.
32-bit index settings using 'ZZ' can be used for the following CPU modules only.
• QnU(D)(H)CPU with a serial number whose first five digits are '10042' or higher
(excluding Q00UJCPU)
• QnUDE(H)CPU
• QnUDVCPU
• LCPU
d Z0
d Z1
d
K1M38Z1
d Z0
d Z1
d
K3Y12FZ1
Actual processing device
X1
MOV
EN ENO
K2X64 s d K1M33
Description
K2X(50 + 14) = K2X64
K2X50Z0
Converts K20 to a hexadecimal number.
K1M38Z1
K1M(38 - 5) = K1M33
X1
MOV
EN ENO
D20 s d K3Y12A
Description
D (0 + 20) = D20
D0Z0
K3Y12FZ1 K3Y(12F - 5) = K3Y12A
Hexadecimal number
4.6 Index Setting
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