Panasonic FZ-10 Service Manual page 16

Continued (IC120) Continued (IC120)
Pin No. 1/0 Pin Name Comment Pin No. 1/0 Pin Name
Comment
11 I
TSMODEO Factory test signal 0 54 I LQSF Split register active side indicator
12 I
TSMODE1 Factory test signal 1
for VRAM and DRAM (data bits
13 I
PBDIN
Data input from 3D0 controllers
[31 :161)
14
VDD Power supply
15 0 PBCLK Control port clock
55 0 LA10 Address 10 for the left DRAM and
VRAM (data bits [31 :16])
16 0
PBDOUT
Data output to 3D0 controllers
17 0
UNCACKW
Video DMA acknowledge signal
18
GND
Ground
19 I
XACLK
Master audio clock from audio DAG
20 VDD
Power supply
21 0 UNCACKR
Video OMA acknowledge signal
22 0 EXTACKW
Audio DMA write acknowledge
signal
23 0
EXTACKR Audio DMA read acknowledge
signal
24
GNP
Ground
25 I
XVIN Crystal input for video clock
26 0 XVOUT Crystal output for video clock
27
GNP
Ground
56 0 LA9 Address 9 for the left DRAM and
VRAM (data bits [31: 16))
57 0 LAB Address 8 for the left DRAM and
VRAM (data bits [31 :16])
58 VDD
Power supply
59 0 LAO Address O for the left DRAM and
VRAM (data bits [31: 161)
60 0 LA7
Address 7 for the left DRAM and
VRAM (data bits [31 :161)
61 0 LA1 Address 1 for the left DRAM and
VRAM (data bits [31 :161)
62 GND Ground
63 0 LA6 Address 6 for the left DRAM and
VRAM (data bits [31: 161)
64 0 LA2 Address 2 for the left DRAM and
28 0
CLC0
CLCO, 1, 2 indicate the type of
transaction
VRAM (data bits [31: 16])
65 0 LA5 Address 5 for the left DRAM and
29 0 CLC1 CLCO, 1, 2 indicate the type of
transaction
30 0
CLC2 CLCO, 1, 2 indicate the type of
transaction
31
GND
Ground
VRAM (data bits [31 :161)
66 VDD
Power supply
67 0 LA3 Address 3 for the left DRAM and
VRAM (data bits [31 :161)
68 0 LA4 Address 4 for the left DRAM and
32
0 LRAS3* Row address strobe for left DRAM
(data bits [31 : 161)
33 0 LRAS2* Row address strobe for left DRAM
(data bits [31 : 161)
VRAM (data bits [31 :161)
69 0 RRAS3* Row address strobe for right DRAM
(data bits [15:01)
70 GND
Ground
34 0 LRAS1* Row address strobe for left VRAM
(data bits [31: 161)
35 VDD
Power supply
36 I
XV251N
Video clock input from the
on-board clock network
37 0
XV25OUT
Video clock output to the on-board
clock network
38
GND
Ground
39 I
X251N
System clock input
71 0 RRAS2* Row address strobe for right DRAM
(data bits [15:01)
72 0 RRAS1* Row address strobe for right VRAM
(data bits [15:0])
73 0 RRASO* Row address strobe for right VRAM
(data bits [15: 01)
74
VDD
Power supply
75 0
RSC
Serial VRAM clock for the right
VRAM (data bits [15:01)
40 0
X25OUT System clock output
76 0 RSOEO* VRAM serial port control output
41 VDD
Power supply
enable
42
0 LRASO*
Row address strobe for left VRAM
77 GND Ground
(data bits [31 : 161)
78 0 RSOE1* VRAM serial port control output
43
0
LSC
Serial VRAM clock for the left
enable
VRAM (data bits [31 :16))
79 0 RDTOE* Indicator of internal transfer of
44 0 LSOEO* VRAM serial port control output
VRAM (data bits [15:01)
enable
45
GND
Ground
80 0 RDSF Indicator of special function of
VRAM (data bits [15:0])
46 0 LSOE1*
VRAM serial port control output
81
VDD
Power supply
enable
82 0 RCAS* Column address strobe for the right
47
0 LDTOE*
Indicator of internal transfer of
DRAM and VRAM (data bits [15:01)
VRAM (data bits [31: 16])
83 0
RWEL*
Lower byte write enable for the
48 0 LDSF Indicator of special function of
right DRAM
VRAM (data bits [31 :16])
84 0
RWEU*
Upper byte write enable for the
49
VDD
Power supply
right DRAM
50 0
LCAS*
Column address strobe for left
DRAM
and
VRAM
(data bits [31 :161)
85 I RQSF Split register active side indicator
for VRAM and DRAM (data bits
51 0 LWEL* Lower byte write enable for the left
[15:01)
DRAM
86 GND Ground
52 0
LWEU*
Upper byte write enable for the left
81
0 RA10 Address 10 for the right DRAM and
DRAM
VRAM (data bits [15:01)
53
GND
Ground
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