Panasonic FZ-10 Service Manual page 20

I
FZ-10
Continued (IC600) Continued (IC640)
Pin No. 1/0 Pin Name Comment Pin No. 1/0 Pin Name
Comment
50 Out XCMD- External bus command 26 1/0 HD6
Host data 6
51 Out XSTR- External bus strobe 27 1/0 HD7 Host data 7
52 GND Ground
28
vss
Ground
53 lnout XRDY- External bus ready 29 NC No connection
54 lnout XINT- External bus interruot 30 lnout TEC TEC
55 1/0 XD7 External bus data 7
31 Input
MRC MRC
56 1/0 XD6 External bus data 6 32 Out DIR DIR
57 1/0 XD5 External bus data 5 33 Out TCK TCK
58 1/0 XD4 External bus data 4 34 Out OTCF OTCF
59 lnout EN15- Ground 35 Out OTCR OTCR
60 Input EN7- Ground 36 Input IOCTL IOCTL
61 1/0 XD3 External bus data 3 37 lnout ENABLE- Chio selection from Host
62 1/0 XD2 External bus data 2 38 lnout CMD- Command/Data selection from Host
63 GND Ground 39 Input RAMSL DRAM/SRAM selection
64 l/O XD1 External bus data 1
40
vss
Ground
65 1/0 XD0 External bus data 0
41 VDD
Power supply
66 Out IPFLAG0 Comolement flaa outout 42 Input
HWR- Write from Host
67 lnout S1- S1
43 lnout HRD- Read from Host
68 Input S2- S2
44 Out WAIT- Wait to host
69 Input IPFLAG1 Complement flaa input
45 Out DTEN-
Data enable
70 lnout BYTCLK Bvte clock
46 Out STEN- Status enable
71 lnout A15 A15 inout
47 Out EOP- End of process
72 Out A15- A 15 reverse output
48 Out
STPH- STPH
73
VDD
Power supply
49 Out
MDACHG Media chanae sianal
74 Input CDMDCH CD media change 50 Input
SELDRQ Data access mode selection with Host
G tvoe
75 lnout COSTEN- CD status enable
51 Input
RD-
Read from Microprocessor
76 lnout CDDTEN- CD data enable 52 Input WR- Write from Microprocessor
77 lnout CDWAIT- CD wait 53 lnout CS- Chio selection from Microprocessor
78 Out CDHRD- CD drive read
54 lnout RS Reaister selection
79 Out CDHWR- CD drive write
55 VDD Power suoolv
80 Out
CDCMD-
CD command
56
vss
Ground
57 1/0 DO Microprocessor data 0
IC640
58 l/O
D1
Microprocessor data 1
Error Correction
P/N:DA98000KV26V)
59 1/0 D2 Microprocessor data 2
Pin No. l/O Pin Name Comment
60 1/0 D3 Microprocessor data 3
1 Out RA9 Data buffer address 9
61 l/O
D4 Microorocessor data 4
2 Out RA10 Data buffer address 1 0
62 l/O
D5 Microorocessor data 5
3 Out RA11 Data buffer address 11
63 1/0 D6 Microprocessor data 6
4 Out RA12 Data buffer address 12
64 l/O D7 Microprocessor data 7
5 Out RA13 Data buffer address 13
65
vss
Ground
6 Out RA14 Data buffer address 14
66 Out INT- Interrupt to Microprocessor
7 Out RA15 Data buffer address 15
67 Out SWAIT- Wait sianal to SUB CPU
8
vss
Ground
68 lnout TEST0 Test pin
9 l/O 100
Data buffer address 0 ·
69 Input TEST1 Test pin
10 1/0 101 Data buffer address 1
70 lnout TEST2 Test oin
11 1/0 102 Data buffer address 2
71 Input TEST3 Test pin
12 1/0 103 Data buffer address 3
72 Out EXCK Sub code
13 1/0 104 Data buffer address 4
73 lnout WFCK Sub code
14 1/0 105 Data buffer address 5
74 lnout SBSO Sub code
15 1/0 106 Data buffer address 6
75 Input
SCOR Sub code
16 1/0 107 Data buffer address 7
76 VDD Power suooly
17 VDD Power suooly
77 lnout SDATA Serial data
18
vss
Ground
78 lnout BCK Serial data input terminal
19 1/0 HD0 Host data 0
79 Input
LRCK 44.1 kHz strobe sianal
20 1/0 HD1 Host data 1
80 lnout C2PO C2 Pointer
21 1/0 HD2 Host data 2
81
vss
Ground
22
110
HD3 Host data 3
82 Input XTALCK Crystal Oscillator Input
23
vss
Ground
83 Out
XTAL Crvstal Oscillator Outout
24 1/0 HD4 Host data 4
84 Out MCK
XTALCK 1/2 Outout
25 1/0 HD5 Host data 5
85 Input
RESET- RESET
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