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S1D13705 Embedded Memory LCD Controller S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Document Number: X27A-G-005-03.1 Rev. 3.1...
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This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by the use of it.
Introduction 1 Introduction This manual describes the setup and operation of the S5U13705B00C Rev. 1.0 Evaluation Board. Implemented using the S1D13705 Embedded Memory Color LCD Controller, the S5U13705B00C board is designed for the 16-bit ISA bus environment. To accommodate other bus architectures, the S5U13705B00C board also provides CPU/Bus interface connectors.
S5U13705B00C memory/register start address, and enable/disable hardware power save mode. The following settings are recommended when using the S5U13705B00C with the ISA bus. Table 2-1: Configuration DIP Switch Settings...
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No Connection LCD Panel Voltage Selection 5V LCD Panel 3.3V LCD Panel LCDPWR polarity Active low (‘LCDPWR#’) Active high (‘LCDPWR’) = recommended settings (JP1 through JP3 configured for ISA bus support) Seiko Epson Corporation S5U13705B00C Rev 1.0 Evaluation Board Rev. 3.1...
LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR Note 1. Un-used GPIO pins must be connected to IO V 2. Inverse Video is enabled on FPDAT11 by REG[02h] bit 1. Seiko Epson Corporation S5U13705B00C Rev 1.0 Evaluation Board Rev. 3.1...
Connected to the WAIT# signal of the S1D13705 Connected to the CS# signal of the S1D13705 Not connected WE1# Connected to the WE1# signal of the S1D13705 IOVDD Connected to the IOVDD supply of the S1D13705 Seiko Epson Corporation S5U13705B00C Rev 1.0 Evaluation Board Rev. 3.1...
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Connected to the BS# signal of the S1D13705 BUSCLK Connected to the BCLK signal of the S1D13705 Connected to the RD# signal of the S1D13705 Not connected CLKI Connected to the CLKI signal of the S1D13705 Seiko Epson Corporation S5U13705B00C Rev 1.0 Evaluation Board Rev. 3.1...
80K byte display buffer and the 32 byte register set must be memory mapped into the host’s memory space. When using the S5U13705B00C board on an ISA bus system, the board can be configured to map the S1D13705 to one of two memory blocks.
(VGA or Monochrome) the following applies: VGA Display Adapter All VGA display adapters can be used with the S5U13705B00C board if the S1D13705 is mapped to the upper 1M Byte of ISA bus memory, address F00000-F1FFFF. If the S1D13705 is mapped to the address range 0C0000-0D0000, then no VGA or VGA compatible display adapters can be used with the S5U13705B00C board.
A 25.0MHz oscillator (U2, socketed) is provided as the input clock source. However, depending on the LCD resolution , desired frame rate, and power consumtion budget, a lower frequency clock may be required. Seiko Epson Corporation S5U13705B00C Rev 1.0 Evaluation Board Rev. 3.1...
Technical Description 6.6 LCD Panel Voltage Setting The S5U13705B00C board supports both 3.3V and 5V LCD panels through the LCD connector J5. The voltage level is selected by setting jumper J4 to the appropriate position. Refer to Table 2-3: “Jumper Settings,” on page 7 for setting this jumper.
CNF[3:0] and BS#, appropriate external decod- ing logic MUST be used to access the S1D13705. Refer to Table 5-1: “Host Bus Inter- face Pin Mapping,” on page 11 for connection details. Seiko Epson Corporation S5U13705B00C Rev 1.0 Evaluation Board Rev. 3.1...
Sales and Technical Support 10 Sales and Technical Support For more information on Epson Display Controllers, visit the Epson Global website. https://global.epson.com/products_and_drivers/semicon/products/display_controllers/ For Sales and Technical Support, contact the Epson representative for your region. https://global.epson.com/products_and_drivers/semicon/information/support.html Seiko Epson Corporation S5U13705B00C Rev 1.0 Evaluation Board...