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Epson S5U13706B00C User Manual

S1d13706 embedded memory lcd controller
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S1D13706 Embedded Memory LCD Controller
S5U13706B00C Rev. 1.0
Evaluation Board User Manual
Document Number: X31B-G-004-05.1
Rev. 5.1

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Summary of Contents for Epson S5U13706B00C

  • Page 1 S1D13706 Embedded Memory LCD Controller S5U13706B00C Rev. 1.0 Evaluation Board User Manual Document Number: X31B-G-004-05.1 Rev. 5.1...
  • Page 2 This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by the use of it.

  • Page 3: Table Of Contents

    12 Technical Support ........33 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 4 THIS PAGE LEFT BLANK Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 5: Introduction

    Introduction 1 Introduction This manual describes the setup and operation of the S5U13706B00C Rev. 1.0 Evaluation Board. The board is designed as an evaluation platform for the S1D13706 Embedded Memory LCD Controller. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development.

  • Page 6: Features

    Features 2 Features Following are some features of the S5U13706B00C Rev. 1.0 Evaluation Board: • 100-pin TQFP S1D13706F00A Embedded Memory LCD Controller with 80K bytes of embedded SRAM. • Headers for connecting to various Host Bus Interfaces. • Configuration options.

  • Page 7: Installation And Configuration

    Installation and Configuration 3 Installation and Configuration The S5U13706B00C is designed to support as many platforms as possible. The S5U13706B00C incorporates a DIP switch and seven jumpers which allow both evaluation board and S1D13706 LCD controller to be configured for a specified evaluation platform.
  • Page 8 • GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1. • GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0. • Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1. Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 9: Configuration Jumpers

    Refer to the S1D13706 Hardware Functional Specification, document number X28B-A-001-xx for details. Note When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no jumper and JP6 must be set to position 2-3. GPIO0 connected GPIO0 disconnected...
  • Page 10 Position 1-2 sets the CLKI2 source to VCLKOUT from the Cypress clock synthesizer (default setting). Position 2-3 sets the CLKI2 source to the external oscillator at U6. External VCLKOUT Oscillator (U6) Figure 3-4: Configuration Jumper (JP3) Location Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 11 Position 1-2 selects software control of the contrast adjustment. Position 2-3 selects manual control of the contrast adjustment using potentiometer R24 (default setting). Manual Software Control Control Figure 3-6: Configuration Jumper (JP5) Location Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 12 Position 1-2 sets the voltage level to 5.0V (default setting). Position 2-3 sets the voltage level to 3.3V. Note When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no jumper and JP6 must be set to position 2-3. 5.0V 3.3V...

  • Page 13: Cpu Interface

    If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. These pins are not used in their corresponding Host Bus Interface mode. Systems are responsible for externally connecting them to the host interface IO V Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 14: Cpu Bus Connector Pin Mapping

    Connected to WE0# of the S1D13706 Connected to WAIT# of the S1D13706 Connected to CS# of the S1D13706 Connected to MR# of the S1D13706 Connected to WE1# of the S1D13706 Connected to TXVDD1 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 15 +5 volt supply Connected to RD/WR# of the S1D13706 Connected to BS# of the S1D13706 Connected to BUSCLK of the S1D13706 Connected to RD# of the S1D13706 Not connected Not connected Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 16: Lcd Interface Pin Mapping

    GPO on H1 can be inverted by setting JP4 to 2-3. The Sharp HR-TFT MOD signal controls the panel power. This must not be confused with the MOD signal used on many passive panels. Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 17 If REG[10h] bits[1:0] are set for either HR-TFT or D-TFD, some of the pins are used for the HR-TFT or D-TFD interfaces and are not available as GPIO pins. Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 18: Technical Description

    PCI Bridge FPGA to support the PCI bus. 6.2 Direct Host Bus Interface Support The S5U13706B00C is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment. However, the S1D13706 directly supports many other host bus interfaces.

  • Page 19: Manual/Software Adjustable Lcd Panel Negative Power Supply (Vlcd)

    Technical Description The S5U13706B00C uses GPO and CVOUT to control the MAX754 as shown in the following table.. Table 6-1: Controlling the MAX754 Signal Turn MAX754 On Turn MAX754 Off Reset MAX754 high CVOUT high X = don’t care When JP5 is set to position 2-3, VDDH is adjustable using R24 (200 potentiometer) to provide an output voltage from +24V to +40V.

  • Page 20: Software Adjustable Lcd Backlight Intensity Support Using Pwm

    LCD Panel Voltage” on page 12 for information on setting the panel voltage). 6.7.2 Extended LCD Connector The S1D13706 directly supports Sharp 18-bit HR-TFT and Epson 18-bit D-TFD panels. The extended LCD connector (H3) provides the extra signals required to support these panels.

  • Page 21: Clock Synthesizer And Clock Options

    25.175MHz. Note If an Epson D-TFD panel is selected, the clock synthesizer cannot be programmed, and external oscillators must provide the clock signals to CLKI and CLKI2. Jumpers JP2 and JP3 allow selection of external oscillators U5 and U6 as the clock source for both CLKI and CLKI2.

  • Page 22: Parts List

    MMBT2222A "NPN transistor, SOT-23 pckg." Motorola or equivalent "R1- 1206 / 5% R9,R33,R36,R37,R38,R39" "R10,R11,R12,R13,R14,R1 330K 1206 / 5% 5,R16,R17,R18" 12.4K 1% "1206 / 1%, E-96 series" "R20,R21" 1206 / 5% Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 23 Maxim MAX749CSA or MAX749 8 pin SO pckg. MAX749ESA EPF6016TC14 144-pin QFP Altera EPF6016TC144-2 8-pin DIP 8-pin DIP socket "Machined socket, 8-pin" socket "Altera EPC1441PC8, (U15) EPC1441PC8 8-pin DIP pckg programmed, socketed" Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 24 Micro Shunt "Computer Bracket, Blank - Bracket Keystone - Cat. No. 9203 PCI" "Screw, pan head, #4-40 x 1/4""-- Screw "Pan head, #4-40 x 1/4""" please assemble bracket onto board" Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 25: Schematics

    Schematics 9 Schematics Figure 9-1: S1D13706B00C Schematics (1 of 6) Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 26 Schematics Figure 9-2: S1D13706B00C Schematics (2 of 6) Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 27 Schematics Figure 9-3: S1D13706B00C Schematics (3 of 6) Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 28 Schematics Figure 9-4: S1D13706B00C Schematics (4 of 6) Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 29 Schematics Figure 9-5: S1D13706B00C Schematics (5 of 6) Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...
  • Page 30 Schematics Figure 9-6: S1D13706B00C Schematics (6 of 6) Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 31: Board Layout

    Board Layout 10 Board Layout Figure 10-1: S5U13706B00C Board Layout Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 32: Change Record

    Change Record 11 Change Record X31A-G-004-05 Revision 1.2 - Issued: April 09, 2018 • Updated address/contact page • Updated Epson web page and email address • Minor formatting changes Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

  • Page 33: Technical Support

    Technical Support 12 Technical Support For more information on Epson Display Controllers, visit the Epson Global website. https://global.epson.com/products_and_drivers/semicon/products/display_controllers/ For Sales and Technical Support, contact the Epson representative for your region. https://global.epson.com/products_and_drivers/semicon/information/support.html Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board Rev. 5.1...

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