Sony MDS-JA50ES Service Manual page 76

• IC501 Noise Shaper, Digital Filter (CXD8595Q)/DA board
Pin No. Pin Name
1 PLMG2
2
VDD
3
NSDOL4
4
NSDOL3
5
NSDOL2
6 NSDOL1
7, 8
NC
9, 10
VDD
11
NC
12
64FSI
13
NSDOR1
14
NSDOR2
15
NSDOR3
16
NSDOR4
17
MCKIN
18
VDD
19
PLMG1
20
VSS
21
TEST3
22
TEST4
23
DFLRCKO
24
DFDTOR
25
NC
26
MODE
27
DRPOL
28
OVFLAG
29
MUTEL
30
MUTER
31
MTPOL
32
INAF
33
DINIT
34
CKVDD
35 128FSO
36
NC
37
INVI
38
INVO1
39
INVO2
40 NC
I/O
I 4 bit conversion data setting pin in SCD mode (Fixed at "L")
— Power supply (+5V)
O Noise shaping data Lch parallel output 4 (MSB) (Not used)
O Noise shaping data Lch parallel output 3 (4SB) (Not used)
O Noise shaping data Lch parallel output 2 (2SB) (Not used)
O Noise shaping data Lch parallel output 1 (LSB) (Not used)
— Not used
— Power supply (+5V)
— Not used
I 64 Fs clock input
O
Noise shaping data Rch parallel output 1 (LSB) (Not used)
O Noise shaping data Rch parallel output 2 (2SB) (Not used)
O Noise shaping data Rch parallel output 3 (4SB) (Not used)
O Noise shaping data Rch parallel output 4 (MSB) (Not used)
I Master clock input (256 Fs)
— Power supply (+5V)
I 4 bit conversion data setting pin in SCD mode (Fixed at "L")
— Ground
I
Test pin (Fixed at "L")
I
O Digital filter data LR clock output
O Digital filter data Rch data output
—
Not used
I Mode setting pin "L":CD mode, "H":DSD mode (Fixed at "L")
I Rch data polarity setting pin "L":Positive phase (Fixed at "L")
O Digital filter output overflow flag output "H":Active (Fixed at "L")
O Mute flag output (Lch) (Not used)
O Mute flag output (Rch) (Not used)
I Mute flag polarity setting pin "L":L active, "H":H active (Not used)
O Sync deviation detection flag "H":Active (Sync deviation detection)
O External INIT signal delay signal output (Not used)
— Power supply (+5V) (Clock system)
O 128 Fs clock output (Not used)
— Not used
I 384 Fs generation three times buffer input (Not used)
O First stage buffer output for three times (Not used)
O Second stage buffer output for three times (Not used)
— Not used
— 98 —
Function