JVC UX-A52 Service Manual page 43

LA72723 (IC3) : RDS demodulation
1. Pin layout
VREF 1
MPXIN 2
Vdda 3
Vssa 4
FLOUT 5
CIN 6
TES 7
XOUT 8
2. Block Diagram
+5V
Vdda
REFERENCE
VOLTAGE
Vssa
MPXIN
ANTI ALIASING
FILTER
TEST
TEST
3. Pin functions
Pin
Symbol
I/O
No.
1 O
VREF
MPXIN I
2
Analog power supply (+5V)
Vdda
3
Analog ground
Vssa
4
O Subcarrier input (filter output)
5 FLOUT
Subcarrier input (comparator input)
6 CIN I
I Test input
TEST
7
Crystal oscillator output (4.332MHz)
8 O
XOUT
Crystal oscillator input (exeternal reference input)
9 XIN I
Vssd Digtal ground
10
Digtal power supply
11 Vddd
I Read mode setting (0:master,1:slave)
12
MODE
RDS-ID/RAM reset (positive polarity)
13 RST I
RDS data output
14 RDDA O
I/O
RDCL RDS clock output (master mode)/RDS clock input (slave mode)
15
RDS-ID/READY output (negative polarity)
RDS-ID
16
O
READY
RDS-ID/READY
16
RDCL
15
RDDA
14
RST
13
MODE
12
Vddd
11
Vssd
10
XIN
9
FLOUT CIN
VREF
+
-
VREF
57kHz
BPF
(SCF)
SMOOTHING
FILTER
CLK(4.332MHz)
OSC
XOUT
XIN
Reference voltage output (Vdda/2)
Baseband (multiplexed) signal input
CLOCK
RECOVERY
PLL
(1187.5Hz)
(57kHz)
DATA
DECODER
RAM
(128-bits)
RDS-ID
DETECT
Function
UX-A52
+5V
Vddd
Vssd
RDDA
RDCL
MODE
RST
RDS-ID/
READY
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