Sharp HR-MB3 Service Manual page 33

IC201 VHICY68013A-1: USB (CY68013A) (1/2)
Pin No. Terminal Name
1 SLRD
2 SLWR
3 AVCC
4 XTALOUT
5 XTALIN
6 AGND
7 AVCC
8 DPLUS
9 DMINUS
10 AGND
11 VCC
12 GND
13* IFCLK
14 Reserved
15 SCL
16 SDA
17 VCC
18 PB0
19 PB1
20 PB2
21 PB3
22 PB4
23 PB5
24 PB6
25 PB7
26 GND
27 VCC
28 GND
29 CTL0
30 CTL1
31 CTL2
32 VCC
33 PA0
34 PA1
35 SLOE
36 WU2
37 FIFOADR0
38 FIFOADR1
39 PKTEND
40 SLCS#
41 GND
42 RESET#
43 VCC
44 WAKEUP
45 PD0
46 PD1
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Input/Output
Input SLRD is the input only read strobe with programmable polarity (FIFOPINPOLAR.3) for the
slave FIFOs connected to FD[7..0] or FD[15..0].
Input SLWR is the input only read strobe with programmable polarity (FIFOPINPOLAR.2) for the
slave FIFOs connected to FD[7..0] or FD[15..0].
Input Analog VCC.
Output Crystal output.
Input Crystal input.
— Analog Ground.
Input Analog VCC.
Input/Output USB D+Signal.
Input/Output USB D-Signal.
— Analog Ground.
Input VCC. Connect to 3.3 V power source.
— Ground.
Output Interface Clock, used for synchronously clocking data into or out of the slave FIFOs. IFCLK
also servers as a timing reference for all slave FIFO control signals and GPIF. When internal
clocking is used (IFCONFIG.7 =1) the IFCLK pin can be configured to output 30/48 MHz by
bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally
sourced, by setting the bit IFCONFIG.4 = 1.
Input Reserved. Connect to ground.
Clock for the I2C interface.
Data for I2C-compatible interface.
Input/Output VCC. Connect to 3.3 V power source.
Input/Output PB0 is a bidirectional I/O port pin.
Input/Output PB1 is a bidirectional I/O port pin.
Input/Output PB2 is a bidirectional I/O port pin.
Input/Output PB3 is a bidirectional I/O port pin.
Input/Output PB4 is a bidirectional I/O port pin.
Input/Output PB5 is a bidirectional I/O port pin.
Input/Output PB6 is a bidirectional I/O port pin.
Input/Output PB7 is a bidirectional I/O port pin.
— Ground.
Input VCC. Connect to 3.3 V power source.
— Ground.
Output CTL0 is a GPIF control output.
Output CTL1 is a GPIF control output.
Output CTL2 is a GPIF control output.
Input VCC. Connect to 3.3 V power source.
Input PA0 is bidirectional I/O port pin.
Input PA1 is bidirectional I/O port pin.
Input/Output SOLE is an input only output enable with program-mable polarity (FIFOPINPOLAR.4) for the
slave FIFOs connected to FD[7..0] or FD[15..0]
Input/Output WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and
polarity set by WU2POL (WAKEUP.4).If the 8051 is in suspend and WU2EN = 1, a transition
on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Asserting this pin inhibits the chip from suspending, if WU2EN=1.
Input/Output FIFOADR0 is an input only address select for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Input/Output FIFOADR1 is an input only address select for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Input PKTEND isi an input used to commit the FIFO packet data to the endpoint and whose polar-
ity is program-mable via FIFOPINPOLAR.5.
Input SLCS# gates all other slave FIFO enable/strobes.
— Ground.
Input Active low reset.
Input VCC. Connect to 3.3 V power source
Input USB wakeup.
Input/Output Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0
(wordwids) bits.
Input/Output Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0
(wordwids) bits.
8 – 4
Function
HR-MB3