Pioneer KRL-46V Service Manual page 62

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HiDTV Pro LX66: Introduction (IC 8101)
DESCRIPTION
The HiDTVTM Video Processor Family combines the features advanced high-definition MPEG2 decoding, system processing
and video processing features to deliver exceptional video fidelity and system functionality.
HiDTV system-on-a-chip digital TV processor designed especially for HD digital TV systems. It contains 32-bit RISC microprocessor,
a 2D graphic engine, an MPEG-2 MP@HL decoder, a programmable MPEG audio decoder which supports AC3, AAC,
and MP3, and a transport stream demultiplexer which supports ATSC, DVB and ARIB standards.
HiDTV integrates Trident's industry-leading SVP family video processor with our DCRe engine to enhance all video signals.
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HiDTV Pro: Introduction (IC 8101)
The main features are:
- Master CPU with MMU.
- DDR2 memory up to 256mHz.
- Two Transport stream inputs, DVB compliant.
- Two HD MPEG2 video decoders.
- Demux, support two TS inputs and one PS input.
- DVB_CI, up to two PCMCIA slots for CAM cards.
- DVB/DES.
- AC3/MPEG2/MP3/AAC...audio.
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- 1920 x 1080p de-interlacing.
- Graphics engine.
- Two video planes and graphics planes with Alpha blender,
overlay, scrolling, flashing, colour key, ARB support.
(CVBS/SVideo/SCART)
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COFDM-Demod TS1
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2
MIPS
HOST
(D_In Video)
DEMUX
2xTS/PS
/OOB/CI
DVB/DES/
(TS2)
DVB-CI
Graphic s
(SCR)
(CIR)
(IDE)
Uart
USB
Flash/PCI/IDE/UDB2.0/RTC/SC/CIR/
8051/I2C/PWM/LVDS/DAC/Key
8051bus
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3
- Smart-Cards/UART/infrared IR/RTC/two HW timers/interrupt
/Key button ADCs.
- Flash/IDE/PCI Host.
- Audio interface: AC97 link/I2S_out/I2S_in/SPDIF and
lip-sync.
- Digital 24-bit RGB/YUV inputs.
- Dual port/Single port LVDS output.
- USB2.0 HOST/PHY built with EHCI.
- CVBS/S-video/YCbCr output.
- Two HD, 1920 x 1080p.
BLOCK DIAGRAM
MI PS A V
MPEG 2
Vedeo Decoder
Two HDs
SV P LX
Up to 1080P
De-interlacing
graphics plans
Peripherals
Uart
ADCs
DDR2 Flash
256MB EEPROM
KRL-46V
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4
D_Out Video
I2S/SPDIF Audio
I2C master/2 interrupts
GPIO / PWM
8xKey buttons
PCI bus
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