Toshiba TC9314F Manual page 11

7. Data Register (DATA REG.)
This is a register composed of 1
program memory is loaded during executing of DAL instruction. This register is treated as one of the port,
and when KEY instruction among input and output instruction is executed, it's content is read in the data
memory in 4 bits unit.
(refer to register port item 2)
8. Carry F/F (C F/F)
This is set when carry or borrow is produced as a result of executing operational instruction, and is reset
when it is not produced. Content of carry F/F changes only when addition and subtraction instruction is
executed, and does not change during the execution of other instructions.
9. Judge Circuit (J)
When a instruction with skip function is executed, this circuit judges it's skip condition. When skip
condition is satisfied, this circuit makes two increments of program counter, and skips the succeeding
instruction.
It is provided with 15 kinds of instructions having abundant skip function.
(refer to Item 11, explanation list of function and operation of instructions, * marked instruction)
10. List of Instructions Set
54 kinds of instruction set are included, all of which consisting of one word instruction.
These instructions are expressed with 6 bits instruction code.
Higher Rank 2 Bits
Lower Rank 4 Bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
16 bits. In this register, 16 bits data of optional address among the
00
0
0 AI M, I
1 AIC M, I
2 SI M, I
3 SIB M, I
4 ORIM M, I
5 ANIM M, I
6 XORIM M, I
7 MVIM M, I
8 AD r, M
9 AC r, M
A SU r, M
B SB r, M
C ORR r, M
D ANDR r, M
E XORR r, M
F MVSR M1, M2
01
1
TMTR r, M
TMFR r, M
SEQ r, M
SNE r, M
CALL ADDR
LD r, M*
ST M*, r
CLT r, M
CLTC r, M
MVGD r, M
JUMP ADDR
MVGS M, r
11
TC9314F
10 11
2 3
SLTI M, I
SGEI M, I
SEQI M, I
SNEI M, I
1
TMTN M, N
TMT M, N
TMFN M, N
TMF M, N
IN1 M, C
IN2 M, C
IN3 M, C
OUT1 C, M
OUT2 C, M
OUT3 C, M
DAL ADDR , r
2
SHRC M
1
RORC M
STIG I*
SKP, SKPN, RN, RNS
WAIT P
SKSTP
XCH M
NOOP
2003-07-03