Backup Modes - Toshiba TC9314F Manual

Backup Modes

To enter the three backup modes, execute the CKSTP or WAIT instruction.
1. Clock Stop Mode
Clock stop mode halts the system and maintains the internal state of the system immediately prior to
halting. During a halt, the system is maintained with low current consumption (1 A or below, at V
V). In clock stop mode, the crystal oscillator halts and the output ports and LCD display output pins are all
automatically set to the low level or the off state. The supply voltage can be reduced to 1.2 V.
When the CKSTP instruction is executed, execution halts at the address of the CKSTP instruction.
Therefore, execution starts again from the next instruction when clock stop mode is released (after a
standby period of around 100 ms).
(1) Setting clock stop mode
Clock stop mode can be set to one of two modes. The CKSTP bit determines which of the two modes
is set. Use the OUT2 instruction with the operand [C
1) MODE-0
In mode 0, executing the CKSTP instruction when the HOLD pin is low enters clock stop
mode. Executing the CKSTP instruction when the HOLD pin is high is equivalent to executing
a NOOP instruction.
2) MODE-1
In mode 1, executing the CKSTP instruction enters clock stop mode regardless of the level of
the HOLD pin.
Note 20: The PLL turns off during execution of the CKSTP instruction.
(2) Releasing clock stop mode
1) MODE-0
In mode 0, clock stop mode is released when the HOLD pin goes to high, or by a change in
the input state of any I/O port 1 pin (P1-0~P1-3) set as an input port.
2) MODE-1
In mode 1, clock stop mode is released by a change in the input state of the HOLD pin or in
the input state of any I/O port 1 pin (P1-0~P1-3) set as an input port.
7H] to access this bit.
N
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TC9314F
5
DD
2003-07-03