Panasonic PT-50LCZ70 Service Manual page 59

VIDEO SIGNAL PATH II BLOCK DIAGRAM
MAIN P.C.B.
IC5501 (EEPROM)
VCC 8 MAIN+5V
I2C SERIAL CLOCK 6
I2C SERIAL DATA 5
WRITE PROTECT 7
IC5500 (EEPROM)
VCC 8 MAIN+5V
I2C SERIAL CLOCK 6
I2C SERIAL DATA
5
WRITE PROTECT
7
CN5501
+5V
TMDS DATA0(+)
TMDS DATA0(-)
TMDS DATA1(+)
TMDS DATA1(-)
TMDS DATA2(+)
HDMI-IN1
TMDS DATA2(-)
TMDS CLOCK(+)
TMDS CLOCK(-)
I2C SERIAL CLOCK
I2C SERIAL DATA
CN5500
+5V
TMDS DATA0(+)
TMDS DATA0(-)
TMDS DATA1(+)
TMDS DATA1(-)
TMDS DATA2(+)
HDMI-IN2
TMDS DATA2(-)
TMDS CLOCK(+)
TMDS CLOCK(-)
I2C SERIAL CLOCK
I2C SERIAL DATA
IC5511 (SW)
6
5
MAIN+5V 8 VCC
1 7
IC5512 (SW)
6
5
MAIN+5V 8 VCC
Q5504 1 7
Q5505
SD/HDMI P.C.B.
IC9802 (EEPROM)
IC9801 (EQUALIZER)
VCC 8 MAIN+5V
I2C SERIAL CLOCK 6
I2C SERIAL DATA 5
4
WRITE PROTECT 7
3
CN9803
7
+5V
6
TMDS DATA0(+)
TMDS DATA0(-)
TMDS DATA1(+)
10
TMDS DATA1(-)
9
TMDS DATA2(+)
HDMI-IN3
TMDS DATA2(-)
TMDS CLOCK(+)
46
TMDS CLOCK(-)
45
I2C SERIAL CLOCK
I2C SERIAL DATA
2,11,ETC
+3.3V
VCC
Q9804
MAIN Y/V
MAIN PB/C
FROM VIDEO I
MAIN PR
SIGNAL PATH
BLOCK DIAGRAM
PC H-SYNC
PC V-SYNC
IC5503 (HDMI SW/EQUALIZER)
31
30 20
SW EQUALIZER BUFFER
4 21
3
34
33 16
SW EQUALIZER BUFFER
7 17
6
40
39 13
SW EQUALIZER BUFFER
10 14
9
28
27 23
SW EQUALIZER BUFFER
46 24
45
2,11,ETC
VCC MAIN2+3.3V
36
2
3
Q5508
2
3
20 CN9804-4 CN5503-4
EQUALIZER BUFFER
CN9804-6 CN5503-6
21
16 CN9804-3 CN5503-3
EQUALIZER BUFFER
17 CN9804-1 CN5503-1
13 CN9804-9 CN5503-9
EQUALIZER BUFFER
CN9804-7 CN5503-7
14
23 CN9804-10 CN5503-10
EQUALIZER BUFFER
24 CN9804-12 CN5503-12
CN9804-25 CN5503-25
CN9804-27 CN5503-27
(FROM IC6004 (6))
HDMI MUX SELECT(L)
(FRON IC6004 (106))
CN9804-26 CN5503-26
EDIT WP(H)
IC5510 (HDMI INTERFACE AD CONVERTER)
Q5516
B 99
Q5515 A/D
B MATRIX
78
CONVERTER
Q5514
B 94
63 PC H-SYNC
62 PC V-SYNC
DATA
PROCESSOR
MUX
116
115
119
118
TMDS MODE
YUV
DECODER
CONVERTER
480p
122
720p
121
/1080i
1080p
113
112
MUX HDMI
DECODER
132
131
135
134
TMDS
DECODER
138
137
129
128
105 I2C SERIAL CLOCK
I2C SERIAL DATA
106
AUDIO
DECODER
I2C SERIAL CLOCK
144
1 I2C SERIAL DATA
59
PT-50LCZ70 / PT-56LCZ70 / PT-61LCZ70 / PT-50LCZ7 / PT-56LCZ7 / PT-61LCZ7
VIDEO SIGNAL AUDIO SIGNAL
IC5504 (EEPROM)
I2C SERIAL CLOCK 108 6 I2C SERIAL CLOCK
I2C SERIAL DATA 107 5 I2C SERIAL DATA VCC 8 MAIN+3.3V
YUV DATA (24BIT)
24-33, 38-47,
52, 53, 55, 58
TO VIDEO I
a SIGNAL PATH
R5646
H-SYNC 17 H-SYNC BLOCK DIAGRAM
b
R5645
V-SYNC
V-SYNC
18
c
R5636
CLOCK 51 CLOCK
a
FREQUENCY
V1 +3.30 Vp-p
27MHz
74.25MHz
148.5MHz
1V 5µs
X5500
b
27MHz CLOCK
65 27MHz
27MHz CLOCK OSC V1 +3.30 Vp-p
66
1V 10ms
c
V1 +1.80 Vp-p
1V 10ns
3 HDMI SERIAL DATA
TO AUDIO
7 HDMI LRCK
BLOCK DIAGRAM
8 HDMI BCK
2 HDMI SPDIF
TP5052 TP5053
111,123,ETC
L5512
TVDD
TP5060 TP5051 IC5506 TP5040 TP5041
84,88
AVDD 1 +3.3V REG. 7 SUB+5V
5 TP5044 TP5055
15,35,ETC
L5515
DVDDIO MAIN+3.3V
IC5508
TP5058 TP5059 TP5042 TP5043
68,71,ETC
L5521
PVDD 4 +1.8V REG. 5 SUB+3.3V
1
104,109,ETC
L5520
CVDD
IC5509
TP5056 TP5057
23,57,ETC
DVDD 1 +1.8V REG. 8
5
FROM SYSTEM CONTROL
TV MAIN ON DELAY (H)
BLOCK DIAGRAM
VIDEO SIGNAL PATH II BLOCK DIAGRAM
PT-50LCZ70/PT-56LCZ70/PT-61LCZ70/PT-50LCZ7/PT-56LCZ7
/PT-61LCZ7/PT-50LCZ70-K/PT-56LCZ70-K/PT61LCZ70-K