Panasonic PT-50LCZ70 Service Manual page 60

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PT-50LCZ70 / PT-56LCZ70 / PT-61LCZ70 / PT-50LCZ7 / PT-56LCZ7 / PT-61LCZ7
VIDEO SIGNAL PATH III BLOCK DIAGRAM
MAIN P.C.B.
IC7101 (DIGITAL SIGNAL PROCESS)
R DATA (8BIT)
N1-N3,P2
P3,T3,U2,U3
G DATA (8BIT)
U1,V1-V3,
W1,Y1-Y3
FROM VIDEO I
SIGNAL PATH
B DATA (8BIT)
L1,L2,P1,
BLOCK DIAGRAM
R1-R3,T1,T2
a
R7372
H-SYNC
H-SYNC
W3
b
R7371
V-SYNC
V-SYNC
W2
c
R7370
CLOCK
M2
CLOCK
MODE
1080p
1080i
OTHER
M12,M13,ETC
L7106
FHD+1.2V
VDD12
V12,V13,ETC
DDR+2.5V
VDD25
L7103
FHD+3.3V
VDD_PLL1
AF18
K5,L5,ETC
L7107
VDDW
IC7105
AC4,AG5,AG14
L7105
+2.5V
1
5
AVDD_DDR
REG.
R7150
AF6
AVDD_DDR CLK
R7275
L7121
DAC_VDD
AF22
IC7115
R7274
L7120
+3.3V
SUB+5V
1
5
AF19
VDD_PLL2
REG.
IC7104
L7104
+3.3V
1
5
W15
VDDPLLDDR
REG.
a
b
c
V1 +3.30 Vp-p
V1 +3.30 Vp-p
V1 +2.20 Vp-p
1V
10ns
1V
10µs
1V
5ms
OSD-H-SYNC
OSD-V-SYNC
OSD-CLOCK
FROM/TO
OSD DATA (16BIT)
VIDEO I
SIGNAL PATH
BLOCK DIAGRAM
OSD-YS
OSD-YM
OSD H-SYNC
OSD-CLOCK
d
e
f
V1 +3.30 Vp-p
V1 +3.30 Vp-p
V1 +3.30 Vp-p
V
5ms
1V
5ms
1V
5ms
R DATA (8BIT)
R7132,R7395
R28,T28-T30,
U28-U30,V30
d
I/P CONVERTER
G DATA (8BIT)
R7126
M28,M29,
/PICTURE CONTROL
N28-N30,P28-P30
e
B DATA (8BIT)
R7125
J28-J30,K28-K30,
L29,L30
g
R7128
f
H-SYNC
H29
h
R7127
V-SYNC
H28
i
R7129
CLOCK(148.5 MHz)
H30
j
R7270
FPGA CLOCK(27MHz)
C16
IC7106 (OSD FIFO MEMORY)
FREQUENCY
135MHz
74.25MHz
81MHz
OSD FIFO
MEMORY
IC7103 (EEPROM)
SCA
SCA
V4
6
Setting data for Digital
Signal Process(IC7101)
SDA
SDA
U4
5
IC7117 (128M SDRAM)
AB1,AC1-AC3,AD1-AD3,
128M
AE2,AE3,AF2,AF3,AG1-AG3,
SDRAM
AH1,AH2,AH11-AH16,
AJ10-AJ16,AK10,AK15,AK16
VDD
L4,E4,ETC
X7101
27MHz CLOCK
AJ23
27MHz
27MHz CLOCK
AK23
OSC
g
h
i
j
k
V1 +3.30 Vp-p
V1 +3.30 Vp-p
V1 +3.30 Vp-p
V1 +3.60 Vp-p
V1 +3.30 Vp-p
1V
s
1V
5ms
1V
5ns
1V
25ns
1V
IC7119 (FPGA/LVDS TRANSMITTER)
N2,N5,P2-P5,
R2,T3
L3-L5,
M2-M5,N1
G1,H1-H5,
K5,L2
G2
H-SYNC
OSD MIX
G3
V-SYNC
CLOCK(148.5MHz)
J3
FPGA CLOCK(27MHz)
J4
A11-A13,A15,B11-B16,
C2,C10-C15,D1-D5,
E2-E5,F1-F5,G5
A4,A8-A10,B4-B6,B8-B10,
C3-C6,C8,C9,C16,D6-D9,
D11-D14,E6-E8,E10,E11,E13,G4
2,8,15,ETC
VCC
FHD+3.3V
L7101
VCC
8
FHD+3.3V
TP7104
IC7109
L7116
+2.5V
DDR+3.3V
1
8
REG.
IC7110
R7404
L7117
+2.5V
1
8
REG.
IC7111
A2,B1,ETC
+2.5V
2
4
VCC INT
REG.
R7170
L7118
J5
VCCA_PLL1
L7119
J12
VCCA_PLL2
IC7112
E18,M12,ETC
+1.5V
4
5
VCCI03
REG.
E1,G7,ETC
FHD+3.3V
VCCI01
V7
OSD-H-SYNC
V8
OSD-V-SYNC
k
R7405
T8
OSD-CLOCK(70.88MHz)
R7365,
l
R7366
T9-T13,U9-U14,
V9-V13
OSD-YS
U7
OSD-YM
T7
OSD H-SYNC
U8
R7396
k
OSD-CLOCK(70.88MHz)
R4
l
V1 +3.30 Vp-p
10ns
1V
5ms
60
VIDEO SIGNAL
n
m
R7320
TA2+
D17
CN7001-31
R7321
TA2-
C17
CN7001-33
TB2+
D15
CN7001-25
D16
CN7001-27
TB2-
TTL PARALLEL
E15
CN7001-19
TC2+
TO LVDS SERIAL
E16
CN7001-21
TC2-
CONVERTER
F17
CN7001-13
TD2+
F18
CN7001-15
TD2-
R7384
H17
CN7001-1
CLK2+
R7385
H16
CN7001-3
CLK2-
o
TO VIDEO IV
SIGNAL PATH
BLOCK DIAGRAM
n
m
R7308
CN7001-10
TA1+
M17
R7309
TA1-
M18
CN7001-8
TB1+
N17
CN7001-16
TB1-
N18
CN7001-14
TTL PARALLEL
TC1+
N15
CN7001-22
TO LVDS SERIAL
TC1-
N16
CN7001-20
CONVERTER
TD1+
R18
CN7001-28
R17
CN7001-26
TD1-
R7310
L17
CN7001-4
CLK1+
R7311
L18
CN7001-2
CLK1-
o
m
1V
5ms
n
1V
5ms
o
1V
10ns
IC7113 (MEMORY)
CLOCK
L1
6
CLOCK
VCC
8
FHD+3.3V
FPGA
Software
DATA
H7
2
DATA
VCC
7
VIDEO SIGNAL PATH III BLOCK DIAGRAM
PT-50LCZ70/PT-56LCZ70/PT-61LCZ70/PT-50LCZ7/PT-56LCZ7
/PT-61LCZ7/PT-50LCZ70-K/PT-56LCZ70-K/PT61LCZ70-K

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