Table of Contents
Advertisement
FDD412A/B
:
Correc-—
Input
Differences
between
ae
ee
tion
data
input
data
intervals!
difference
values
O@E886
©
(c)
Operating
principle
of VFO
The
VFO
circuit
is
intended
to generate
the window
signal.
In practice,
the
intervals
between
read
data
vary
depending
on
several
factors
including
medium
revolutions.
This
keeps
the window
signal
from
correct
separation
as
a fixed
generator
output.
It becomes
necessary
for
the window
signal
to
synchronize
with
data
interval
variations.
This
is achieved
by a circuit
as
shown
in Fig.
2.25.
correcting
differ-
and window
signal
ences
are
created.
are
checked
Window
signal
Fig.
2.25
Operating
Principle
of VFO
(d)
Correspondence
to block
diagram
(Fig.
2.22)
(i)
Data
SS:
Converts
input
data waveshapes
into pulse
waveshapes
for
easy
comparison
in
order
to
verify
differ-
ences
(in FM mode:
1.0
Us-wide
pulse;
in MFM
mode:
0.5
s-wide
pulse).
(ii)
Data
separator:
Compares
the
generator
output
and
data
pulses
in phase.
For
a phase
difference,
a signal
with
the
pulse
width
proportionate
to
the
amount
of
difference
is
output.
The
DEC
(decrease)
or
INC
(increase)
signal
is
output
depending
on
the
phase
shift
direction
(leading
or lagging).
(iti)
Charge
pump/L.P.F.:
Produces
the
control
voltage
(VE)
for
control
on
the VCO
generator
output.
The
voltage
is
output
in proportion
to
the
pulse
width
(i.e.,
phase
difference)
of the DEC
or
INC
signal.
(iv)
vco:
This
voltage
controlled
oscillator
provides
oscil-
lation
at
frequencies
proportionate
to
the
input
control
voltage
(center
frequency:
2MHz).
(e)
Other
operations
(i)
HIGH
GAIN:
Promotes
VFO
follow-up
characteristics.
When
the
VFO
SYNC
signal
is
given,
it is preferable
to
complete
the
follow-up
as
soon
as
possible.
Once
the
follow-up
is completed,
it
then
is necessary
to keep
off
effects
of noise
and
bit
dislocation.
This
signal
turns
on
the
follow-up
characteristics.
,
(ii)
2ND FILE
DATA:
The
FDD
equipped
with
VFO
can
separate
data read by an FDD without
VFO by connecting
a model
B
FDD.
This
signal
allows
data
from
a model
B FDD
to
enter
the
VFO
circuit
of
this
FDD.
2us
Input
data
A
DATAYSSoutpatel
(LSP
te
ee
:
;
yoo ctock
UCP
LUE
ep
i
:
if
\,
;
DEC
L
Lf
]
|
|
INC
aa
aaa
a
EE
state
Advertisement
Table of Contents
