HP 8082A Operating And Service Manual page 21

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TRIGGER

Figure 3-9. Flip-Flop Test Circuit

3 - 3 4

The minimum set-up time required for

measured as shown in Figure 3-l

The pulse delay controls of the clock output are slowly

decreased and because the output is in double pulse

form, only the second pulse in each case advances

FIRST SOS2A

TRIGGER

OUTPUT

CLOCK

OUTPUT

INSERT 7ns DELAY

SQUARE WAVE MODE

DOUBLE PULSE MODE

wards the

leading

a '1'). The minimum set-up time is found wh.en the

flip-flop ceases to switch properly from '0' to 'I'. The

minimum set-up time for switching from '1' to '0' c a n

then be found by switching to the complement of the

data input and repeating

-FLOP

edge of its data input (in this case

the exercise.

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