Mitsubishi Electric AJ71QC24 Manual page 119

Melsec qna serial communications module
Table of Contents

Advertisement

6. BIDIRECTIONAL
PROTOCOL
COMMUNICATIONS
MELSEC
QnA
6.4.2
PC CPU input/output signals
The following shows the inpuVoutput signals used with the bidirectional protocol.
Input signals (AJ71 QC24+PC CPU)
Input Signal
Contents
Signal Name
XnO
Turned ON while the QC24 is sending data to the
Sending
Xn2
Turned ON when an error was detected during trans-
Transmission abnormal end
Xnl
Turned ON at the end of transmission in response to
Transmission normal end
a Request to Send signal from the PC CPU.
mission.
PC CPU.
Xn3
Turned ON when an error was detected while re-
Receive error detected
Xn4
device after the QC24 is started.
Turned ON when data is received from the external Receive
data read request
ceiving data.
Xnl E
QC24 Ready signal
Turned ON when the QC24 is ready to operate.
Xnl F
Watchdog timer error
Turned ON when the QC24 cannot operate normally.
Output signals (PC CPUjAJ71 QC24)
Output Signal
Contents
Signal Name
Turned ON when the data sent
to the QC24 buffer
YnO
Request to Send
Turned ON by the QC24 when the PC CPU has
device after the QC24 is started.
memory from the PC CPU is sent to the externa
Ynl
End of Receive Data Read finished reading the data received from the exter-
nal device.
(Note) XnO and YnO are determined by the slot into which the QC24 is inserted.
With the system configuration shown below, the QC24 is allocated to X.Y80-9F,
0
1
z
3
4
(Slot
No.)
XnO=XBO
XnZ=XBZ
XrO=Y80
Y 1 l = Y 8 1
X30
Y 4 3
X Y 8 G
X3F
Y7F
X Y S F
6 - 8

Advertisement

Table of Contents
loading

This manual is also suitable for:

Aj71qc24-r2Aj71qc24-r4

Table of Contents