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APPENDIXES
MELSEC QnA
APPENDIX 2
PC CPU INPUT/OUTPUT SIGNALS TABLE
The following shows the QC24 inputloutput signals for the PC CPU.
The No. of the inputloutput signal of the slot into which the QC24 is inserted determines (n) added
to the X and Y numbers.
(Example: When the QC24 was inserted into slot 0
of
the basic base unit XnO+XO)
(1) InpuVoutput signals table
XnB
XnC
I
Recelve error detected
CHI .ERR LED OFF reauest
YnE
CHI .ERR LED ON
XnE
YnD
CH2
I
Mode switching (initializlng) '1 XnD
to
XnF
CH2.ERR LED OFF request YnF
CH2.ERR LED
ON
X (n+l) 0
(Unusable) Y
(n+l) 0
to
to
X (n+l) 6
Reauest to read EEPROM
X (n+ll 7
End of EEPROM read
X ( n + l l 7
Y (n+l) 6
X ( n t l ) 8
Y (n+l)
F
Watchdog tlmer error '3
X (n+l) F
to
QC24 Ready (accessible) '2
X (n+l) E
(Unusable)
Y (n+l)
D
X (n+l) D
System setting default request
Y (n+l) C
End of system setting default
X (n+l) C
Y (n+l) B
CH2
I
Global signal
X (n+l) 6
(Unusable)
Y (n+l) A
CHI
I
Global signal
X (n+l) A
Request to write system settrng to EEPROM
Y (n+l) 9
End of EEPROM system settings write
X (n+l) 9
Request to write EEPROM
Y (n+l) 8
End of EEPROM write
*I
During mode switching (Xn6, XnD: ON), do not send a Request to Send signal to the objective
interface. (The QC24 will stop sendheceive processing.)
*2 The QC24 Ready signal (X(n+l)E) is turned ON when the PC CPU can access the QC24. (The
QC24 Ready signal is turned ON about 1 second after the power is turned ON or the PC CPU
is reset.)
Use this signal as a FROMflO instruction or other interlock signal.
mally. When it is turned ON, the PC CPU must be reset.
*3
The watchdog timer error signal (X(n+l)F) is turned ON when the QC24 cannot operate nor-
IMPORTANT
The output signals designatged "(unusable)" in the table above are used by the system and
cannot be used by the user.
If the user should use these signals, the functions of the QC24 cannot be guaranteed.
APPENDIX
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5
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