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APPENDICES
MELSEC-A
APPENDIX
4.
DTR
Control
This appendix explains
DTR
control.
(1)
Explanation of
DTR
control
DTR control enables and disables data communications with an exter-
nal device via the
AJ71C24 RS-232C
by means of the
DSR
and DTR
signals.
DTR
control is not available for the
RS-422.
(2)
Data received from an external device is stored in the
AJ71C24
no-
protocol receive buffer memory area via the
OS
memory area.
Under the following conditions, the
A J 7 1 C 2 4
temporarily stores
received data to its
OS
area. When transfer to the no-protocol receive
buffer memory is enabled (read request signal X n l is
OFF),
data is
transferred until the receive completed code is received, or until the
fixed length of data has been transmitted.
Conditions:
1)
When there is too much data for the buffer memory because the
received data length exceeds the no-protocol receive buffer
memory area.
2)
When data is transmitted from an external device before the
PC
CPU
reads the data received previously.
(3)
The size of the receive data storage area of
AJ71 C24
OS area is
279
bytes. It turns the
DTR
signal
ON
and
OFF
as follows:
*less than
1 0
bytes storage area free
: OFF
more than
41
bytes storage area free :
O N
(4)
When received data is cleared as described in Section
9.5 (5),
all data
in the
OS
area is cleared at the same time as data in the no-protocol
receive buffer memory area.
(OFF: receive disabled)
I
Receive
ON
ON
ready
AJ71C24 memorv
AJ71C24 memory
(0s
area)
(0s
area)
OFF
279 byte]
storage)
Free area
OFF
279 bytes
110
bytes
OTR signal
(ON : receive enabled
'i
I
(Data
storage)
APP
-
7
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