CHAPTER 3 THEORY OF OPERATION
1.3.5
Optional serial I/O
HL-1250
The interrupt of the serial I/O is input to the EXINT terminal of the ASIC, and is recognized by
the CPU. A 32-byte register is provided for this I/O, which is read from and written to by the
CPU.
1.3.6
EEPROM
HL-1240
The EEPROM is X24C01A type of two-wire method with a 128 x 8 bits configuration.
HL-1250
The EEPROM is X24C04 type of two-wire method with a 512 x 8 bits configuration.
Fig. 3-12
Fig. 3-13
Fig. 3-14
3-12