Technical Description; Pci Bus Support; Direct Host Bus Interface Support; S1D13706 Embedded Memory - Epson S5U13706P00C100 User Manual

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Page 16

6 Technical Description

Note

S1D13706

X31B-G-021-01

The S1D13706 does not have on-chip PCI bus interface support. The S1D13706P00C100

uses the PCI Bridge FPGA to support the PCI bus.

The S5U13706P00C100 is specifically designed to work using the PCI Bridge FPGA in a

standard PCI bus environment. However, the S1D13706 directly supports many other host

bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these

host buses. For further information on the host bus interfaces supported, see "CPU

Interface" on page 11.

The PCI Bridge FPGA must be disabled using SW1-10 in order for direct host bus inter-

faces to operate properly.

The S1D13706 has 80K bytes of embedded SRAM. The 80K byte display buffer address

space is directly and contiguously available through the 17-bit address bus.

The S1D13706 provides Pulse Width Modulation output on PWMOUT. PWMOUT can be

used to control LCD panels which support PWM control of the backlight inverter. The

PWMOUT signal is provided on the buffered LCD connector (H1).

S5U13706P00C100 Evaluation Board User Manual

Revision 1.1

Epson Research and Development

Vancouver Design Center

Issue Date: 2009/03/03

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S1d13706