Main Assy (2/2) - Pioneer CDJ-400 Service Manual

1

10.2 MAIN ASSY (2/2)

A 1/2
A
IPF
SBOK
CPU&FPGA
A 1/2
S R V S B S Y
B
SRVBSY
OEICG
R 5 0 8
1 0 k
VREF1R65
IO1A
C 5 0 3
CH
47p R 5 1 0
R 5 0 3
5 . 6 k
R 5 1 1
4 7 k
R 5 0 4
1 5 0 k
LPFO
1 5 0 k
R 5 0 5 C 5 1 1
0.015u
1 5 k
0.022u
C 5 0 8
C 5 0 9
0.022u
C
C 5 1 0
1000p
LD3S
LDCHK
2 S A 1 0 3 6 K ( P Q R )
Q 5 0 1
LD780
GNDD
VR780PD
D
GNDD
GNDD
V+3R3S
C N 5 0 1
INSIDE
C K S 4 9 9 9 - A
E
V+5M
INSIDE
1
V+5M
V+5M
2
C 5 0 4
GNDD
0.01u
GNDD
3
H3-
H3-
4
H3+
H3+
5
H2-
H2-
6
H2+
H2+
7
H1-
H1-
8
H1+
H1+
9
C 5 0 7
C 5 1 2
A1 0.01u
A1
1 0
0.01u
A2
A2
1 1
A3
1 2
C 5 0 6
A3
0.01u
GNDD
F
A 2/2
52
1
2
SRV-FPGA
CPU-SRV
51
V+3R3S
C 5 1 4
1 0 0 u / 6 . 3
1
I P F
2
S B O K
3
0.1u
C L C K
C 5 1 5
4
V D D 3 _ 1
5
V S S 3 _ 1
6 100. D O U T
D A T A
7
S F S Y
8
S B S Y
9
I O 0 A ( / H S O )
1 0
I O 1 A ( / U H S O )
1 1
A R S E L
1 2
A W R C
C 5 1 6
1 3
P V D D 3
0.1u
1 4
P D O
1 5
T M A X S
1 6
T M A X
1 7
L P F N
1 8
L P F O
1 9
P V R E F
C 5 1 7
2 0
V C O F
0.01u
2 1
V C O R E F
S L C O
25.
2 2
R F I
26.
D T C N
27. R F R P I
2 3
D T C P
2 4
P V S S 3
2 5
VCOF
(RF)
RFI
(RF)
(RF)
(RF)
V+3R3
(RF)
680p
C 5 2 2
R 5 2 3
VREF1R65
2 2 k
R 5 6 2
NM 0
V+3R3
IC501
1 5
I N + V D D
2
V S S
3 4
I N - O U T
R 5 2 1
N M
GNDD
C 5 1 9
N M
MONITOR DIODE IN
C 5 3 5
4 7 u / 1 6
C 5 3 6
0.1u
R 5 5 8
0
GNDM
2
3
SRV-FPGA
CPU-SRV
52
LO RO
7 5
7 4
X O
7 3
X I
7 2
75. X V D D 3
X V S S 3
7 1
T E S I N
7 0
V D D 3 _ 2
6 9
V S S 3 _ 2
6 8
F G I N
6 7
M O N I T
6 6
I O 3 A
6 5
I O 2 A
6 4
D M O
I C 5 0 2 6 3
F M O
T C 9 4 A 1 5 F G 6 2
V R E F
6 1
T R O
6 0
F O O
5 9
A V D D 3 _ 2
5 8
T E Z I
5 7
T E I
5 6
S B A D
5 5
F E I
5 4
R F D C
5 3
51. R F Z I R F R P
5 2
A V S S 3 _ 1
5 1
(RF)
RFZI
(RF)
C 5 3 4
68p CH
LDO MDI
R 5 3 5
2 2 k
ADC
V+7M
DRIVER
MOTOR
I C 5 0 3
1 54
L D O - ACO1+
53
2
L D O + ACO1-
52
3
V C C ACO2+
(F)
4 51
ACO2-
A C T I N 1
5 50
VREF1R65
A C T I N 2 ACO3+
V+5M
6 49
T J M O N ACO3-
C 5 3 8 C 5 3 9
7 4 8
B T H C A V M
47p 0.1u
8 4 7
S P V M _ S
A C T I N 3
CH
9 4 6
P G N D 1 L D I N
1 0 4 5
P G N D 2 A G N D
C 5 4 0
1 1 4 4
U S P C N F
1 2 4 3 0.01u
S P V M 1 F G
1 3 4 2
V V C
1 4 4 1
(S)
f i n 1 f i n 2
1 5 4 0
P G N D 3 S L O 1 +
1 6 3 9
W S L O 1 -
(S)
1 7 3 8 (S)
S P V M 2 S L O 2 +
(S)
1 8 3 7
S P R N F S L O 2 -
1 9 3 6
H B S L G N D
2 0 3 5
H U + C T L 2
2 1 3 4
1/4W
H U - C T L 1
R 5 5 5
2 2 3 3
H V + S L R N F 2
2 . 7 2 . 7 C 5 5 9
2 3 3 2
H V - S L R N F 1
R 5 5 6
2 4 3 1
4 7 u / 6 . 3
1/4W
H W + S L V D D
2 5 3 0
H W - S L I N 2
C 5 4 1
2 6 2 9 0.1u
S P I N S L I N 1
C 5 5 8
2 7 2 8
D G N D D V C C
0.1u
B D 7 9 5 6 F S
GNDD
CDJ-400
3
4
A 1/2
C 5 4 2
0.1u R 5 6 1 C 5 6 0
C L K _ S R V 1 6 M
N M N M
16.9344M
53
SRV16M
C 5 4 3
VREF1R65 1.65V
0.1u
MONIT
TACTHI
IO3A
DMO
IO2A
(TS)
TRO
(F)
C 5 4 4
(TS) FOO
C 5 4 9
0.01u
TEZI
0.033u
TE
(TS)
SBAD
FE
RFDC
GNDD
C 5 4 5
0.033u RFRP
VREF1R65
V+3R3S
R 5 4 3
6 8 k
2
8
1
TRACK COUNT
4
3
V+3R3S
I C 5 0 4
NJM2903M
ADC IN
VREF1R65
6
8
R 5 4 2
7
R 5 5 7
2 2 k
4
5 1 0 k
SPIN
C 5 5 1
OVER T A C T
270p
to CPU
R 5 4 7
1 0 k
GNDD
C 5 5 2
VREF1R65
270p
A 1/2
VREF1R65
FILTER
FILTER
VREF1R65
V+3R3S
SPDLFG
54
DRVMUTE1
DRVMUTE1
DRVMUTE2
DRVMUTE2
55
VREF1R65
(S)
GNDD
SL2IN
SL1IN
(S)
4
LPS2
LPS1
TCOUNT
TCOUNT
ADC
INSIDE
PWMLO
R 5 4 5
F
1 0 k
SPDLFG
FILTER
(S)
R 5 1 8
(S)
4 7 k 4 7 k F
R 5 1 7