Pioneer CDJ-2000 Service Manual page 93

5
RESET
GENERATION
CIRCUIT
V+1R2_CPLL1
V+3R3_CPU
15I
R E S T _ E R
IC102
From EMU
1 5
E R V D D
RESET
C159
R 1 5 8
2
S U B
0.1u
1 0 0 k 3 4
BA G N D V O U T C160
C P U _ R S T
for TFT & DEBUG
0.1u
BD45302G 12C;15I;13:14I
C 2 4 6
CCG1171-A-T
7 10u
GNDD
C 2 4 7
CCG1171-A-T
10u
GNDD
CPU_BUS
V22 W22 Y22 AA22 AB22
A22/PB4/ PRESET# VSS94 XTAL
A24/PB6/
CTS1# DACK0#/
CTS0#
V21 W21 Y21 AA21 AB21
VSS90 VSS93 EXTAL
A23/PB5/ ASEBRKAK#
DTEND0#/ /BRKACK/
RTS1# TCLK/PC1
V20 W20 Y20 AA20 AB20
A21/PB3 VSS87 BS# VSS-PLL1 VDD-PLL1
V19 W19 Y19 AA19 AB19
VSS86 BREQ# VSS-PLL2 VDD-PLL2
A25/PB7/
DREQ0#/
RTS0#
V18 W18 Y18 AA18 AB18
VDDQ30 CS0# VSS89 BACK# VSS97
R 1 6 5
CPU_NMI
0
V17 W17 Y17 AA17 AB17
VDDQ29 CS3# RD# NMI RDY#
V16 W16 Y16 AA16 AB16
VSS76 VSS85 PI0/COM/CDE VSS92 VSS96
CPU_PH3
V15 W15 Y15 AA15 AB15
LCD_CL2/DE_V LCD_DATA0/ LCD_DON/
VSS75 VSS84
/CLS/PH3 DB0/BT_DATA0 DCLKOUT/PH2
V14 W14 Y14 AA14 AB14
VDDQ28 VSS83 LCD_DATA3/ LCD_DATA2/ LCD_DATA1/
DB3/BT_DATA3 DB2/BT_DATA2 DB1/BT_DATA1
V13 W13 Y13 AA13 AB13
VDDQ27 VSS82 LCD_DATA6/DG0 LCD_DATA5/DB5 LCD_DATA4/DB4
/BT_DATA6/PI3 /BT_DATA5/PI2 /BT_DATA4/PI1
V12 W12 Y12 AA12 AB12
LCD_DATA9/ LCD_DATA8/ LCD_DATA7/DG1/
VDD32 VSS81
DG3/PG1 DG2/PG0 BT_DATA7/PI4
V11 W11 Y11 AA11 AB11
LCD_DATA12/ LCD_DATA11/ LCD_DATA10/
VDD31 VSS80
DR0/PG4 DG5/PG3 DG4/PG2
V10 W10 Y10 AA10 AB10
LCD_DATA15/ LCD_DATA14/ LCD_DATA13/
VDDQ26 VSS79
DR3/PG7 DR2/PG6 DR1/PG5
CPU_LCD_CLK
V9 W9 Y9 AA9 AB9
VDDQ25 VSS78
LCD_VCPWC/ LCD_M_DISP/ LCD_CLK/
DR4/PH1 DE_H/DE_C/BT_DE_C DCLKIN
V8 W8 Y8 AA8 AB8
VDDQ24 VSS77 LCD_VEPWC/ LCD_FLM/VSYNC/SPS/ LCD_CL1/HSYNC/SPL/
DR5/PH0 EX_VSYNC/BT_VSYNC EX_HSYNC/BT_HSYNC
V7 W7 Y7 AA7 AB7
VSS74 TRST# VSS88 VSS91 VSS95
V6 W6 Y6 AA6 AB6
VSS73 TDO TMS TDI TCK
V5 W5 Y5 AA5 AB5
VDDQ23 WDTOVF#/IRQ1/ RXD0/AUDATA0 TXD0/AUDATA1 SCK0/AUDSYNC/FCLE
AUDCK/DACK1#
V4 W4 Y4 AA4 AB4
CPU_SCK1
MODE4/FD4 VDDQ31 RXD1/AUDATA2 TXD1/AUDATA3 SCK1/FR/B#
R 1 6 7
V3 W3 Y3 AA3 AB3
1 0
MODE5/FD5 MODE1/FD1 VDDQ32 MODE0/FD0 SDA
R 1 6 8
V2 W2 Y2 AA2 AB2 1 0
MODE2/FD2 RXD2/PA1 VDDQ33 SCL
PJ0/
DIRECTION_M
V1 W1 Y1 AA1 AB1
MODE3/FD3 TXD2/PA2 SCK2/PA0 VDDQ34
PJ1/
IDERST_M#
CPU-USB-ETH-SD
CPU_BUS
CPU-DSP-DAC-PANEL
5
6
V+1R2_CPLL2
V+3R3_CPU
OSC
IC124 V+3R3_CPU
TC7WHU04FU
CPU_TFT_RST
DSP710_CS
8 1
V C C 1 A
7 2
1 Y 3 Y
6 3
3 A 2 A
5 4
2 Y G N D
9
R 3 1 9
1 M
27MHz
X 1 0 5
Crystal
D S S 1 1 8 5 - A
C 2 3 1 C 2 3 0
DSP710_RST
7p 7p
CH CH
GNDD
ETHER_RST
USB_RST
V+3R3_CPU
CPU_BREQ
CPU_BACK
E 2/3
5:1G
C P U _ R D Y
from DSP
16H;5:1G;13:10K
C P U _ R D
to FLASH&DSP&USB
F L A S H _ R D Y
from FLASH
15G
CPU_INT_DSP
E 2/3
12I;3B;5:1F
C P U _ R / W
from CPU
CPU_USB_HSTPWREN
CPU_USB_HSTLED
CPU_USB_HSTSTOP
CPU_PNL_CNVss
CPU_PNL_BUSY
CPU_USB_HSTPWRFL
TP230
CONT01
TP136
CONT00
TP137
CPU_PG2
TP138
CPU_PG7
CPU_EUP_CONT
TP140
CONT02
CPU_PH1
V+3R3_CPU
R 3 4 3
4 7 k
CPU_PH0
CPU_AUDCK
CPU_TDO
CPU_TRST
CPU_TMS
CPU_TDI
CPU_TCK
CPU_AUDATA0
CPU_AUDATA1
CPU_AUDSYNC
CPU_AUDATA2
E 2/3
CPU_AUDATA3
R 3 3 9
12F;3B;5:1F
4 7 k
C P U _ R / W
from CPU
CPU_MODE0
V+3R3_CPU
CPU_SDA
R 1 7 0
4 . 7 k
R 1 7 2
4 . 7 k CPU_SCL
CPU_RXD2
V+3R3_CPU
R 1 8 0
CPU_SCK2
4 . 7 k
CPU_TXD2
R 3 8 8
4 7 k
CPU_MODE3
CPU_MODE2
CPU_MODE1
CPU_SD_CD
CPU_SD_WP
CPU_MODE5
CPU_MODE4
NOTES
NM
GNDD
6
E-b
1/3
A-a
GNDD
V+3R3_CPU
RST logical circuit
C 2 4 4 0.1u
IC122
C P U _ R S T
from Reset IC
1 8
1 A V C C
15I;9A;13:14I 2 7
1 B 1 Y
3 6
2 Y 2 B
4 5
G N D 2 A
V+3R3_CPU
GNDD TC7W08FU
CPU_CS3
C 2 4 5 0.1u
IC123
R 3 6 4
1 1 4
1 A
4 . 7 k V C C
CPU_DSP710_RST 2 1 3
1 B
4 B
3 1 2
1 Y
4 A
R 3 6 5 4 1 1
2 A
4 Y
4 . 7 k
5 1 0
CPU_ETHER_RST
2 B
3 B
6 9
2 Y
3 A
R 3 6 6 7 8
G N D
10
4 . 7 k 3 Y
GNDD
TC74VHC08FTS1
CPU_USB_RST
V+3R3_CPU
C 2 0 4 CCG1171-A-T
IC108
10u
C 2 0 2 54
1
V D D 1 VSS3
0.1u 53
CPU_DATA0 2
D Q 0 DQ15
C 2 1 5 52
3
V D D Q 1 VSSQ4
0.1u 4 51
CPU_DATA1
D Q 1 DQ14
5 50
CPU_DATA2
D Q 2 DQ13
6 49
V S S Q 1 VDDQ4
7 4 8
CPU_DATA3
D Q 3 D Q 1 2
CPU_DATA4 8 4 7
D Q 4 D Q 1 1
C 2 1 6
9 4 6
V D D Q 2 V S S Q 3
0.1u
CPU_DATA5 1 0 4 5
D Q 5 D Q 1 0
1 1 4 4
CPU_DATA6
D Q 6 D Q 9
1 2 4 3
V S S Q 2 V D D Q 3
CPU_DATA7 1 3 4 2
D Q 7 D Q 8
C 2 1 7
1 4 4 1
1000p V D D 2 V S S 2
CPU_LLDQM 1 5 4 0
L D Q M N . C / R F U
1 6 3 9
W E U D Q M
1 7 3 8
CPU_CAS
C A S C L K
1 8 3 7
CPU_RAS
R A S C K E
1 9 3 6
CPU_CS1
C S A 1 2
2 0 3 5
CPU_ADRS13
B A 0 A 1 1
2 1 3 4
CPU_ADRS14
B A 1 A 9
2 2 3 3
CPU_ADRS10
A 1 0 / A P A 8
2 3 3 2
CPU_ADRS0
A 0 A 7
2 4 3 1
CPU_ADRS1
A 1 A 6
2 5 3 0
CPU_ADRS2
A 2 A 5
2 6 2 9
CPU_ADRS3
A 3 A 4
C 2 1 8
2 7 2 8
V D D 3 V S S 1
0.1u
K4S561632J-UC75
Low
R 3 6 3
CPU_CLKOUT
2 2
IC109
C 2 0 3 54
1
V D D 1 VSS3
0.1u 2 53
CPU_DATA16
D Q 0 DQ15
C 2 2 1
3 52
V D D Q 1 VSSQ4
0.1u
4 51
CPU_DATA17
D Q 1 DQ14
5 50
CPU_DATA18
D Q 2 DQ13
6 49
V S S Q 1 VDDQ4
7 4 8
CPU_DATA19
D Q 3 D Q 1 2
8 4 7
CPU_DATA20
D Q 4 D Q 1 1
C 2 2 2
9 4 6
V D D Q 2 V S S Q 3
0.1u
1 0 4 5
CPU_DATA21
D Q 5 D Q 1 0
CPU_DATA22 1 1 4 4
D Q 6 D Q 9
1 2 4 3
V S S Q 2 V D D Q 3
CPU_DATA23 1 3 4 2
D Q 7 D Q 8
C 2 2 3
1 4 4 1
1000p V D D 2 V S S 2
1 5
CPU_ULDQM 4 0
L D Q M N . C / R F U
1 6 3 9
W E U D Q M
1 7 3 8
CPU_CAS
C A S C L K
1 8 3 7
CPU_RAS
R A S C K E
1 9 3 6
CPU_CS1
C S A 1 2
2 0 3 5
CPU_ADRS13
B A 0 A 1 1
2 1 3 4
CPU_ADRS14
B A 1 A 9
2 2 3 3
CPU_ADRS10
A 1 0 / A P A 8
2 3 3 2
CPU_ADRS0
A 0 A 7
2 4 3 1
CPU_ADRS1
A 1 A 6
CPU_ADRS2 2 5 3 0
A 2 A 5
CPU_ADRS3 2 6 2 9
A 3 A 4
C 2 2 4
2 7 2 8
V D D 3 V S S 1
0.1u
K4S561632J-UC75
High
256M SDRAM
CPU_ADDRESS_BUS
CPU_DATA_BUS
CPU_BUS
CPU-USB-ETH-SD
means STANDBY
RS1/16SS***J
*CAPACITORS
RS1/16SS****F
F
Indicated in Capacity/Voltage(V)
unless otherwise noted. u: μF, p: pF
CKSSYB
CCSSCH
CH *RESISTORS
Indicated in Ω, ± 5% tolerance
CEHVAW221M6R3
unless otherwise noted. k: kΩ, M: MΩ
CDJ-2000
7
E
1/3
MAIN ASSY (DWG1660)
A-a A-b
Guide page
Large size
A-b
SCH diagram
Detailed page
A-a A-b
CPU_ADDRESS_BUS
CPU_DATA_BUS
CPU-DSP-DAC-PANEL
5L
V+3R3_CPU
C P U _ D S P 7 1 0 _ B O O T
from CPU
C 2 4 3
0.1u
IC119
TC74LCX32FTS1
1 1 4
1 A
V C C
2 1 3
1 B
4 B
3 1 2
1 Y
4 A
4 1 1
2 A
4 Y
5 1 0
2 B
3 B
6 9
2 Y
3 A
7 8
11
G N D
3 Y
GNDD
CPU_DATA_BUS
CPU_DATA15
CPU_DATA14
CPU_DATA13
C 2 1 9
0.1u
CPU_DATA12
CPU_DATA11
CPU_DATA10
CPU_DATA9
C 2 2 0 CPU_DATA_BUS_R
1000p
CPU_BUS
CPU_DATA8
FLASH ROM
CPU_LUDQM
IC114
CPU_ADRS12
1
CPU_ADRS16R
A 1 5
CPU_ADRS11
2
CPU_ADRS15R
A 1 4 B Y T E #
CPU_ADRS9
3
CPU_ADRS14R R 3 7 4
A 1 3 V S S 2
1 0
CPU_ADRS8
4
CPU_ADRS13R R 3 7 5 D Q 1 5 / A - 1
A 1 2
1 0
CPU_ADRS7
5
CPU_ADRS12R R 3 7 6
A 1 1
1 0
CPU_ADRS6
6
CPU_ADRS11R R 3 7 7
A 1 0 D Q 1 4
1 0
CPU_ADRS5
7
CPU_ADRS10R R 3 7 8
A 9
1 0
CPU_ADRS4
CPU_ADRS9R 8
R 3 7 9
A 8 D Q 1 3
1 0
CPU_ADRS20R 9
A 1 9
CPU_ADRS21R 1 0
A 2 0 D Q 1 2
1F;5:1G;13:10K
1 1
C P U _ W E 0 W E #
from CPU 1 2
R E S E T #
GNDD
R 2 6 7 N M
1 3
CPU_ADRS22
A 2 1 D Q 1 1
11E
1 4
F L A S H _ R D Y
W P # / A C C
to CPU
R 2 6 8 0
1 5
R Y / B Y # D Q 1 0
1 6
CPU_ADRS19R
A 1 8
1 7
CPU_ADRS18R
A 1 7
1 8
CPU_ADRS8R R 3 8 0
A 7
1 0
1 9
CPU_ADRS7R R 3 8 1
A 6
1 0
2 0
CPU_ADRS6R R 3 8 2
A 5
1 0
2 1
CPU_ADRS5R R 3 8 3
A 4
1 0
CPU_ADRS4R 2 2
R 3 8 4
A 3 V S S 1
1 0
CPU_ADRS3R 2 3
R 3 8 5
A 2
1 0
CPU_ADRS2R 2 4
R 3 8 6
A 1
1 0
R 2 6 6
CPU_DATA31
R 2 9 5
680
N M
CPU_DATA30
S29GL032N90TFI030
CPU_DATA29
C 2 2 5
V+3R3_CPU
0.1u
CPU_DATA28
CPU_DATA27
CPU_DATA26
CPU_AUDATA0
CPU_DATA25
CPU_AUDATA2
C 2 2 6
1000p CPU_AUDSYNC
CPU_DATA24
CPU_MPMD
14
CPU_AUDATA1
CPU_AUDCK
CPU_UUDQM
CPU_AUDATA3
CPU_TDO
CPU_CKE
CPU_TCK
CPU_ADRS12
CPU_TMS
CPU_ADRS11
CPU_TDI
CPU_ADRS9
CPU_EMU_BRK
CPU_ADRS8
CPU_TRST
CPU_ADRS7
for Debug
CPU_ADRS6
CPU_ADRS5
V+3R3_CPU
CPU_ADRS4
CPU_MODE0
R 2 8 7
4 . 7 k
CPU_MODE1
R 2 8 8
4 . 7 k
CPU_MODE2
CPU_MODE3
GNDD
CPU_MODE4
R 2 9 1
4 . 7 k
CPU_MODE5
R 2 9 2
4 . 7 k
CPU_MODE7
CPU_MODE8
GNDD
7
8
A
E 2/3
1B;5:1B
CPU_ADDRESS_BUS
CPU-DSP-DAC-PANEL
1B;5:1A
CPU_DATA_BUS
1L;5:12H;5:1B;13:16B
C 1 9 9 B
0.1u
IC120
TC7SH04FUS1
5 1
V C C N C
2
I N A
4 3
O U T Y G N D
GNDD
CS distribute circuit
USB_CS
C
V+3R3_CPU
C 2 1 1
10u CCG1171-A-T
4 8
CPU_ADRS17R
A 1 6
4 7
4 6
4 5
CPU_DATA15
4 4
CPU_DATA7
D Q 7
4 3
CPU_DATA14
4 2
CPU_DATA6
D Q 6
4 1 CPU_DATA13
4 0 CPU_DATA5
D Q 5
3 9 CPU_DATA12
3 8 CPU_DATA4
D Q 4
3 7 C 2 1 4
V C C
3 6 0.1u
CPU_DATA11
3 5
CPU_DATA3
D Q 3
3 4
CPU_DATA10
3 3
CPU_DATA2
D Q 2
3 2
CPU_DATA9
D Q 9 D
3 1
CPU_DATA1
D Q 1
3 0
CPU_DATA8
D Q 8
2 9
CPU_DATA0
D Q 0
2 8 from CPU
O E # C P U _ R D
11E;5:1G;13:10K
2 7
R 2 9 7
2 6 FLASH_CS
4.7k
C E #
2 5 CPU_ADRS1R
A 0
GNDD
C N 1 0 1
C K S 5 0 6 4 - A
1
12C;9A;13:14I
C P U _ R S T
2
From RESET IC
R E S T _ E R
3
for DEBUG
8A
4
5
6
7
8
9
1 0
1 1
1 2
E
1 3
1 4
1 5
1 6
1 7
1 k
R 3 3 2
GNDD
MODE[2:0] CLOCK MODE
010(2):X10
011(3):X12
OTHER:NG
MODE[4:3] BUS WIDTH
00(0):RESERVED
01(1):SRAM 8bit
10(2):SRAM 16bit
11(3):SRAM 32bit
MODE5 ENDIAN
0:BIG
1:LITTLE
MODE7 USB CLOCK
0:EXT CLOCK
1:XTAL
MODE8 SYSTEM CLOCK
0:EXT CLOCK
1:XTAL
F
E
1/3
93
8