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3. IC903 (H Driver) and IC902 (V Driver)
An H driver (IC903) and V driver (IC902) are necessary in
order to generate the clocks (vertical transfer clock, horizon-
tal transfer clock and electronic shutter clock) which driver
the CCD.
IC902 is an inverter IC which drives the horizontal CCDs (H1
and H2). In addition the VREG 0~7, VXREG2 and VXREG3
signals which are output from IC102 are the vertical transfer
clocks. The clock is drived until peak value which necessary
CCD at IC902.
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
Fig. 1-3. IC903 Block Diagram
14
V
CC
13
6A
12
6Y
11
5A
10
5Y
4A
9
8
4Y
GND
1
OUT_1
2
3
OUT_2
OUT_3
4
5
OUT_4
OUT_5
6
OUT_6
7
OUT_7
8
OUT_8
9
OUT_9
10
OUT_10
11
12
OUT_NSUB
13
CAP5V
14
CAPNS
15
Power circuit
GND
Fig. 1-4. IC902 Block Diagram
4. IC901 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
Pins (26) and (27) of IC901. There are S/H blocks inside IC905
generated from the XSHP and XSHD pulses, and it is here
that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 10-bit signal, and is then input to IC102.
PBLK
CLPDM
19
23
CLAMP
27
PIN
CDS
26
DIN
36
ADCIN
REFERENCE
37
48
47
CMLEVEL VRT VTB STBY CLPOB ADCMODE
Fig. 1-5. IC901 Block Diagram
30
VDD
29
OCNT
28
DUTY
OCNT circuit
27
IN_1
DUTY circuit
26
IN_2
25
IN_3
24
IN_4
IN_5
23
22
IN_6
21
IN_7
20
IN_8
19
IN_9
18
IN_10
OCNT circuit
IN_NSUB
17
16
VDD
– 3 –
SHP SHD ADCCLK
29
30
21
22
16
TIMING
GENERATOR
PGA
10
2
A/D
MUX S/H
11
12
CLAMP
AD9802
17
20
41
33
18
43
ACVDD
ADVDD
DOUT
DRVDD
DVDD
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