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HP 27130A
Interrupt acknowledge to the devices listed above is accomplished by the Z-80B CPU executing a
special Ml- cycle (see D24, 7-1) in which IORQ- goes active instead of MREQ- and RO-.
Whenever M 1- goes active, all devices are inhibited from changing their interrupt status. This
allows time for IEO- to propagate through the other devices in the chain before 10RQ- goes active.
As soon as 10RQ- and Ml- go active, the device that has its lEI signal high, and an interrupt
pending, gates an 8-bit interrupt vector onto the data bus.
In order to guarantee that the MUX card's long daisy chain is stable before IORQ- is active,
IORQ- is delayed by at least half of a T-state (see figure 3-6 for T-state timing). With this ex-
tended T-state, the total time between M 1- going active and IORQ- going active is at least 710
nsec, which is long enough for the daisy chain to become stable.
Figure 3-5 shows the MUX card's wait circuit for an interrupt acknowledge cycle. The ZIORQ-
and Ml- signals are the inputs from the Z-80B CPU. IORQ- and WAIT- are the outplits from the
wait circuit. 10RQ- drives all the devices (SIOs, MIC, and CTC 0), WAIT- drives the input of a
74LS08 AND gate.
The output of the AND gate drives the WAIT- input of the Z- 80B CPU.
Except during an interrupt acknowledge cycle, IORQ- always follows ZIORQ- of the Z- 80B CPU
with a maximum of 22 nsec delay. During an interrupt acknowledge cycle, IORQ- is asserted half a
T-state after ZIORQ-, at the rising edge of the following T-state. At the same time, WAIT- is also
asserted for one full T-state to add an additional wait state. 10RQ- follows ZIORQ- on the rising
edge (de-asserting edge).
The timing diagram of the wait state circuit is shown in figure 3-6.
DIAGNOSTIC HOOD FOR EXTERNAL LOOP BACK
A diagnostic test hood (part number 0950-1659) can be ordered and used to test the
RS-232-C/RS-423-A single-ended drivers, the RS-422-A differential drivers, and the receivers.
One diode and one resistor are used for each channel of the MUX card. A total of eight diodes and
eight resistors are needed to test all eight channels of the MUX. A schematic diagram of one channel
of the test hood, with the drivers and receivers for one MUX channel, is shown in figure 3-7.
When the single-ended drivers are being tested, the EN_SEO- signal (RTSA- of SIO 0, see B42,
figure 7-1) must be asserted (LOW level), and the EN_DO signal (DTRB- of SIO
0)
must be unas-
serted (LOW level).
When the differential drivers are being tested, the EN_DD signal (DTRB- of SIO 0) must be as-
serted (HIGH level), and the EN_SED- signal (RTSA- of SIO 0) must be unasserted (HIGH level).
Using the diagnostic hood, the data sent from the transmit channels will loop back to the cor-
responding receive channels through the enabled drivers. For example, channell loops back to chan-
nel I, channel 2 loops back to channel 2, and so forth.
The diagnostic hood has an LED to indicate that the self -test firmware detected the presence of
the hood. The control circuit for the hood LED and hood sensing is shown in figure 3-4.
3-28
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