HP 27130A Technical Reference Manual page 57

HP 27130A
TL TI T2 TW TW
lW.
T3
eLK
INT-
\
/
M1-
\
I
ZIORQ-
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I
IORQ-
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I
W/4JT-
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TW
=
W/4JT STATE CENERATEO BY Z-80B CPU AUTOMAnCALLY DURING AN INTERRUPT ACKNOWLEDGE CYCLE
TW •• W/4JT STATE GENERATED BY WAIT STATE CIRCUIT
Figure 3-6. Wait State Circuit Timing Diagram
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