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HP 27130A
The following time-line illustrates the host/card interactions during the self-test sequence:
Host
to
sends card
DCl or asserts
RES after a
power-on
Teach card
PA.
Wait time t2
or poll PST
where:
t1
t2
t1
=
1.0 second
Card
Self-test begun
Successful:
Set PST
Turn off lED
Unsuccessful:
Hal
t
Z80
t2
=
3 seconds if RES, or 15 seconds if DCl/DEN;
may
be less
CONNECT LOGICAL CHANNEL REQUEST DEFINITIONS
The following paragraphs describe the subfunction options that are available for each Connect
Logical Channel (CLC) request. See the paragraph "Connect Logical Channel (CLC) Request Format"
for a description of the data format.
4-21
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