Epson S1C31W65 Manuals

Manuals and User Guides for Epson S1C31W65. We have 1 Epson S1C31W65 manual available for free PDF download: Technical Manual

Epson S1C31W65 Technical Manual (367 pages)

CMOS 32-BIT SINGLE CHIP MICROCONTROLLER

Brand: Epson | Category: Microcontrollers | Size: 10.73 MB

Table of Contents
4
Overview
15
Features
15
Block Diagram
17
Pins
18
Pin Configuration Diagram
18
Pin Descriptions
19
Power Supply, Reset, and Clocks
23
Power Generator (PWGA)
23
Overview
23
Pins
23
D1 Regulator Operation Mode
24
D1 Regulator Voltage Mode
24
System Reset Controller (SRC)
25
Overview
25
Input Pin
26
Reset Sources
26
Reset Request Flag
27
RESET Pin Input Control
27
Initialization Conditions (Reset Groups)
28
Clock Generator (CLG)
29
Overview
29
Input/Output Pins
30
Clock Sources
30
Operations
33
Operating Mode
38
Initial Boot Sequence
38
Transition between Operating Modes
38
Interrupts
40
Control Registers
40
PWGA Control Register
40
SRC Reset Request Flag Register
41
SRC #RESET Port Control Register
41
CLG System Clock Control Register
42
CLG Oscillation Control Register
43
CLG IOSC Control Register
44
CLG OSC1 Control Register
45
CLG OSC3 Control Register
46
CLG Interrupt Flag Register
47
CLG Interrupt Enable Register
48
CLG FOUT Control Register
48
CLG Oscillation Frequency Trimming Register 1
49
CLG Oscillation Frequency Trimming Register 2
50
CPU and Debugger
51
Overview
51
Cpu
51
Debugger
51
List of Debugger Input/Output Pins
51
External Connection
51
Reference Documents
52
Memory and Bus
53
Overview
53
Bus Access Cycle
54
Flash Memory
54
Flash Memory Pin
54
Flash Bus Access Cycle Setting
54
Flash Programming
54
Ram
55
Display Data RAM
55
Peripheral Circuit Control Registers
55
System-Protect Function
61
Control Registers
61
System Protect Register
61
FLASHC Flash Read Cycle Register
62
Interrupt
63
Overview
63
Vector Table
63
Vector Table Offset Address (VTOR)
65
Priority of Interrupts
65
Peripheral Circuit Interrupt Control
65
Nmi
65
DMA Controller (DMAC)
66
Overview
66
Operations
67
Initialization
67
Priority
67
Data Structure
67
Transfer Source End Pointer
68
Transfer Destination End Pointer
68
Control Data
68
DMA Transfer Mode
70
Basic Transfer
70
Auto-Request Transfer
70
Ping-Pong Transfer
71
Memory Scatter-Gather Transfer
72
Peripheral Scatter-Gather Transfer
73
DMA Transfer Cycle
74
Interrupts
74
Control Registers
75
DMAC Status Register
75
DMAC Configuration Register
75
DMAC Control Data Base Pointer Register
76
DMAC Alternate Control Data Base Pointer Register
76
DMAC Software Request Register
76
DMAC Request Mask Set Register
76
DMAC Request Mask Clear Register
77
DMAC Enable Set Register
77
DMAC Enable Clear Register
77
DMAC Primary-Alternate Set Register
77
DMAC Primary-Alternate Clear Register
78
DMAC Priority Set Register
78
DMAC Priority Clear Register
78
DMAC Error Interrupt Flag Register
78
DMAC Transfer Completion Interrupt Flag Register
79
DMAC Transfer Completion Interrupt Enable Set Register
79
DMAC Transfer Completion Interrupt Enable Clear Register
79
DMAC Error Interrupt Enable Set Register
79
DMAC Error Interrupt Enable Clear Register
80
O Ports (PPORT)
81
Overview
81
I/O Cell Structure and Functions
82
Schmitt Input
82
Over Voltage Tolerant Fail-Safe Type I/O Cell
82
Pull-Up/Pull-Down
82
CMOS Output and High Impedance State
83
Clock Settings
83
PPORT Operating Clock
83
Clock Supply in SLEEP Mode
83
Clock Supply During Debugging
83
Operations
83
Initialization
83
Port Input/Output Control
85
Interrupts
86
Control Registers
86
Px Port Data Register
86
Px Port Enable Register
87
Px Port Pull-Up/Down Control Register
87
Px Port Interrupt Flag Register
88
Px Port Interrupt Control Register
88
Px Port Chattering Filter Enable Register
88
Px Port Mode Select Register
88
Px Port Function Select Register
89
P Port Clock Control Register
89
P Port Interrupt Flag Group Register
90
Control Register and Port Function Configuration of this IC
91
P0 Port Group
91
P1 Port Group
92
P2 Port Group
93
P3 Port Group
94
P4 Port Group
95
P5 Port Group
96
P6 Port Group
97
Pd Port Group
98
Common Registers between Port Groups
99
Universal Port Multiplexer (UPMUX)
100
Overview
100
Peripheral Circuit I/O Function Assignment
100
Control Registers
101
Pxy-Xz Universal Port Multiplexer Setting Register
101
Watchdog Timer (WDT2)
102
Overview
102
Clock Settings
102
WDT2 Operating Clock
102
Clock Supply in DEBUG Mode
102
Operations
103
WDT2 Control
103
Operations in HALT and SLEEP Modes
104
Control Registers
104
WDT2 Clock Control Register
104
WDT2 Control Register
105
WDT2 Counter Compare Match Register
106
Real-Time Clock (RTCA)
107
Overview
107
Output Pin and External Connection
107
Output Pin
107
Clock Settings
108
RTCA Operating Clock
108
Theoretical Regulation Function
108
Operations
109
RTCA Control
109
Real-Time Clock Counter Operations
110
Stopwatch Control
110
Stopwatch Count-Up Pattern
110
Interrupts
111
Control Registers
112
RTCA Control Register (Low Byte)
112
RTCA Control Register (High Byte)
113
RTCA Second Alarm Register
113
RTCA Hour/Minute Alarm Register
114
RTCA Stopwatch Control Register
114
RTCA Second/1Hz Register
115
RTCA Hour/Minute Register
116
RTCA Month/Day Register
117
RTCA Year/Week Register
117
RTCA Interrupt Flag Register
118
RTCA Interrupt Enable Register
119
Supply Voltage Detector (SVD4)
121
Overview
121
Input Pins and External Connection
122
Input Pins
122
External Connection
122
Clock Settings
122
SVD4 Operating Clock
122
Clock Supply in SLEEP Mode
122
Clock Supply in DEBUG Mode
123
Operations
123
SVD4 Control
123
SVD4 Operations
124
SVD4 Interrupt and Reset
124
SVD4 Interrupt
124
SVD Reset
125
Control Registers
125
SVD4 Ch.n Clock Control Register
125
SVD4 Ch.n Control Register
126
S1C31W65 Technical Manual
126
Seiko Epson Corporation
126
SVD4 Ch.n Status and Interrupt Flag Register
127
SVD4 Ch.n Interrupt Enable Register
128
16-Bit Timers (T16)
129
Overview
129
Input Pin
129
Clock Settings
130
T16 Operating Clock
130
Clock Supply in SLEEP Mode
130
Clock Supply During Debugging
130
Event Counter Clock
130
Operations
130
Initialization
130
Counter Underflow
131
Operations in Repeat Mode
131
Operations in One-Shot Mode
131
Counter Value Read
132
Interrupt
132
Control Registers
132
T16 Ch.n Clock Control Register
132
T16 Ch.n Control Register
133
T16 Ch.n Reload Data Register
134
T16 Ch.n Counter Data Register
134
T16 Ch.n Interrupt Flag Register
134
T16 Ch.n Interrupt Enable Register
135
Uart (Uart3)
136
Overview
136
Input/Output Pins and External Connections
137
List of Input/Output Pins
137
External Connections
137
Input Pin Pull-Up Function
137
Output Pin Open-Drain Output Function
137
Input/Output Signal Inverting Function
137
Clock Settings
137
UART3 Operating Clock
137
Clock Supply in SLEEP Mode
138
Clock Supply During Debugging
138
Baud Rate Generator
138
Data Format
138
Operations
139
Initialization
139
Data Transmission
140
Data Reception
141
Carrier Modulation
143
Receive Errors
144
Framing Error
144
Parity Error
144
Overrun Error
144
Interrupts
145
DMA Transfer Requests
145
Control Registers
146
UART3 Ch.n Clock Control Register
146
UART3 Ch.n Mode Register
146
UART3 Ch.n Baud-Rate Register
148
UART3 Ch.n Control Register
148
UART3 Ch.n Transmit Data Register
149
UART3 Ch.n Receive Data Register
149
UART3 Ch.n Status and Interrupt Flag Register
149
UART3 Ch.n Interrupt Enable Register
150
UART3 Ch.n Transmit Buffer Empty DMA Request Enable Register
151
UART3 Ch.n Receive Buffer One Byte Full DMA Request Enable Register
151
UART3 Ch.n Carrier Waveform Register
151
Synchronous Serial Interface (SPIA)
152
Overview
152
Input/Output Pins and External Connections
153
List of Input/Output Pins
153
External Connections
153
Pin Functions in Master Mode and Slave Mode
154
Input Pin Pull-Up/Pull-Down Function
154
Clock Settings
154
SPIA Operating Clock
154
Clock Supply During Debugging
155
SPI Clock (Spiclkn) Phase and Polarity
155
Data Format
156
Operations
156
Initialization
156
Data Transmission in Master Mode
157
Data Reception in Master Mode
159
Terminating Data Transfer in Master Mode
161
Data Transfer in Slave Mode
161
Terminating Data Transfer in Slave Mode
162
Interrupts
163
DMA Transfer Requests
164
Control Registers
164
SPIA Ch.n Mode Register
164
SPIA Ch.n Control Register
165
SPIA Ch.n Transmit Data Register
166
SPIA Ch.n Receive Data Register
166
SPIA Ch.n Interrupt Flag Register
166
SPIA Ch.n Interrupt Enable Register
167
SPIA Ch.n Transmit Buffer Empty DMA Request Enable Register
167
SPIA Ch.n Receive Buffer Full DMA Request Enable Register
167
C (I2C)
168
Overview
168
Input/Output Pins and External Connections
169
List of Input/Output Pins
169
External Connections
169
Clock Settings
170
I2C Operating Clock
170
Clock Supply During Debugging
170
Baud Rate Generator
170
Operations
171
Initialization
171
Data Transmission in Master Mode
172
Data Reception in Master Mode
174
10-Bit Addressing in Master Mode
177
Data Transmission in Slave Mode
178
Data Reception in Slave Mode
180
Slave Operations in 10-Bit Address Mode
182
Automatic Bus Clearing Operation
182
Error Detection
183
Interrupts
184
DMA Transfer Requests
185
Control Registers
185
I2C Ch.n Clock Control Register
185
I2C Ch.n Mode Register
186
I2C Ch.n Baud-Rate Register
186
I2C Ch.n Own Address Register
187
I2C Ch.n Control Register
187
I2C Ch.n Transmit Data Register
188
I2C Ch.n Receive Data Register
188
I2C Ch.n Status and Interrupt Flag Register
189
I2C Ch.n Interrupt Enable Register
190
I2C Ch.n Transmit Buffer Empty DMA Request Enable Register
191
I2C Ch.n Receive Buffer Full DMA Request Enable Register
191
16-Bit PWM Timers (T16B)
192
Overview
192
Input/Output Pins
193
Clock Settings
194
T16B Operating Clock
194
Clock Supply in SLEEP Mode
194
Clock Supply During Debugging
194
Event Counter Clock
194
Operations
195
Initialization
195
Counter Block Operations
196
Comparator/Capture Block Operations
199
TOUT Output Control
208
Interrupt
214
DMA Transfer Requests
214
Control Registers
214
T16B Ch.n Clock Control Register
214
T16B Ch.n Counter Control Register
215
T16B Ch.n Max Counter Data Register
216
T16B Ch.n Timer Counter Data Register
216
T16B Ch.n Counter Status Register
217
T16B Ch.n Interrupt Flag Register
218
T16B Ch.n Interrupt Enable Register
219
T16B Ch.n Comparator/Capture M Control Register
220
T16B Ch.n Compare/Capture M Data Register
222
T16B Ch.n Counter Max/Zero DMA Request Enable Register
223
T16B Ch.n Compare/Capture M DMA Request Enable Register
223
Sound Generator (SNDA)
224
Overview
224
Output Pins and External Connections
225
List of Output Pins
225
Output Pin Drive Mode
225
External Connections
225
Clock Settings
226
SNDA Operating Clock
226
Clock Supply in SLEEP Mode
226
Clock Supply in DEBUG Mode
226
Operations
226
Initialization
226
Buzzer Output in Normal Buzzer Mode
226
Buzzer Output in One-Shot Buzzer Mode
229
Output in Melody Mode
230
Interrupts
232
DMA Transfer Requests
233
Control Registers
233
SNDA Clock Control Register
233
SNDA Select Register
234
SNDA Control Register
235
SNDA Data Register
235
SNDA Interrupt Flag Register
236
SNDA Interrupt Enable Register
236
SNDA Sound Buffer Empty DMA Request Enable Register
237
IR Remote Controller (REMC3)
238
Overview
238
Output Pins and External Connections
238
List of Output Pins
238
External Connections
239
Clock Settings
239
REMC3 Operating Clock
239
Clock Supply in SLEEP Mode
239
Clock Supply During Debugging
239
Operations
239
Initialization
239
Data Transmission Procedures
240
REMO Output Waveform
240
Continuous Data Transmission and Compare Buffers
242
Interrupts
243
Application Example: Driving el Lamp
244
Control Registers
244
REMC3 Clock Control Register
244
REMC3 Data Bit Counter Control Register
245
REMC3 Data Bit Counter Register
246
REMC3 Data Bit Active Pulse Length Register
247
REMC3 Data Bit Length Register
247
REMC3 Status and Interrupt Flag Register
247
REMC3 Interrupt Enable Register
248
REMC3 Carrier Waveform Register
248
REMC3 Carrier Modulation Control Register
248
12-Bit A/D Converter (ADC12A)
250
Overview
250
Input Pins and External Connections
251
List of Input Pins
251
External Connections
251
Clock Settings
251
ADC12A Operating Clock
251
Sampling Time
251
Operations
252
Initialization
252
Conversion Start Trigger Source
252
Conversion Mode and Analog Input Pin Settings
253
A/D Conversion Operations and Control Procedures
253
Interrupts
255
DMA Transfer Requests
255
Control Registers
256
ADC12A Ch.n Control Register
256
ADC12A Ch.n Trigger/Analog Input Select Register
257
ADC12A Ch.n Configuration Register
258
ADC12A Ch.n Interrupt Flag Register
259
ADC12A Ch.n Interrupt Enable Register
259
ADC12A Ch.n DMA Request Enable Register M
260
ADC12A Ch.n Result Register
260
Temperature Sensor/Reference Voltage Generator (TSRVR)
261
Overview
261
Output Pin and External Connections
261
Output Pin
261
External Connections
262
Operations
262
Reference Voltage Setting
262
Temperature Sensor Setting
262
Control Registers
263
TSRVR Ch.n Temperature Sensor Control Register
263
TSRVR Ch.n Reference Voltage Generator Control Register
263
LCD Driver (LCD8D)
264
Overview
264
Output Pins and External Connections
265
List of Output Pins
265
External Connections
265
Clock Settings
266
LCD8D Operating Clock
266
Clock Supply in SLEEP Mode
266
Clock Supply in DEBUG Mode
266
Frame Frequency
266
LCD Power Supply
267
Internal Generation Mode
267
LCD Power Supply Circuit Settings
269
Operations
269
Initialization
269
Display On/Off
270
Inverted Display
270
Drive Duty Switching
270
Drive Waveforms
271
Partial Common Output Drive
280
N-Segment-Line Inverse AC Drive
280
Display Data RAM
280
Display Area Selection
280
Common Pin Assignment
281
Interrupt
283
Control Registers
283
LCD8D Clock Control Register
283
LCD8D Control Register
284
LCD8D Power Control Register
285
LCD8D Display Control Register
287
LCD8D COM Pin Control Register 0
287
LCD8D Interrupt Flag Register
288
LCD8D Interrupt Enable Register
288
F Converter (RFC)
289
Overview
289
Input/Output Pins and External Connections
290
List of Input/Output Pins
290
Clock Settings
291
RFC Operating Clock
291
Clock Supply in SLEEP Mode
291
Clock Supply in DEBUG Mode
291
Operations
291
Initialization
291
Operating Modes
292
Converting Operations and Control Procedure
293
CR Oscillation Frequency Monitoring Function
295
Interrupts
295
Control Registers
296
RFC Ch.n Clock Control Register
296
RFC Ch.n Control Register
296
RFC Ch.n Oscillation Trigger Register
297
RFC Ch.n Measurement Counter Low and High Registers
298
RFC Ch.n Time Base Counter Low and High Registers
298
RFC Ch.n Interrupt Flag Register
299
RFC Ch.n Interrupt Enable Register
299
Electrical Characteristics
300
Current Consumption
301
System Reset Controller (SRC) Characteristics
303
Clock Generator (CLG) Characteristics
304
Flash Memory Characteristics
306
Input/Output Port (PPORT) Characteristics
307
Supply Voltage Detector (SVD4) Characteristics
308
UART (UART3) Characteristics
310
I 2 C (I2C) Characteristics
313
12-Bit A/D Converter (ADC12A) Characteristics
320
Temperature Sensor/Reference Voltage Generator (TSRVR) Characteristics
321
Basic External Connection Diagram
322
Package
324
Appendix A List of Peripheral Circuit Control Registers
325
System Register (SYS)
325
Power Generator (PWGA)
325
0X4000 03A0-0X4000 03Ac 16-Bit Timer (T16) Ch.1
337
0X4000 03B0-0X4000 03Be Synchronous Serial Interface (SPIA) Ch.0
337
0X4000 0400-0X4000 042C 16-Bit PWM Timer (T16B) Ch.0
339
0X4000 0660-0X4000 066C 16-Bit Timer (T16) Ch.6
347
0X4000 0670-0X4000 067E Synchronous Serial Interface (SPIA) Ch.1
347
0X4000 06C0-0X4000 06D6 I 2 C (I2C) Ch.1
349
0X4000 0740-0X4000 076C 16-Bit PWM Timer (T16B) Ch.2
351
0X4000 07C0-0X4000 07C2 Temperature Sensor
355
0X4000 0840-0X4000 0850 R/F Converter (RFC) Ch.0
357
0X4000 1000-0X4000 2014 DMA Controller (DMAC)
357
Appendix B Power Saving
360
Operating Status Configuration Examples for Power Saving
360
Other Power Saving Methods
361
Appendix D Measures against Noise
364
Revision History
365

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Epson S1C31W65 Technical Manual (367 pages)

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