Epson S1C31W65 Technical Manual
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Epson S1C31W65 Technical Manual

Cmos 32-bit single chip microcontroller
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CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C31W65
Technical Manual
Rev. 1.1

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Summary of Contents for Epson S1C31W65

  • Page 1 CMOS 32-BIT SINGLE CHIP MICROCONTROLLER S1C31W65 Technical Manual Rev. 1.1...
  • Page 2 2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by its use.
  • Page 3 PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C31W65. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. Notational conventions and symbols in this manual Register address Peripheral circuit chapters do not provide control register addresses.

  • Page 4: Table Of Contents

    CLG Oscillation Frequency Trimming Register 2 ..............2-28 3 CPU and Debugger ......................3-1 3.1 Overview ......................... 3-1 3.2 CPU ..........................3-1 3.3 Debugger ........................3-1 3.3.1 List of Debugger Input/Output Pins ..............3-1 3.3.2 External Connection ..................3-1 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 5 DMAC Request Mask Set Register ..................6-11 DMAC Request Mask Clear Register ..................6-12 DMAC Enable Set Register ...................... 6-12 DMAC Enable Clear Register ....................6-12 DMAC Primary-Alternate Set Register ..................6-12 DMAC Primary-Alternate Clear Register .................. 6-13 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 6 8.2 Peripheral Circuit I/O Function Assignment ..............8-1 8.3 Control Registers ......................8-2 Pxy–xz Universal Port Multiplexer Setting Register ..............8-2 9 Watchdog Timer (WDT2) ....................9-1 9.1 Overview ......................... 9-1 9.2 Clock Settings ......................... 9-1 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 7 11.5 SVD4 Interrupt and Reset .................... 11-4 11.5.1 SVD4 Interrupt ....................11-4 11.5.2 SVD Reset ...................... 11-5 11.6 Control Registers ......................11-5 SVD4 Ch.n Clock Control Register ..................11-5 SVD4 Ch.n Control Register ..................... 11-6 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 8 13.6 Receive Errors ......................13-9 13.6.1 Framing Error ....................13-9 13.6.2 Parity Error ..................... 13-9 13.6.3 Overrun Error ....................13-9 13.7 Interrupts ........................13-10 13.8 DMA Transfer Requests ....................13-10 13.9 Control Registers ......................13-11 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 9 15.3.1 I2C Operating Clock ..................15-3 15.3.2 Clock Supply During Debugging ..............15-3 15.3.3 Baud Rate Generator ..................15-3 15.4 Operations ........................15-4 15.4.1 Initialization ....................15-4 15.4.2 Data Transmission in Master Mode ............... 15-5 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 10 17 Sound Generator (SNDA) ..................17-1 17.1 Overview ........................17-1 17.2 Output Pins and External Connections ................ 17-2 17.2.1 List of Output Pins ..................17-2 17.2.2 Output Pin Drive Mode .................. 17-2 Seiko Epson Corporation viii S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 11 19 12-bit A/D Converter (ADC12A) ................19-1 19.1 Overview ........................19-1 19.2 Input Pins and External Connections ................19-2 19.2.1 List of Input Pins .................... 19-2 19.2.2 External Connections ..................19-2 19.3 Clock Settings ......................19-2 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 12 21.5.2 Display On/Off ....................21-7 21.5.3 Inverted Display ..................... 21-7 21.5.4 Drive Duty Switching ..................21-7 21.5.5 Drive Waveforms .................... 21-8 21.5.6 Partial Common Output Drive............... 21-17 21.5.7 n-Segment-Line Inverse AC Drive ..............21-17 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 13 23.8 Supply Voltage Detector (SVD4) Characteristics ............23-9 23.9 UART (UART3) Characteristics ................... 23-11 23.10 Synchronous Serial Interface (SPIA) Characteristics ..........23-12 23.11 I C (I2C) Characteristics .................... 23-14 23.12 LCD Driver (LCD8D) Characteristics ................. 23-14 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 14 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Revision History Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 15: Overview

    1 OVERVIEW 1 Overview The S1C31W65 is a 32-bit MCU with an Arm Cortex -M0+ processor included that features low-power operation. It ® ® incorporates a lot of serial interface circuits and is suitable for various kinds of battery-driven controller applications.
  • Page 16 0.8 µA IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF, RTCA = ON HALT mode 1.5 µA OSC1 = 32.768 kHz (crystal oscillator) 4.0 µA OSC1 = 32.768 kHz (crystal oscillator), LCD = ON (no panel load) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 17: Block Diagram

    (T16B) CAP10–13 LFRO 3 Ch. CAP20–23 C1–3 EXCL00–01 P1–2 EXCL10–11 EXCL20–21 RFIN0 R/F converter REF0 UART (RFC) SENA0 USIN0–1 (UART3) 1 Ch. SENB0 USOUT0–1 2 Ch. RFCLKO0 Figure 1.2.1 S1C31W65 Block Diagram Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 18: Pins

    P11/UPMUX/ADIN05 SEG28 SEG27 P10/UPMUX/ADIN06 SEG27 SEG26 SEG26 P07/RFIN0/UPMUX SEG25 SEG25 P06/REF0/UPMUX P50/SEG24 P05/SENA0/UPMUX P51/SEG23 P04/SENB0/UPMUX P03/#SPISS1/UPMUX P52/SEG22 P02/SPICLK1/UPMUX P53/SEG21 P01/SDO1/UPMUX P54/SEG20 P55/SEG19 P00/SDI1/UPMUX P56/SEG18 P57/SEG17 Figure 1.3.1.1 S1C31W65 Pin Configuration Diagram (TQFP14-100PIN) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 19: Pin Descriptions

    User-selected I/O (universal port multiplexer) ADIN05 12-bit A/D converter Ch.0 analog signal input 5 Hi-Z – I/O port UPMUX User-selected I/O (universal port multiplexer) ADIN04 12-bit A/D converter Ch.0 analog signal input 4 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 20 User-selected I/O (universal port multiplexer) SEG45 LCD segment output Hi-Z I/O port ✓ FOUT Clock external output UPMUX User-selected I/O (universal port multiplexer) SEG44 12-bit A/D converter Ch.0 analog signal input 3 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 21 Hi-Z I/O port ✓ SEG13 LCD segment output Hi-Z I/O port ✓ COM7 LCD common output SEG3 LCD segment output Hi-Z I/O port ✓ COM6 LCD common output SEG2 LCD segment output Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 22 T16B Ch.n PWM output/capture input 1 TOUTn2/CAPn2 T16B Ch.n PWM output/capture input 2 TOUTn3/CAPn3 T16B Ch.n PWM output/capture input 3 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 23: Power Supply, Reset, And Clocks

    For the V operating voltage range and recommended external parts, refer to “Recommended Operating Condi- tions, Power supply voltage V ” in the “Electrical Characteristics” chapter and the “Basic External Connection Diagram” chapter, respectively. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 24: D1 Regulator Operation Mode

    6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Note: After the voltage mode has been switched, correct the RTC, as the RTC operating clock is also stopped for the period set using the CLGOSC1.OSC1WT[1:0] bits. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 25: System Reset Controller (Src)

    Supply voltage detector reset circuit SVDRSTREQ Reset request from CPU SYSRST_S0_0 Software reset 0 To peripheral circuit 0 Reset decoder SYSRST_S0_n Software reset n To peripheral circuit n Figure 2.2.1.1 SRC Configuration Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 26: Input Pin

    This makes it possible to put the system into reset state if the IC must be stopped under a low voltage condition. For more information, refer to the “Supply Volt- age Detector” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 27: Reset Request Flag

    The #RESET pin has a built-in pull-up resistor and it can be disabled by setting the SRCRESETPCTL.PORT_ PLUP_EN bit to 0. PORT_PLUP_EN PORT_RESET_EN #RESET pin reset request signal #RESET Figure 2.2.5.1 #RESET Pin Input Control Circuit Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 28: Initialization Conditions (Reset Groups)

    POR and BOR Peripheral circuit software reset Reset state is canceled immediately (MODEN and SFTRST bits. The after the reset request is canceled. software reset operations de- pend on the peripheral circuit. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 29: Clock Generator (Clg)

    Ceramic3 EXOSCEN EXOSC EXOSC EXOSCCLK clock input circuit FOUTEN Peripheral circuit 1 FOUT FOUT Clock output CLKSRC[x:0] selector circuit CLKDIV[x:0] FOUTDIV[2:0] Peripheral circuit n Clock CLKSRC[x:0] selector CLKDIV[x:0] Figure 2.3.1.1 CLG Configuration Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 30: Input/Output Pins

    For more information on the auto- trimming function and the oscillation characteristics, refer to “IOSC oscillation auto-trimming function” in this chapter and “IOSC oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 31 OSC2 pin open. For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 32 EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation 2-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 33: Operations

    Figure 2.3.4.2 shows an operation example when the oscillation start- up control circuit is used. (1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1N[1:0] setting gain Oscillation waveform Normal operation Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-11 (Rev. 1.1)
  • Page 34 CLGOSC1.INV1B[1:0], and CLGTRIM2.OSC1SAJ[5:0] bits should be determined after performing evaluation using the populated circuit board. Note: Make sure the CLGOSC.OSC1EN bit is set to 0 (while the OSC1 oscillation is halted) when set- ting the CLGTRIM2.OSC1SAJ[5:0] bits. Seiko Epson Corporation 2-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 35 RUN mode, and the peripheral circuits to continue operating without disabling the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-13 (Rev. 1.1)
  • Page 36 2. Configure the following CLGFOUT register bits: - CLGFOUT.FOUTSRC[1:0] bits (Select clock source) - CLGFOUT.FOUTDIV[2:0] bits (Set clock division ratio) - Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output) Seiko Epson Corporation 2-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 37 7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current (I OSD1 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-15 (Rev. 1.1)

  • Page 38: Operating Mode

    0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this mode when no software processing and peripheral circuit operations are required, power consumption can be less than HALT mode. The RAM retains data even in SLEEP mode. Seiko Epson Corporation 2-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 39 The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Reset request Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-17 (Rev. 1.1)

  • Page 40: Interrupts

    Bits 3–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the V regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGACTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode Seiko Epson Corporation 2-18 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 41: Src Reset Request Flag Register

    0 (R/WP): Disable pull-up Bit 0 PORT_RESET_EN This bit enables the #RESET pin to input the external reset signal. 1 (R/WP): Enable external reset input 0 (R/WP): Disable external reset input Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-19 (Rev. 1.1)

  • Page 42: Clg System Clock Control Register

    These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation 2-20 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 43: Clg Oscillation Control Register

    Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-21 (Rev. 1.1)

  • Page 44: Clg Iosc Control Register

    IOSCFQ[2:0] bits voltage mode = mode0 voltage mode = mode1 32 MHz 24 MHz 16 MHz Setting prohibited 12 MHz 8 MHz Setting prohibited 2 MHz 2 MHz 1 MHz 1 MHz Seiko Epson Corporation 2-22 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 45: Clg Osc1 Control Register

    For more information, refer to “OSC1 oscillator circuit characteristics, Internal gate capacitance C ” in the “Electrical Characteristics” chapter. Bits 7–6 INV1B[1:0] These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 oscillator circuit. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-23 (Rev. 1.1)

  • Page 46: Clg Osc3 Control Register

    16 MHz 12 MHz 0x3–0x0 8 MHz Bit 9 OSC3MD This bit selects an oscillator type of the OSC3 oscillator circuit. 1 (R/WP): Crystal/ceramic oscillator 0 (R/WP): Internal oscillator Bits 8–6 Reserved Seiko Epson Corporation 2-24 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 47: Clg Interrupt Flag Register

    Bit 0 IOSCSTAIF These bits indicate the CLG interrupt cause occurrence statuses. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-25 (Rev. 1.1)

  • Page 48: Clg Interrupt Enable Register

    Reset Remarks CLGFOUT 15–8 – 0x00 – – – – 6–4 FOUTDIV[2:0] 3–2 FOUTSRC[1:0] – – FOUTEN Bits 15–7 Reserved Bits 6–4 FOUTDIV[2:0] These bits set the FOUT clock division ratio. Seiko Epson Corporation 2-26 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 49: Clg Oscillation Frequency Trimming Register 1

    This setting affects the high-speed oscillation frequencies (8 MHz to 32 MHz). Table 2.6.15 High-Speed Oscillation Frequency Trimming Setting of IOSC Internal Oscillator Circuit CLGTRIM1.IOSCHSAJ[6:0] bits IOSC oscillation frequency (32/24/16/12/8 MHz) 0x7f High 0x00 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 2-27 (Rev. 1.1)

  • Page 50: Clg Oscillation Frequency Trimming Register 2

    “Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC1 oscillator circuit is inactive. Seiko Epson Corporation 2-28 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 51: Cpu And Debugger

    For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up re- sistors R ” in the “Electrical Characteristics” chapter. R and R are not required when using the debug DBG1–2 DBG1 DBG2 pins as general-purpose I/O port pins. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 52: Reference Documents

    Architecture Reference Manual ® 2. Cortex -M0+Technical Reference Manual ® 3. Cortex -M0+ Devices Generic User Guide ® These documents can be downloaded from the document site of Arm Ltd. https://developer.arm.com/documentation Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 53: Memory And Bus

    0x2000 3fff RAM area (16K bytes) (Device size: 32 bits) 0x2000 0000 0x1fff ffff Reserved 0x0002 0000 0x0001 ffff Flash area (128K bytes) (Device size: 32 bits) 0x0000 0000 Figure 4.1.1 Memory Map Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 54: Bus Access Cycle

    Notes: • When programming the Flash memory, 2.2 V or more V voltage is required. • Be sure to avoid using the V pin output for driving external circuits. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 55: Ram

    T16 Ch.0 Counter Data Register 0x4000 014a T16_0INTF T16 Ch.0 Interrupt Flag Register 0x4000 014c T16_0INTE T16 Ch.0 Interrupt Enable Register Flash controller (FLASHC) 0x4000 01b0 FLASHCWAIT FLASHC Flash Read Cycle Register Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 56 0x4000 02dc PPORTPDMODSEL Pd Port Mode Select Register 0x4000 02de PPORTPDFNCSEL Pd Port Function Select Register 0x4000 02e0 PPORTCLK P Port Clock Control Register 0x4000 02e2 PPORTINTFGRP P Port Interrupt Flag Group Register Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 57 0x4000 03d2 I2C_0INTE I2C Ch.0 Interrupt Enable Register 0x4000 03d4 I2C_0TBEDMAEN I2C Ch.0 Transmit Buffer Empty DMA Request Enable Register 0x4000 03d6 I2C_0RBFDMAEN I2C Ch.0 Receive Buffer Full DMA Request Enable Register Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 58 0x4000 04a6 T16_4TR T16 Ch.4 Reload Data Register 0x4000 04a8 T16_4TC T16 Ch.4 Counter Data Register 0x4000 04aa T16_4INTF T16 Ch.4 Interrupt Flag Register 0x4000 04ac T16_4INTE T16 Ch.4 Interrupt Enable Register Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 59 SNDA Control Register 0x4000 0706 SNDADAT SNDA Data Register 0x4000 0708 SNDAINTF SNDA Interrupt Flag Register 0x4000 070a SNDAINTE SNDA Interrupt Enable Register 0x4000 070c SNDAEMDMAEN SNDA Sound Buffer Empty DMA Request Enable Register Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 60 LCD8D Power Control Register 0x4000 080a LCD8DDSP LCD8D Display Control Register 0x4000 080c LCD8DCOMC0 LCD8D COM Pin Control Register 0 0x4000 0810 LCD8DINTF LCD8D Interrupt Flag Register 0x4000 0812 LCD8DINTE LCD8D Interrupt Enable Register Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 61: System-Protect Function

    Other than 0x0096 (R/W): Enable system protection While the system protection is enabled, any data will not be written to the affected control bits (bits with “WP” or “R/WP” appearing in the R/W column). Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 62: Flashc Flash Read Cycle Register

    Notes: • Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. • When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP instructions immediately after that. Program example: FLASHC->WAIT_b.RDWAIT = 1; asm(“NOP”); asm(“NOP”); CLG->OSC_b.IOSCEN = 0; Seiko Epson Corporation 4-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 63: Interrupt

    • IOSC oscillation stabilization waiting completion • OSC1 oscillation stabilization waiting completion • OSC3 oscillation stabilization waiting completion • OSC1 oscillation stop • IOSC oscillation auto-trimming completion • IOSC oscillation auto-trimming error Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 64 • End of transmission interface Ch.1 interrupt • Receive buffer full • Transmit buffer empty • Overrun error VTOR + 0x94 Sound generator interrupt • Sound buffer empty • Sound output completion Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 65: Vector Table Offset Address (Vtor)

    The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece- dence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 66: Dma Controller (Dmac)

    • Priority level for each channel is selectable from two levels. • DMA transfers are allowed even if the CPU is placed into HALT mode. Figure 6.1.1 shows the configuration of the DMAC. Table 6.1.1 DMAC Channel Configuration of S1C31W65 Item S1C31W65 Number of channels 4 channels (Ch.0 to Ch.3)

  • Page 67: Operations

    256 bytes DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00) DMACCPTR.CPTR[31:0] + 0x080 9 to 16 512 bytes DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x100 17 to 32 1,024 bytes DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x200 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 68: Transfer Source End Pointer

    6.4.2 Transfer Destination End Pointer Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if the transfer destination address is not incremented. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 69 When the DMAC is performing a successive transfer, it suspends the data transfer at the cycle set with R_pow- er. If DMA requests have been issued at that point, the DMAC re-arbitrates them according to their priorities and then performs a DMA transfer for the channel with the highest priority. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 70: Dma Transfer Mode

    DMA transfer 1 DMA transfer 2 DMA transfer 3 DMA transfer 4 DMA transfer 7 DMA transfer 8 operation DMACENDIF.ENDIFn DMA transfer request Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2 = 2) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 71: Ping-Pong Transfer

    5. Set cycle_ctrl to 0x0 after a DMA transfer completion interrupt has occurred by the next to last task. 6. The DMA transfer is completed when a DMA transfer completion interrupt occurs by the last task. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 72: Memory Scatter-Gather Transfer

    Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 73: Peripheral Scatter-Gather Transfer

    Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 74: Dma Transfer Cycle

    The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 75: Control Registers

    – 15–8 – 0x00 – – 7–1 – 0x00 – MSTEN – – Bits 31–1 Reserved Bit 0 MSTEN This bit enables the DMA controller. 1 (W): Enable 0 (W): Disable Seiko Epson Corporation 6-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 76: Dmac Control Data Base Pointer Register

    DMA transfer requests from peripheral circuits have been disabled. 0 (R): DMA transfer requests from peripheral circuits have been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 6-11 (Rev. 1.1)

  • Page 77: Dmac Request Mask Clear Register

    The alternate data structure has been enabled. 0 (R): The primary data structure has been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 78: Dmac Primary-Alternate Clear Register

    ERRIF This bit indicates the DMAC error interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 6-13 (Rev. 1.1)

  • Page 79: Dmac Transfer Completion Interrupt Flag Register

    DMAC Error Interrupt Enable Set Register Register name Bit name Initial Reset Remarks DMACERRIESET 31–24 – 0x00 – – 23–16 – 0x00 – 15–8 – 0x00 – 7–1 – 0x00 – ERRIESET Bits 31–1 Reserved Seiko Epson Corporation 6-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 80: Dmac Error Interrupt Enable Clear Register

    0x00 – ERRIECLR – – Bits 31–1 Reserved Bit 0 ERRIECLR This bit disables DMA error interrupts. 1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.) 0 (W): Ineffective Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 6-15 (Rev. 1.1)

  • Page 81: O Ports (Pport)

    Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 7.1.1 shows the configuration of PPORT. Table 7.1.1 Port Configuration of S1C31W65 Item S1C31W65...

  • Page 82: I/O Cell Structure And Functions

    Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 83: Cmos Output And High Impedance State

    • Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 84 * Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 7.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 85: Port Input/Output Control

    1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)”). 2. Configure the input pin combination for key-entry reset using the PPORTCLK.KRSTCFG[1:0] bits. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 86: Interrupts

    These bits are used to set data to be output from the GPIO port pins. 1 (R/W): Output high level from the port pin 0 (R/W): Output low level from the port pin Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 87: Px Port Enable Register

    PPORTPxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 88: Px Port Interrupt Flag Register

    PPORTPxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 89: Px Port Function Select Register

    Table 7.6.2 Key-Entry Reset Function Settings PPORTCLK.KRSTCFG[1:0] bits key-entry reset Reset when P0[3:0] inputs = all low Reset when P0[2:0] inputs = all low Reset when P0[1:0] inputs = all low Disable Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 90: P Port Interrupt Flag Group Register

    A port generated an interrupt 0 (R): No port generated an interrupt The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 7-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 91: Control Register And Port Function Configuration Of This Ic

    RFC Ch.0 SENA0 UPMUX – – – – RFC Ch.0 REF0 UPMUX – – – – RFC Ch.0 RFIN0 UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 7-11 (Rev. 1.1)

  • Page 92: P1 Port Group

    T16B Ch.0 EXCL00 UPMUX ADC12A ADIN01 – – T16B Ch.1 EXCL10 UPMUX ADC12A ADIN00 – – – – UPMUX ADC12A VREFA0 – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 93: P2 Port Group

    T16 Ch.0 EXCL01 UPMUX – – LCD8D SEG55 T16 Ch.1 EXCL11 UPMUX – – LCD8D SEG54 T16 Ch.2 EXCL21 UPMUX – – LCD8D SEG53 *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 7-13 (Rev. 1.1)

  • Page 94: P3 Port Group

    – UPMUX SVD4 Ch.0 EXSVD00 LCD8D SEG42 – – UPMUX SVD4 Ch.0 EXSVD01 LCD8D SEG41 RFC Ch.0 RFCLKO0 UPMUX – – LCD8D SEG40 *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 95: P4 Port Group

    – – – – – LCD8D SEG35 – – – – – – LCD8D SEG34 – – – – – – LCD8D SEG33 – – – – – – LCD8D SEG32 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 7-15 (Rev. 1.1)

  • Page 96: P5 Port Group

    – – – – – LCD8D SEG20 – – – – – – LCD8D SEG19 – – – – – – LCD8D SEG18 – – – – – – LCD8D SEG17 Seiko Epson Corporation 7-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 97: P6 Port Group

    – – – – – LCD8D COM7/SEG3 – – – – – – LCD8D COM6/SEG2 – – – – – – LCD8D COM5/SEG1 – – – – – – LCD8D COM4/SEG0 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 7-17 (Rev. 1.1)

  • Page 98: Pd Port Group

    – – – – – – – – – – – – – – FLASHC – – – – – – LCD8D – – – – – – LCD8D – – Seiko Epson Corporation 7-18 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 99: Common Registers Between Port Groups

    Register) 7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PPORTINTFGRP 15–8 – 0x00 – – (P Port Interrupt Flag – – Group Register) P6INT P5INT P4INT P3INT P2INT P1INT P0INT Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 7-19 (Rev. 1.1)

  • Page 100: Universal Port Multiplexer (Upmux)

    4. Initialize the peripheral circuit. 5. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PPORTPxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 101: Control Registers

    Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 102: Watchdog Timer (Wdt2)

    CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DEBUG mode. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 103: Operations

    1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 104: Operations In Halt And Sleep Modes

    IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 105: Wdt2 Control Register

    Always 0x0 is read if a value other than 0xa is written. Since an NMI or reset may be generated immediately after running depending on the counter value, WDT2 should also be reset concurrently when running WDT2. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 106: Wdt2 Counter Compare Match Register

    These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 107: Real-Time Clock (Rtca)

    If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 10-1 (Rev. 1.1)

  • Page 108: Clock Settings

    · · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation 10-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 109: Operations

    3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 10-3 (Rev. 1.1)

  • Page 110: Real-Time Clock Counter Operations

    The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 10.4.4.1. Seiko Epson Corporation 10-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 111: Interrupts

    1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 10-5 (Rev. 1.1)

  • Page 112: Control Registers

    This bit executes the 30-second correction time adjustment function. 1 (W): Execute 30-second correction 0 (W): Ineffective 1 (R): 30-second correction is executing. 0 (R): 30-second correction has finished. (Normal operation) Seiko Epson Corporation 10-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 113: Rtca Control Register (High Byte)

    1 as well. However, no correcting operation is performed. RTCA Second Alarm Register Register name Bit name Initial Reset Remarks RTCAALM1 – – – 14–12 RTCSHA[2:0] 11–8 RTCSLA[3:0] 7–0 – 0x00 – Bit 15 Reserved Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 10-7 (Rev. 1.1)

  • Page 114: Rtca Hour/Minute Alarm Register

    BCD code. RTCA Stopwatch Control Register Register name Bit name Initial Reset Remarks RTCASWCTL 15–12 BCD10[3:0] – 11–8 BCD100[3:0] 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation 10-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 115: Rtca Second/1Hz Register

    10-second digit and the 1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 10-9 (Rev. 1.1)

  • Page 116: Rtca Hour/Minute Register

    1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCAHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 10-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 117: Rtca Month/Day Register

    The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 10.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 10-11 (Rev. 1.1)

  • Page 118: Rtca Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: RTCAINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCAINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCAINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCAINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 10-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 119: Rtca Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: RTCAINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCAINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCAINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCAINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 10-13 (Rev. 1.1)
  • Page 120 RTCAINTE.T1DAYIE bit: 1-day interrupt RTCAINTE.T1HURIE bit: 1-hour interrupt RTCAINTE.T1MINIE bit: 1-minute interrupt RTCAINTE.T1SECIE bit: 1-second interrupt RTCAINTE.T1_2SECIE bit: 1/2-second interrupt RTCAINTE.T1_4SECIE bit: 1/4-second interrupt RTCAINTE.T1_8SECIE bit: 1/8-second interrupt RTCAINTE.T1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 10-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 121: Supply Voltage Detector (Svd4)

    - Continuous operation is also possible. Figure 11.1.1 shows the configuration of SVD4. Table 11.1.1 SVD4 Configuration of S1C31W65 Item S1C31W65 Number of channels 1 channel (Ch.0)

  • Page 122: Input Pins And External Connection

    SLEEP mode and SVD4 Ch.n stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD4_n is supplied and the SVD4 Ch.n operation re- sumes. Seiko Epson Corporation 11-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 123: Clock Supply In Debug Mode

    SVD4_nCTL.MODEN bit = 1, wait for at least SVD circuit re- SVD_EXT sponse time before reading the SVD4_nINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 11-3 (Rev. 1.1)

  • Page 124: Svd4 Operations

    An interrupt request is sent to the CPU only when the SVD4_nINTF.SVDIF bit is set while the interrupt is enabled by the SVD4_nINTE.SVDIE bit. For more information on interrupt control, refer to the “Inter- rupt” chapter. Seiko Epson Corporation 11-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 125: Svd Reset

    Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD4 Ch.n operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD4 Ch.n. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 11-5 (Rev. 1.1)

  • Page 126: Svd4 Ch.n Control Register

    0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 11-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 127: Svd4 Ch.n Status And Interrupt Flag Register

    , EXSVDnx) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT 0 (R): Power supply voltage (V , EXSVDnx) ≥ SVD detection voltage V or EXSVD detection voltage V SVD_EXT Bits 7–1 Reserved Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 11-7 (Rev. 1.1)

  • Page 128: Svd4 Ch.n Interrupt Enable Register

    • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 129: 16-Bit Timers (T16)

    • A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 12.1.1 shows the configuration of a T16 channel. Table 12.1.1 T16 Channel Configuration of S1C31W65 Item S1C31W65 Number of channels 8 channels (Ch.0–Ch.7)

  • Page 130: Clock Settings

    (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 12-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 131: Counter Underflow

    At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 12-3 (Rev. 1.1)

  • Page 132: Counter Value Read

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 12-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 133: T16 Ch.n Control Register

    PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 12-5 (Rev. 1.1)

  • Page 134: T16 Ch.n Reload Data Register

    This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 12-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 135: T16 Ch.n Interrupt Enable Register

    This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 12-7 (Rev. 1.1)

  • Page 136: Uart (Uart3)

    • Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. • Provides the carrier modulation output function. Figure 13.1.1 shows the UART3 configuration. Table 13.1.1 UART3 Channel Configuration of S1C31W65 Item S1C31W65 Number of channels 2 channels (Ch.0 and Ch.1)

  • Page 137: Input/Output Pins And External Connections

    (Clock source selection) - UART3_nCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 13-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 138: Clock Supply In Sleep Mode

    (UART3_nMOD.STPB bit = 1). Parity function The parity function is configured using the UART3_nMOD.PREN and UART3_nMOD.PRMD bits. Table 13.4.1 Parity Function Setting UART3_nMOD.PREN bit UART3_nMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 13-3 (Rev. 1.1)

  • Page 139: Operations

    8. Configure the DMA controller and set the following UART3 control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the UART3_nTBEDMAEN and UART3_nRB1FDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 13-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 140: Data Transmission

    Read the UART3_nINTF.TBEIF bit UART3_nINTF.TBEIF = 1 ? Write transmit data to the UART3_nTXD register Transmit data remained? Wait for an interrupt request (UART3_nINTF.TBEIF = 1) Figure 13.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 13-5 (Rev. 1.1)

  • Page 141: Data Reception

    UART3_nINTF.RB1FIF bit to 1 (receive buffer one byte full). If the sec- ond data is received without reading the first data, the UART3_nINTF.RB2FIF bit is set to 1 (receive buffer two bytes full). Seiko Epson Corporation 13-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 142 Set the UART3_nMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 13-7 (Rev. 1.1)

  • Page 143: Carrier Modulation

    CAREN = 0 CAREN = 1 USOUTn PECAR = 0 (INVTX = 1) CAREN = 1 PECAR = 1 Figure 13.5.5.1 Carrier Modulation Waveform (UART3_nMOD.CHLN = 1, UART3_nMOD.STPB = 0, UART3_nMOD.PREN = 1) Seiko Epson Corporation 13-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 144: Receive Errors

    When an overrun error occurs, the UART3_nINTF.OEIF bit (overrun error interrupt flag) is set to 1. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 13-9 (Rev. 1.1)

  • Page 145: Interrupts

    After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 13-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 146: Control Registers

    UART3 Ch.n Mode Register Register name Bit name Initial Reset Remarks UART3_nMOD 15–13 – – – PECAR CAREN BRDIV INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Bits 15–13 Reserved Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 13-11 (Rev. 1.1)
  • Page 147 1 (R/W): Enable parity function 0 (R/W): Disable parity function Bit 1 PRMD This bit selects either odd parity or even parity when using the parity function. 1 (R/W): Odd parity 0 (R/W): Even parity Seiko Epson Corporation 13-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 148: Uart3 Ch.n Baud-Rate Register

    Note: If the UART3_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the UART3_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the UART3_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 13-13 (Rev. 1.1)

  • Page 149: Uart3 Ch.n Transmit Data Register

    This bit indicates the receiving status. (See Figure 13.5.3.1.) 1 (R): During receiving 0 (R): Idle Bit 8 TBSY This bit indicates the sending status. (See Figure 13.5.2.1.) 1 (R): During sending 0 (R): Idle Bit 7 Reserved Seiko Epson Corporation 13-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 150: Uart3 Ch.n Interrupt Enable Register

    UART3_nINTE.PEIE bit: Parity error interrupt UART3_nINTE.OEIE bit: Overrun error interrupt UART3_nINTE.RB2FIE bit: Receive buffer two bytes full interrupt UART3_nINTE.RB1FIE bit: Receive buffer one byte full interrupt UART3_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 13-15 (Rev. 1.1)

  • Page 151: Uart3 Ch.n Transmit Buffer Empty Dma Request Enable Register

    UART3_nCAWF 15–8 – 0x00 – – 7–0 CRPER[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 CRPER[7:0] These bits set the carrier modulation output frequency. For more information, refer to “Carrier Modu- lation.” Seiko Epson Corporation 13-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 152: Synchronous Serial Interface (Spia)

    • Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 14.1.1 shows the SPIA configuration. Table 14.1.1 SPIA Channel Configuration of S1C31W65 Item S1C31W65 Number of channels 2 channels (Ch.0 and Ch.1)

  • Page 153: Input/Output Pins And External Connections

    SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 14.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 14-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 154: Pin Functions In Master Mode And Slave Mode

    16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 14-3 (Rev. 1.1)

  • Page 155: Clock Supply During Debugging

    SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPIA_nTXD register Figure 14.3.3.1 SPI Clock Phase and Polarity (SPIA_nMOD.LSBFST bit = 0, SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 156: Data Format

    6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 14-5 (Rev. 1.1)

  • Page 157: Data Transmission In Master Mode

    Data (W) → SPIA_nTXD Data (W) → SPIA_nTXD Software operations Data (W) → SPIA_nTXD 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.2.1 Example of Data Sending Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 158 Transfer destination SPIA_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 14-7 (Rev. 1.1)

  • Page 159: Data Reception In Master Mode

    Software operations SPIA_nRXD → Data (R) Data (W) → SPIA_nTXD SPIA_nRXD → Data (R) 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 160 Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 14-9 (Rev. 1.1)

  • Page 161: Terminating Data Transfer In Master Mode

    • Data transmission/reception can be performed even in SLEEP mode, it makes it possible to wake the CPU up using an SPIA interrupt. Seiko Epson Corporation 14-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 162: Terminating Data Transfer In Slave Mode

    1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 14-11 (Rev. 1.1)

  • Page 163: Interrupts

    SPIA_nINTF.BSY SPIA_nMOD register CPOL bit CPHA bit SPICLKn SDOn SPICLKn SDOn SPIA_nINTF.TENDIF Writing data to the SPIA_nTXD register Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 164: Dma Transfer Requests

    16 bits 15 bits 14 bits 13 bits 12 bits 11 bits 10 bits 9 bits 8 bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits Setting prohibited Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 14-13 (Rev. 1.1)

  • Page 165: Spia Ch.n Control Register

    Note: If the SPIA_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the SPIA_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the SPIA_nCTL.SFTRST bit as well. Seiko Epson Corporation 14-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 166: Spia Ch.n Transmit Data Register

    These bits indicate the SPIA interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag (OEIF, TENDIF) 0 (W): Ineffective Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 14-15 (Rev. 1.1)

  • Page 167: Spia Ch.n Interrupt Enable Register

    Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 14-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 168: C (I2C)

    • The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns. Figure 15.1.1 shows the I2C configuration. Table 15.1.1 I2C Channel Configuration of S1C31W65 Item S1C31W65 Number of channels 2 channels (Ch.0 and Ch.1)

  • Page 169: Input/Output Pins And External Connections

    • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 15-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 170: Clock Settings

    15.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-3 (Rev. 1.1)

  • Page 171: Operations

    - Set the I2C_nCTL.MST bit to 0. (Set slave mode) - Set the I2C_nCTL.SFTRST bit to 1. (Execute software reset) - Set the I2C_nCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 15-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 172: Data Transmission In Master Mode

    I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condi- tion. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and I2C_nINTF. TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-5 (Rev. 1.1)
  • Page 173 Last data sent? Retry? Write 1 to the I2C_nCTL.TXSTOP bit Write data to the I2C_nTXD register Wait for an interrupt request (I2C_nINTF.STOPIF = 1) Figure 15.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 15-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 174: Data Reception In Master Mode

    10. (When DMA is not used) Repeat Steps 6 to 8 until the end of data reception. 11. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1). Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-7 (Rev. 1.1)
  • Page 175 S: START condition, Sr: Repeated START condition, P: STOP condition, A: ACK, A: NACK, Saddr/R: Slave address + R(1), Data n: 8-bit data Figure 15.4.3.1 Example of Data Receiving Operations in Master Mode Seiko Epson Corporation 15-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 176 Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 (+1) dst_size 0x0 (byte) src_inc 0x3 (no increment) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of receive data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-9 (Rev. 1.1)

  • Page 177: 10-Bit Addressing In Master Mode

    Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data transfer di- rection to the I2C_nTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 15-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 178: Data Transmission In Slave Mode

    Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2C_nINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-11 (Rev. 1.1)
  • Page 179 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 15.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 15-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 180: Data Reception In Slave Mode

    I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2C_nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1. After that, the received data can be read out from the I2C_nRXD register. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-13 (Rev. 1.1)
  • Page 181 Wait for an interrupt request (I2C_nINTF.RBFIF = 1) Last data received next? Write 1 to the I2C_nCTL.TXNACK bit Read receive data from the I2C_nRXD register Last data received? Figure 15.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 15-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 182: Slave Operations In 10-Bit Address Mode

    If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-15 (Rev. 1.1)

  • Page 183: Error Detection

    4 <Master mode only> When 1 is written to the I2C_nCTL. I2C_nINTF.ERRIF = 1 TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to “Au- Automatic bus clearing I2C_nCTL.TXSTART = 0 tomatic Bus Clearing Operation.”) failure I2C_nINTF.STARTIF = 1 Seiko Epson Corporation 15-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 184: Interrupts

    Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2C_nOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-17 (Rev. 1.1)

  • Page 185: Dma Transfer Requests

    15.7 Control Registers I2C Ch.n Clock Control Register Register name Bit name Initial Reset Remarks I2C_nCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 15-18 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 186: I2C Ch.n Mode Register

    Note: The I2C_nMOD register settings can be altered only when the I2C_nCTL.MODEN bit = 0. I2C Ch.n Baud-Rate Register Register name Bit name Initial Reset Remarks I2C_nBR 15–8 – 0x00 – – – – 6–0 BRT[6:0] 0x7f Bits 15–7 Reserved Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-19 (Rev. 1.1)

  • Page 187: I2C Ch.n Own Address Register

    STOP condition has been generated. This bit is automatically cleared when the bus free time (t defined in the I C Specifications) has elapsed after the STOP condition has been generated. Seiko Epson Corporation 15-20 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 188: I2C Ch.n Transmit Data Register

    Register name Bit name Initial Reset Remarks I2C_nRXD 15–8 – 0x00 – – 7–0 RXD[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-21 (Rev. 1.1)

  • Page 189: I2C Ch.n Status And Interrupt Flag Register

    Bit 0 TBEIF These bits indicate the I2C interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 15-22 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 190: I2C Ch.n Interrupt Enable Register

    I2C_nINTE.NACKIE bit: NACK reception interrupt I2C_nINTE.STOPIE bit: STOP condition interrupt I2C_nINTE.STARTIE bit: START condition interrupt I2C_nINTE.ERRIE bit: Error detection interrupt I2C_nINTE.RBFIE bit: Receive buffer full interrupt I2C_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 15-23 (Rev. 1.1)

  • Page 191: I2C Ch.n Transmit Buffer Empty Dma Request Enable Register

    (Ch.0–Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 15-24 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 192: 16-Bit Pwm Timers (T16B)

    - The capture circuit captures counter values using external/software trigger signals and generates interrupts or DMA requests. (Can be used to measure external event periods/cycles.) Figure 16.1.1 shows the T16B configuration. Table 16.1.1 T16B Channel Configuration of S1C31W65 Item S1C31W65 Number of channels 3 channels (Ch.0–Ch.2)

  • Page 193: Input/Output Pins

    If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 16-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 194: Clock Settings

    Figure 16.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-3 (Rev. 1.1)

  • Page 195: Operations

    5. Set the following bits when using the interrupt: - Write 1 to the interrupt flags in the T16B_nINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the T16B_nINTE register to 1. (Enable interrupts) Seiko Epson Corporation 16-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 196: Counter Block Operations

    T16Bn, one of the operations shown below is required to read correctly by the CPU. - Read the counter value twice or more and check to see if the same value is read. - Stop the timer and then read the counter value. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-5 (Rev. 1.1)
  • Page 197 0x0000 and continues counting down from the new MAX value after a counter under- flow occurs. In one-shot down count mode, the counter returns to the MAX value if a counter underflow occurs and stops automatically at that point. Seiko Epson Corporation 16-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 198 0x0000 and then starts counting up to the new MAX value. In one-shot up/down count mode, the counter stops automatically when it reaches 0x0000 during count down operation. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-7 (Rev. 1.1)

  • Page 199: Comparator/Capture Block Operations

    When the counter reaches the MAX value in comparator mode, the T16B_nINTF.CNTMAXIF bit (counter MAX interrupt flag) is set to 1. When the counter reaches 0x0000, the T16B_nINTF.CNTZEROIF bit (counter zero interrupt flag) is set to 1. Seiko Epson Corporation 16-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 200 Count cycle = — — — — — — — — [s] (Eq. 16.2) CLK_T16B CLK_T16B Where T16B_nCCRm register setting value (0 to 65,535) MAX: T16B_nMC register setting value (0 to 65,535) : Count clock frequency [Hz] CLK_T16B Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-9 (Rev. 1.1)
  • Page 201 (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 16-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 202 Count cycle MAX value (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-11 (Rev. 1.1)
  • Page 203 Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 16-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 204 Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-13 (Rev. 1.1)
  • Page 205 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 (Note that the T16B_nINTF.CMPCAPmIF/CNTMAXIF/CNTZEROIF bit clearing operations via software are omitted from the figure.) Figure 16.4.3.2 Compare Buffer Operations Seiko Epson Corporation 16-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 206 If the captured data stored in the T16B_nCCRm register is overwritten by the next trigger when the T16B_ nINTF.CMPCAPmIF bit is still set, an overwrite error occurs (the T16B_nINTF.CAPOWmIF bit is set). Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-15 (Rev. 1.1)
  • Page 207 Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16B_nTC.TC[15:0] Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation Figure 16.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation 16-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 208: Tout Output Control

    Furthermore, when the T16B_nCCCTLm.TOUTMT bit is set to 1, the TOUT circuit uses the MATCH signal output from another system in the circuit pair (0 and 1, 2 and 3, 4 and 5). This makes it possible to change the signal twice within a counter cycle. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-17 (Rev. 1.1)
  • Page 209 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 16-18 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 210 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 16.4.4.2 TOUT Output Waveform (T16B_nCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-19 (Rev. 1.1)
  • Page 211 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 16-20 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 212 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-21 (Rev. 1.1)
  • Page 213 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 16.4.4.3 TOUT Output Waveform (T16B_nCCCTL0.TOUTMT bit = 1, T16B_nCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation 16-22 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 214: Interrupt

    Bit 8 DBRUN This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-23 (Rev. 1.1)

  • Page 215: T16B Ch.n Counter Control Register

    T16B_nCTL.ONEST bit setting (see Table 16.7.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16B_nCTL.CNTMD[1:0] bit settings (see Table 16.7.2). Seiko Epson Corporation 16-24 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 216: T16B Ch.n Max Counter Data Register

    T16B_nCTL.MODEN bit to 1 until the T16B_nCS.BSY bit is set to 0 from 1. • Do not set the T16B_nMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16B_nTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-25 (Rev. 1.1)

  • Page 217: T16B Ch.n Counter Status Register

    This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 16-26 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 218: T16B Ch.n Interrupt Flag Register

    Note: The configuration of the T16B_nINTF.CAPOWmIF and T16B_nINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-27 (Rev. 1.1)

  • Page 219: T16B Ch.n Interrupt Enable Register

    The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 16-28 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 220: T16B Ch.n Comparator/Capture M Control Register

    These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16B_nCCRm register in capture mode (see Table 16.7.4). The T16B_nCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-29 (Rev. 1.1)
  • Page 221 T h e s i g n a l b e c o m e s i n a c t i v e b y t h e M AT C H m o r MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 16-30 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 222: T16B Ch.n Compare/Capture M Data Register

    In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 16-31 (Rev. 1.1)

  • Page 223: T16B Ch.n Counter Max/Zero Dma Request Enable Register

    (Ch.0–Ch.15) when the counter value reaches the compare data or is captured. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 16-32 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 224: Sound Generator (Snda)

    Sound register MOSEL[1:0] Sound generation STIM[3:0] circuit BZOUT SINV Output control circuit SSTP #BZOUT Interrupt control circuit EMIE EMIF EDIE EDIF DMA request controller control circuit EMDMAENx Figure 17.1.1 SNDA Configuration Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 17-1 (Rev. 1.1)

  • Page 225: Output Pins And External Connections

    Piezoelectric buzzer #BZOUT S1C31 SNDA Figure 17.2.2.1 Connection between SNDA and Piezoelectric Buzzer (Direct Drive) Piezoelectric buzzer BZOUT S1C31 SNDA Figure 17.2.2.2 Connection between SNDA and Piezoelectric Buzzer (Single Pin Drive) Seiko Epson Corporation 17-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 226: Clock Settings

    Normal buzzer mode generates a buzzer signal with the software specified frequency and duty ratio, and outputs the generated signal to outside the IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 17-3 (Rev. 1.1)
  • Page 227 Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDADAT.SFRQ[7:0] bits ≤ SNDADAT.SLEN[5:0] bits • Settings as SNDADAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 17-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 228 – 71.9 35.9 0x15 – – – – 68.8 34.4 0x14 – – – – 65.6 32.8 0x13 – – – – 62.5 31.3 0x12 – – – – 59.4 29.7 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 17-5 (Rev. 1.1)

  • Page 229: Buzzer Output In One-Shot Buzzer Mode

    At the same time, the SNDAINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDAINTF.SBSY bit is cleared to 0. Figure 17.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 17-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 230: Output In Melody Mode

    At the same time, the SNDAINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDAINTF.SBSY bit is cleared to 0. Figure 17.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 17-7 (Rev. 1.1)
  • Page 231 Dotted quarter rest 0x07 Quarter note Quarter rest 0x05 Dotted eighth note Dotted eighth rest 0x03 Eighth note Eighth rest 0x01 Sixteenth note Sixteenth rest 0x00 Thirty-second note Thirty-second rest Other Setting prohibited Seiko Epson Corporation 17-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 232: Interrupts

    1 is register written to the SNDACTL.SSTP bit Sound output SNDAINTF.EDIF When a sound output has completed Writing 1 or writing to completion the SNDADAT register Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 17-9 (Rev. 1.1)

  • Page 233: Dma Transfer Requests

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SNDA operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SNDA. Seiko Epson Corporation 17-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 234: Snda Select Register

    This bit selects an output pin drive mode. 1 (R/W): Normal drive mode 0 (R/W): Direct drive mode For more information, refer to “Output Pin Drive Mode.” Bits 1–0 MOSEL[1:0] These bits select a sound output mode. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 17-11 (Rev. 1.1)

  • Page 235: Snda Control Register

    0 (R/W): Note When a rest is selected, the BZOUT pin goes low and the #BZOUT pin goes high during the output duration. This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation 17-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 236: Snda Interrupt Flag Register

    0x00 – – 7–2 – 0x00 – EMIE EDIE Bits 15–2 Reserved Bit 1 EMIE Bit 0 EDIE These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 17-13 (Rev. 1.1)

  • Page 237: Snda Sound Buffer Empty Dma Request Enable Register

    (Ch.0–Ch.15) when a sound buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 17-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 238: Ir Remote Controller (Remc3)

    • Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 18.1.1 shows the REMC3 configuration. Table 18.1.1 REMC3 Channel Configuration of S1C31W65 Item S1C31W65 Number of channels...

  • Page 239: External Connections

    1. Write 1 to the REMC3DBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMC3CLK.CLKSRC[1:0] and REMC3CLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 18-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 240: Data Transmission Procedures

    The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 18.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 18-3 (Rev. 1.1)
  • Page 241 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REMC3DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMC3A- PLEN.APLEN[15:0] and REMC3DBLEN.DBLEN[15:0] bits. Figure 18.4.3.3 shows an example of the data signal generated. Seiko Epson Corporation 18-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 242: Continuous Data Transmission And Compare Buffers

    (REMC3DBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMC3DBLEN.DBLEN[15:0] bit-setting value. 18.4.4 Continuous Data Transmission and Compare Buffers Figure 18.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 18-5 (Rev. 1.1)

  • Page 243: Interrupts

    The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 18-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 244: Application Example: Driving El Lamp

    This bit sets whether the REMC3 operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 18-7 (Rev. 1.1)

  • Page 245: Remc3 Data Bit Counter Control Register

    This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 18-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 246: Remc3 Data Bit Counter Register

    0x0000 H0/S0 Cleared by writing 1 to the REMC3DBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 18-9 (Rev. 1.1)

  • Page 247: Remc3 Data Bit Active Pulse Length Register

    Transfer to the REMC3APLEN buffer has not completed. 0 (R): Transfer to the REMC3APLEN buffer has completed. While this bit is set to 1, writing to the REMC3APLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 18-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 248: Remc3 Interrupt Enable Register

    REMC3CARR.CRPER[7:0] bit-setting value. (See Figure 18.4.3.2.) REMC3 Carrier Modulation Control Register Register name Bit name Initial Reset Remarks REMC3CCTL 15–9 – 0x00 – – OUTINVEN 7–1 – 0x00 – CARREN Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 18-11 (Rev. 1.1)
  • Page 249 This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMC3DBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 18-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 250: 12-Bit A/D Converter (Adc12A)

    • Can convert multiple analog input signals sequentially. • Can generate conversion completion and overwrite error interrupts. • Can issue a DMA transfer request when a conversion has completed. Figure 19.1.1 shows the ADC12A configuration. Table 19.1.1 ADC12A Configuration of S1C31W65 Item S1C31W65 Number of channels 1 channel (Ch.0)

  • Page 251: Input Pins And External Connections

    : acquisition time). Figure 19.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 19.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 19-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 252: Operations

    Writing 1 to the ADC12A_nCTL.ADST bit enables the ADC12A to accept trigger inputs. After that, A/D con- version is started when an underflow occurs in the 16-bit timer Ch.k. Software trigger Writing 1 to the ADC12A_nCTL.ADST bit starts A/D conversion. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 19-3 (Rev. 1.1)

  • Page 253: Conversion Mode And Analog Input Pin Settings

    3. Read the A/D conversion result of the analog input m (ADC12A_nADD.ADD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12A_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 19-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 254 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 19-5 (Rev. 1.1)

  • Page 255: Interrupts

    After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 19-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 256: Control Registers

    Note: The data written to the ADC12A_nCTL.ADST bit must be retained for one or more CLK_T16_ k clock cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 19-7 (Rev. 1.1)

  • Page 257: Adc12A Ch.n Trigger/Analog Input Select Register

    Right justified (ADC12A_nTRG.STMD bit = 0) 0 (MSB) 12-bit conversion result (LSB) Figure 19.7.1 Conversion Data Alignment Bit 6 CNVMD This bit sets the A/D conversion mode. 1 (R/W): Continuous conversion mode 0 (R/W): One-time conversion mode Seiko Epson Corporation 19-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 258: Adc12A Ch.n Configuration Register

    A/D conversion. • Be aware that ADC circuit current I flows if the ADC12_nCFG.VRANGE[1:0] bits are set to a value other than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 19-9 (Rev. 1.1)

  • Page 259: Adc12A Ch.n Interrupt Flag Register

    0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: ADC12A_nINTE.OVIE bit: A/D conversion result overwrite error interrupt ADC12A_nINTE.ADmCIE bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation 19-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 260: Adc12A Ch.n Dma Request Enable Register M

    ADC12A Ch.n Result Register Register name Bit name Initial Reset Remarks ADC12A_nADD 15–0 ADD[15:0] 0x0000 – Bits 15–0 ADD[15:0] The A/D conversion results are set to these bits. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 19-11 (Rev. 1.1)

  • Page 261: Temperature Sensor/Reference Voltage Generator (Tsrvr)

    A/D converter. • Can supply the reference voltage generated in this circuit to external devices if this IC has the VREFA exclusive pin. Figure 20.1.1 shows the TSRVR configuration. Table 20.1.1 TSRVR Configuration of S1C31W65 Item S1C31W65 Number of channels 1 channel (Ch.0)

  • Page 262: External Connections

    ADD: A/D conversion result at temperature T or T (decimal) : A/D converter reference voltage [V] REFA For details of the internal A/D converter, refer to the “12-bit A/D Converter” chapter. Seiko Epson Corporation 20-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 263: Control Registers

    TSRVR_nVCTL.VREFAMD[1:0] VREFA bits are set to 0x2 or 0x3. • When the TSRVR_nVCTL.VREFAMD[1:0] bits are not set to 0x0, do not apply an external voltage to the VREFAm pin. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 20-3 (Rev. 1.1)

  • Page 264: Lcd Driver (Lcd8D)

    • Includes a power supply for 1/2 or 1/3 bias driving (allows external voltages to be applied). • Provides the frame signal monitoring output pin. • Can generate interrupts every frame. Figure 21.1.1 shows the LCD8D configuration. Table 21.1.1 LCD8D Configuration of S1C31W65 Item S1C31W65 Number of segments supported Max.

  • Page 265: Output Pins And External Connections

    Note: When the panel is connected, the LCD8DCTL.LCDDIS bit must be set to 1 to bias the panel even if display is turned off. COMm LCD Panel COM0 SEGn SEG0 S7C17 LCD8D Figure 21.2.2.1 Connections between LCD8D and an LCD Panel Seiko Epson Corporation 21-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 266: Clock Settings

    : LCD8D operating clock frequency [Hz] CLK_LCD8D FRMCNT: LCD8DTIM1.FRMCNT[3:0] setting value (0 to 15) LDUTY: LCD8DTIM1.LDUTY[2:0] setting value (0 to 7) Table 21.3.4.1 lists frame frequency settings when f = 32,768 Hz as an example. CLK_LCD8D Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-3 (Rev. 1.1)

  • Page 267: Lcd Power Supply

    LCD8DPWR.BSTEN bits to 0 to turn both the LCD voltage regulator and LCD voltage booster off. The LCD8DPWR.RESISEL[1:0] bits should be set to 0x0 to disable the internal LCD voltage dividing resistors. Figure 21.4.2.1 shows an external connection example for external voltage application mode 1. Seiko Epson Corporation 21-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 268 1. Turn the external power supply off. 2. Set the LCD8DPWR.EXVCSEL bit to 0. (Select internal generation mode) 3. Set the LCD8DPWR.EXVCSEL bit to 1. (Select external voltage application mode) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-5 (Rev. 1.1)

  • Page 269: Lcd Power Supply Circuit Settings

    (Set LCD contrast initial value) - LCD8DPWR.BSTEN bit (Enable LCD voltage booster) - LCD8DPWR.BIASSEL bit (Select drive bias) - LCD8DPWR.VCSEL bit (Set reference voltage for boosting) - LCD8DPWR.VCEN bit (Enable LCD voltage regulator) Seiko Epson Corporation 21-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 270: Display On/Off

    Valid COM pins Valid SEG pins display dots/segments LDUTY[2:0] bits COM0–COM7 SEG4–SEG55 COM0–COM6 COM0–COM5 COM0–COM4 COM0–COM3 SEG0–SEG55 COM0–COM2 COM0–COM1 Static COM0 Unused common pins output an OFF waveform that turns the segments off. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-7 (Rev. 1.1)

  • Page 271: Drive Waveforms

    21.5.5 Drive Waveforms LCD8D supports two types (Waveform A, Waveform B) of drive waveform outputs. The waveform type can be selected using the LCD8DTIM2.LCDWAVE bit. The following shows drive waveform examples. Seiko Epson Corporation 21-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 272 LFRO display status COM0 COM0 COM1 COM2 COM3 COM1 COM4 COM5 COM6 COM7 COM2 SEGx COM3 COM4 COM5 COM6 COM7 SEGx Figure 21.5.5.1 1/8 Duty Drive Waveform (Waveform A, 1/3 bias) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-9 (Rev. 1.1)
  • Page 273 COM2 COM3 SEGx Figure 21.5.5.2 1/4 Duty Drive Waveform (Waveform A, 1/3 bias) 1 frame LFRO display status COM0 COM0 SEGx SEGx Figure 21.5.5.3 Static Drive Waveform (Waveform A, 1/3 bias) Seiko Epson Corporation 21-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 274 (= V COM6 (= V COM7 (= V (= V (= V (= V SEGx (= V (= V (= V Figure 21.5.5.4 1/8 Duty Drive Waveform (Waveform A, 1/2 bias) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-11 (Rev. 1.1)
  • Page 275 Figure 21.5.5.5 1/4 Duty Drive Waveform (Waveform A, 1/2 bias) 1 frame LFRO display status COM0 COM0 (= V SEGx (= V SEGx (= V Figure 21.5.5.6 Static Drive Waveform (Waveform A, 1/2 bias) Seiko Epson Corporation 21-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 276 LFRO display status COM0 COM0 COM1 COM2 COM3 COM1 COM4 COM5 COM6 COM7 COM2 SEGx COM3 COM4 COM5 COM6 COM7 SEGx Figure 21.5.5.7 1/8 Duty Drive Waveform (Waveform B, 1/3 bias) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-13 (Rev. 1.1)
  • Page 277 COM2 COM3 SEGx Figure 21.5.5.8 1/4 Duty Drive Waveform (Waveform B, 1/3 bias) 1 frame LFRO display status COM0 COM0 SEGx SEGx Figure 21.5.5.9 Static Drive Waveform (Waveform B, 1/3 bias) Seiko Epson Corporation 21-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 278 (= V COM6 (= V COM7 (= V (= V (= V (= V SEGx (= V (= V (= V Figure 21.5.5.10 1/8 Duty Drive Waveform (Waveform B, 1/2 bias) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-15 (Rev. 1.1)
  • Page 279 Figure 21.5.5.11 1/4 Duty Drive Waveform (Waveform B, 1/2 bias) 1 frame LFRO display status COM0 COM0 (= V SEGx (= V SEGx (= V Figure 21.5.5.12 Static Drive Waveform (Waveform B, 1/2 bias) Seiko Epson Corporation 21-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 280: Partial Common Output Drive

    In the display data RAM, two screen areas can be allocated and the LCD8DDSP.DSPAR bit can be used to switch between the screens. Setting the LCD8DDSP.DSPAR bit to 0 selects display area 0; setting to 1 selects display area 1. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-17 (Rev. 1.1)

  • Page 281: Common Pin Assignment

    COM1 COM5 COM0 Unused area (general-purpose RAM) LCD8DDSP. · · · SEGREV bit = 1 LCD8DDSP. · · · SEGREV bit = 0 Figure 21.6.3.2 Display Data RAM Map (1/6 duty) Seiko Epson Corporation 21-18 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 282 SEGREV bit = 1 LCD8DDSP. · · · SEGREV bit = 0 Figure 21.6.3.4 Display Data RAM Map (static drive) Note: No physical memory is allocated to D8 through D31 of each address. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-19 (Rev. 1.1)

  • Page 283: Interrupt

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the LCD8D operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the LCD8D. Seiko Epson Corporation 21-20 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 284: Lcd8D Control Register

    7–6 – – (reserved) 4–3 – – 2–0 LDUTY[2:0] Bits 15–12 Reserved Bits 11–8 FRMCNT[3:0] These bits set the frame frequency. For more information, refer to “Frame Frequency.” Bits 7–3 Reserved Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-21 (Rev. 1.1)

  • Page 285: Lcd8D Power Control Register

    Note: Be sure to avoid applying voltages to the V pins when the LCD8DPWR.EXVCSEL bit to V is set to 0, as the LCD power supply pins are short-circuited to GND. Seiko Epson Corporation 21-22 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 286 VCEN This bit turns the LCD voltage regulator on and off. 1 (R/W): LCD voltage regulator on 0 (R/W): LCD voltage regulator off For more information, refer to “LCD Power Supply.” Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-23 (Rev. 1.1)

  • Page 287: Lcd8D Display Control Register

    “Display On/Off.” LCD8D COM Pin Control Register 0 Register name Bit name Initial Reset Remarks LCD8DCOMC0 15–8 – 0x00 – – COM7DEN COM6DEN COM5DEN COM4DEN COM3DEN COM2DEN COM1DEN COM0DEN Bits 15–8 Reserved Seiko Epson Corporation 21-24 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 288: Lcd8D Interrupt Flag Register

    LCD8DINTE 15–8 – 0x00 – – 7–1 – 0x00 – FRMIE Bits 15–1 Reserved Bit 0 FRMIE This bit enables the frame interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 21-25 (Rev. 1.1)

  • Page 289: F Converter (Rfc)

    • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 22.1.1 shows the RFC configuration. Table 22.1.1 RFC Channel Configuration of S1C31W65 Item S1C31W65 Number of channels 1 channel (Ch.0)

  • Page 290: Input/Output Pins And External Connections

    Figure 22.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C31 RFC : Reference capacitor Figure 22.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 22-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 291: Clock Settings

    (Clear interrupt flags) - Set the interrupt enable bits in the RFC_nINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 22-3 (Rev. 1.1)

  • Page 292: Operating Modes

    To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 22-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 293: Converting Operations And Control Procedure

    The measurement counter overflow sets the RFC_nINTF.EREFIF bit to 1 indicating that the reference os- cillation has been terminated normally. If the RFC_nINTE.EREFIE bit = 1, a reference oscillation comple- tion interrupt request occurs at this point. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 22-5 (Rev. 1.1)
  • Page 294 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 22.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 22-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 295: Cr Oscillation Frequency Monitoring Function

    The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more infor- mation on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 22-7 (Rev. 1.1)

  • Page 296: Control Registers

    This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 22-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 297: Rfc Ch.n Oscillation Trigger Register

    This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 22-9 (Rev. 1.1)

  • Page 298: Rfc Ch.n Measurement Counter Low And High Registers

    Note: The time base counter must be set from the low-order value (RFC_nTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFC_nTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 22-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 299: Rfc Ch.n Interrupt Flag Register

    RFC_nINTE.OVTCIE bit: Time base counter overflow error interrupt RFC_nINTE.OVMCIE bit: Measurement counter overflow error interrupt RFC_nINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFC_nINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFC_nINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 22-11 (Rev. 1.1)

  • Page 300: Electrical Characteristics

    *5 R are not required when using the debug pins as general-purpose I/O ports. DBG1–2 *6 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-1 (Rev. 1.1)

  • Page 301: Current Consumption

    *1 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 0, CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1. OSDEN bit = 0, C = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), = 7 pF) *2 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 1...
  • Page 302 IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = 20 MHz (ceramic PWGACTL.REGSEL bit = 0 (mode1), Typ. value oscillator), CLGOSC3.OSC3INV[1:0] bits = 0x2, Typ. value 4,500 4,000 3,500 3,000 2,500 2,000 1,500 1,000 Ta [°C] Ta [°C] Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-3 (Rev. 1.1)

  • Page 303: System Reset Controller (Src) Characteristics

    = 0 V, Ta = -40 to 105°C Item Symbol Condition Min. Typ. Max. Unit Reset hold time ｍs RSTR *1 Time until the internal reset signal is negated after the reset request is canceled. Seiko Epson Corporation 23-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 304: Clock Generator (Clg) Characteristics

    CLGIOSC.IOSCFQ[2:0] bits = 0x0, PWGACTL.REGSEL bit = 0 -40 to 105°C 0.84 1.16 IOSC oscillation frequency-temperature characteristic = 2.0 to 5.5 V, PWGACTL.REGSEL bit = 1, Typ. value CLGIOSC.IOSCFQ[2:0] bits = 0x7 Ta [°C] Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-5 (Rev. 1.1)
  • Page 305 CLGOSC1.OSC1SELCR bit = 1, 27.84 36.16 Ta = -40 to 105°C *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) OSC1 internal oscillation frequency-temperature characteristic = 1.8 to 5.5 V, Typ. value Ta [°C]...

  • Page 306: Flash Memory Characteristics

    *2 Assumed that Erasing + Programming as count of 1. The count includes programming in the factory for shipment with ROM data programmed. *3 The value is added to the current consumption in the current operating mode. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-7 (Rev. 1.1)

  • Page 307: Input/Output Port (Pport) Characteristics

    Ta = 105°C, Min. value –V = 5.5 V = 3.6 V = 1.8 V = 1.8 V = 3.6 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 = 5.5 V Seiko Epson Corporation 23-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 308: Supply Voltage Detector (Svd4) Characteristics

    SVD4_0CTL.SVDC[4:0] bits = 0x1b 1,101 1,211 SVD4_0CTL.SVDC[4:0] bits = 0x1c 1,012 1,125 1,237 SVD4_0CTL.SVDC[4:0] bits = 0x1d 1,034 1,149 1,264 1,173 SVD4_0CTL.SVDC[4:0] bits = 0x1e 1,055 1,290 SVD4_0CTL.SVDC[4:0] bits = 0x1f 1,077 1,197 1,316 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-9 (Rev. 1.1)
  • Page 309 SVD4_0CTL.SVDC[4:0] bits = 0x1d 4.61 4.99 SVD4_0CTL.SVDC[4:0] bits = 0x1e 4.70 5.10 SVD4_0CTL.SVDC[4:0] bits = 0x1f 4.80 5.20 – – µs SVD circuit enable response time SVDEN SVD circuit response time – – µs Seiko Epson Corporation 23-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 310: Uart (Uart3) Characteristics

    = 1.8 to 5.5 V, V = 0 V, Ta = -40 to 105°C Item Symbol Condition Min. Typ. Max. Unit Transfer baud rate Normal mode – 460,800 BRT1 IrDA mode – 115,200 BRT2 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-11 (Rev. 1.1)
  • Page 311 SDI1 hold time – mode0 – – – mode1 – – SDO1 output delay time = 15 pF – mode0 – – – mode1 – – *1 C = Pin load Seiko Epson Corporation 23-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 312 (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-13 (Rev. 1.1)

  • Page 313: I 2 C (I2C) Characteristics

    3.97 4.14 4.31 LCD8DPWR.LC[4:0] bits = 0x10 4.12 4.29 4.47 LCD8DPWR.LC[4:0] bits = 0x11 4.27 4.45 4.63 LCD8DPWR.LC[4:0] bits = 0x12 4.42 4.61 4.80 LCD8DPWR.LC[4:0] bits = 0x13 4.57 4.76 4.96 Seiko Epson Corporation 23-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 314 2.54 2.65 2.77 LCD8DPWR.LC[4:0] bits = 0x0f 2.64 2.76 2.87 LCD8DPWR.LC[4:0] bits = 0x10 2.74 2.86 2.98 LCD8DPWR.LC[4:0] bits = 0x11 2.84 2.97 3.09 LCD8DPWR.LC[4:0] bits = 0x12 2.94 3.07 3.20 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-15 (Rev. 1.1)
  • Page 315 LCD8DPWR.VCSEL bit = 0, LCD8DTIM2.LCDWAVE bit = 0 *1 *2 LCD8DDSP.DSPC[1:0] bits = 0x2 (all on), – µA LCD8DPWR.BIASSEL bit = 1, LCD8DPWR.VCSEL bit = 0, LCD8DTIM2.LCDWAVE bit = 0 *1 *2 Seiko Epson Corporation 23-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 316 LCDH4 in heavy load protection mode LCD8DPWR.BIASSEL bit = 0, (1/2 bias, V reference voltage, LCD8DPWR.VCSEL bit = 1, Waveform A) LCD8DTIM2.LCDWAVE bit = 1, LCD8DPWR.HVLD bit = 1 *1 *2 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-17 (Rev. 1.1)
  • Page 317 LCD8DPWR.LC[4:0] bits = 0x1f LCD8DPWR.LC[4:0] bits = 0x1f 0x0f 0x0f 0x00 0x00 LCD drive voltage-temperature characteristic (V reference voltage) Typ. value 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 0.94 Ta [°C] Seiko Epson Corporation 23-18 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 318 µA = 1,000 pF, Ta = 25°C 3.6 V – µA *1 In this characteristic, unevenness between production lots, and variations in measurement board, resistances and capacitances are taken into account. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-19 (Rev. 1.1)
  • Page 319 = 1,000 pF, Ta = 25°C, Typ. value 3,000 2,500 5.5 V 3.6 V 1.8 V 2,000 = 5.5 V 1,500 1,000 3.6 V 1.8 V 1,000 Ta [°C] [kHz] RFCLK Seiko Epson Corporation 23-20 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 320: 12-Bit A/D Converter (Adc12A) Characteristics

    *3 The error will be increased according to the potential difference between V and VREFAn. A/D converter current consumption-power supply voltage characteristic , ADIN = V /2, f = 100 ksps, Ta = 25°C, Typ. value REFA REFA ADC12A_nCFG.VRANGE[1:0] bits = REFA Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 23-21 (Rev. 1.1)

  • Page 321: Temperature Sensor/Reference Voltage Generator (Tsrvr) Characteristics

    – – µs TEMP 0x1–0x3 TSRVR_nVCTL.VREFAMD[1:0] Invalid Valid VREFAn VREFA TSRVR_nTCTL.TEMPEN Invalid Valid Temperature sensor output TEMP Temperature sensor output voltage-temperature characteristic = 2.2 to 5.5 V, Typ. value Ta [°C] Seiko Epson Corporation 23-22 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 322: Basic External Connection Diagram

    *3: When 1/2 bias is selected *3: When 1/3 bias is selected *4: When OSC1 crystal oscillator is selected *5: When OSC3 crystal/ceramic oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 24-1 (Rev. 1.1)
  • Page 323 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...

  • Page 324: Package

    25 PACKAGE 25 Package TQFP14-100PIN (P-TQFP100-1212-0.40) INDEX 0.13 /0.23 0.09 /0.20 0° /10° 0.30 /0.75 Figure 25.1 TQFP14-100PIN Package Dimensions Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL 25-1 (Rev. 1.1)

  • Page 325: Appendix A List Of Peripheral Circuit Control Registers

    – – – 0046 (CLG OSC1 Control OSDRB R/WP Register) OSDEN R/WP OSC1BUP R/WP OSC1SELCR R/WP 10–8 CGI1[2:0] R/WP 7–6 INV1B[1:0] R/WP 5–4 INV1N[1:0] R/WP 3–2 – – 1–0 OSC1WT[1:0] R/WP Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-1 (Rev. 1.1)
  • Page 326 Register name Bit name Initial Reset Remarks 0x4000 SRCRESETREQ 15–8 – 0x00 – – 0060 SRC Reset Request 7–5 – – Flag Register PORBORREQ Cleared by writing 1. XRESETREQ WDTRSTREQ SVDRSTREQ KEYRSTREQ Seiko Epson Corporation AP-A-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 327 11–8 RTCHLA[3:0] – – 6–4 RTCMIHA[2:0] 3–0 RTCMILA[3:0] 0x4000 RTCASWCTL 15–12 BCD10[3:0] – 00c6 (RTCA Stopwatch 11–8 BCD100[3:0] Control Register) 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-3 (Rev. 1.1)
  • Page 328 T1MINIF T1SECIF T1_2SECIF T1_4SECIF T1_8SECIF T1_32SECIF 0x4000 RTCAINTE RTCTRMIE – 00d2 (RTCA Interrupt En- SW1IE able Register) SW10IE SW100IE 11–9 – – ALARMIE T1DAYIE T1HURIE T1MINIE T1SECIE T1_2SECIE T1_4SECIE T1_8SECIE T1_32SECIE Seiko Epson Corporation AP-A-4 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 329 Flash Controller (FLASHC) Address Register name Bit name Initial Reset Remarks 0x4000 FLASHCWAIT 15–8 – 0x00 – – 01b0 (FLASHC Flash Read 7–2 – 0x00 – Cycle Register) 1–0 RDWAIT[1:0] R/WP Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-5 (Rev. 1.1)
  • Page 330 (P1 Port Mode Select 7–0 P1SEL[7:0] 0x00 Register) 0x4000 PPORTP1FNCSEL 15–14 P17MUX[1:0] – 021e (P1 Port Function 13–12 P16MUX[1:0] Select Register) 11–10 P15MUX[1:0] 9–8 P14MUX[1:0] 7–6 P13MUX[1:0] 5–4 P12MUX[1:0] 3–2 P11MUX[1:0] 1–0 P10MUX[1:0] Seiko Epson Corporation AP-A-6 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 331 (P3 Port Function 13–12 P36MUX[1:0] Select Register) 11–10 P35MUX[1:0] 9–8 P34MUX[1:0] 7–6 P33MUX[1:0] 5–4 P32MUX[1:0] 3–2 P31MUX[1:0] 1–0 P30MUX[1:0] 0x4000 PPORTP4DAT 15–8 P4OUT[7:0] 0x00 – 0240 (P4 Port Data 7–0 P4IN[7:0] 0x00 Register) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-7 (Rev. 1.1)
  • Page 332 3–2 P51MUX[1:0] 1–0 P50MUX[1:0] 0x4000 PPORTP6DAT 15–8 P6OUT[7:0] 0x00 – 0260 (P6 Port Data 7–0 P6IN[7:0] 0x00 Register) 0x4000 PPORTP6IOEN 15–8 P6IEN[7:0] 0x00 – 0262 (P6 Port Enable 7–0 P6OEN[7:0] 0x00 Register) Seiko Epson Corporation AP-A-8 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 333 7–6 PD3MUX[1:0] 5–4 PD2MUX[1:0] 3–2 PD1MUX[1:0] 1–0 PD0MUX[1:0] 0x4000 PPORTCLK 15–9 – 0x00 – – 02e0 (P Port Clock Control DBRUN R/WP Register) 7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-9 (Rev. 1.1)
  • Page 334 10–8 P13PERISEL[2:0] Setting Register) 7–5 P12PPFNC[2:0] 4–3 P12PERICH[1:0] 2–0 P12PERISEL[2:0] 0x4000 UPMUXP1MUX2 15–13 P15PPFNC[2:0] – 030c (P14–15 Universal 12–11 P15PERICH[1:0] Port Multiplexer 10–8 P15PERISEL[2:0] Setting Register) 7–5 P14PPFNC[2:0] 4–3 P14PERICH[1:0] 2–0 P14PERISEL[2:0] Seiko Epson Corporation AP-A-10 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 335 10–8 P35PERISEL[2:0] Setting Register) 7–5 P34PPFNC[2:0] 4–3 P34PERICH[1:0] 2–0 P34PERISEL[2:0] 0x4000 UPMUXP3MUX3 15–13 P37PPFNC[2:0] – 031e (P36–37 Universal 12–11 P37PERICH[1:0] Port Multiplexer 10–8 P37PERISEL[2:0] Setting Register) 7–5 P36PPFNC[2:0] 4–3 P36PERICH[1:0] 2–0 P36PERISEL[2:0] Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-11 (Rev. 1.1)
  • Page 336 TBEIF H0/S0 Cleared by writing to the UART3_0TXD register. 0x4000 UART3_0INTE 15–8 – 0x00 – – 038e (UART3 Ch.0 – – Interrupt Enable TENDIE Register) FEIE PEIE OEIE RB2FIE RB1FIE TBEIE Seiko Epson Corporation AP-A-12 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 337: 0X4000 03A0-0X4000 03Ac 16-Bit Timer (T16) Ch.1

    (SPIA Ch.0 Mode 11–8 CHLN[3:0] Register) 7–6 – – PUEN NOCLKDIV LSBFST CPHA CPOL 0x4000 SPIA_0CTL 15–8 – 0x00 – – 03b2 (SPIA Ch.0 Control 7–2 – 0x00 – Register) SFTRST MODEN Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-13 (Rev. 1.1)
  • Page 338 (I2C Ch.0 Own 9–0 OADR[9:0] 0x000 Address Register) 0x4000 I2C_0CTL 15–8 – 0x00 – – 03ca (I2C Ch.0 Control 7–6 – – Register) TXNACK H0/S0 TXSTOP H0/S0 TXSTART H0/S0 SFTRST MODEN Seiko Epson Corporation AP-A-14 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 339: 0X4000 0400-0X4000 042C 16-Bit Pwm Timer (T16B) Ch.0

    0x00 – – 0402 (T16B Ch.0 Counter MAXBSY Control Register) 7–6 – – 5–4 CNTMD[1:0] ONEST PRESET MODEN 0x4000 T16B_0MC 15–0 MC[15:0] 0xffff – 0404 (T16B Ch.0 Max Counter Data Register) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-15 (Rev. 1.1)
  • Page 340 – 0412 (T16B Ch.0 Compare/ Capture 0 Data Register) 0x4000 T16B_0CC0DMAEN 15–8 – 0x00 – – 0414 (T16B Ch.0 Compare/ 7–4 – – Capture 0 DMA Request Enable 3–0 CC0DMAEN[3:0] Register) Seiko Epson Corporation AP-A-16 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 341 – 042a (T16B Ch.0 Compare/ Capture 3 Data Register) 0x4000 T16B_0CC3DMAEN 15–8 – 0x00 – – 042c (T16B Ch.0 Compare/ 7–4 – – Capture 3 DMA Request Enable 3–0 CC3DMAEN[3:0] Register) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-17 (Rev. 1.1)
  • Page 342 Enable Register) CMPCAP3IE CAPOW2IE CMPCAP2IE CAPOW1IE CMPCAP1IE CAPOW0IE CMPCAP0IE CNTMAXIE CNTZEROIE 0x4000 T16B_1MZDMAEN 15–8 – 0x00 – – 044e (T16B Ch.1 Counter 7–4 – – Max/Zero DMA Request Enable 3–0 MZDMAEN[3:0] Register) Seiko Epson Corporation AP-A-18 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 343 – 0462 (T16B Ch.1 Compare/ Capture 2 Data Register) 0x4000 T16B_1CC2DMAEN 15–8 – 0x00 – – 0464 (T16B Ch.1 Compare/ 7–4 – – Capture 2 DMA Request Enable 3–0 CC2DMAEN[3:0] Register) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-19 (Rev. 1.1)
  • Page 344 04a0 (T16 Ch.4 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] 3–2 – – 1–0 CLKSRC[1:0] 0x4000 T16_4MOD 15–8 – 0x00 – – 04a2 (T16 Ch.4 Mode 7–1 – 0x00 – Register) TRMD Seiko Epson Corporation AP-A-20 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 345 Register name Bit name Initial Reset Remarks 0x4000 UART3_1CLK 15–9 – 0x00 – – 0600 (UART3 Ch.1 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-21 (Rev. 1.1)
  • Page 346 3–0 TBEDMAEN[3:0] Empty DMA Request Enable Register) 0x4000 UART3_1 15–8 – 0x00 – – 0612 RB1FDMAEN 7–4 – – (UART3 Ch.1 Receive Buffer One Byte Full 3–0 RB1FDMAEN[3:0] DMA Request Enable Register) Seiko Epson Corporation AP-A-22 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 347: 0X4000 0660-0X4000 066C 16-Bit Timer (T16) Ch.6

    7–2 – 0x00 – Register) SFTRST MODEN 0x4000 SPIA_1TXD 15–0 TXD[15:0] 0x0000 – 0674 (SPIA Ch.1 Transmit Data Register) 0x4000 SPIA_1RXD 15–0 RXD[15:0] 0x0000 – 0676 (SPIA Ch.1 Receive Data Register) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-23 (Rev. 1.1)
  • Page 348 (T16 Ch.2 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x4000 T16_2INTE 15–8 – 0x00 – – 068c (T16 Ch.2 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-24 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 349: 0X4000 06C0-0X4000 06D6 I 2 C (I2C) Ch.1

    I2C_1RXD register. TBEIF H0/S0 Cleared by writing to the I2C_1TXD register. 0x4000 I2C_1INTE 15–8 – 0x00 – – 06d2 (I2C Ch.1 Interrupt BYTEENDIE Enable Register) GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-25 (Rev. 1.1)
  • Page 350 IR Remote Controller (REMC3) Address Register name Bit name Initial Reset Remarks 0x4000 REMC3CLK 15–9 – 0x00 – – 0720 (REMC3 Clock Con- DBRUN trol Register) 7–4 CLKDIV[3:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-26 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 351: 0X4000 0740-0X4000 076C 16-Bit Pwm Timer (T16B) Ch.2

    DBRUN Control Register) 7–4 CLKDIV[3:0] – – 2–0 CLKSRC[2:0] 0x4000 T16B_2CTL 15–9 – 0x00 – – 0742 (T16B Ch.2 Counter MAXBSY Control Register) 7–6 – – 5–4 CNTMD[1:0] ONEST PRESET MODEN Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-27 (Rev. 1.1)
  • Page 352 – 0752 (T16B Ch.2 Compare/ Capture 0 Data Register) 0x4000 T16B_2CC0DMAEN 15–8 – 0x00 – – 0754 (T16B Ch.2 Compare/ 7–4 – – Capture 0 DMA Request Enable 3–0 CC0DMAEN[3:0] Register) Seiko Epson Corporation AP-A-28 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 353 – 076a (T16B Ch.2 Compare/ Capture 3 Data Register) 0x4000 T16B_2CC3DMAEN 15–8 – 0x00 – – 076c (T16B Ch.2 Compare/ 7–4 – – Capture 3 DMA Request Enable 3–0 CC3DMAEN[3:0] Register) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-29 (Rev. 1.1)
  • Page 354 – figuration Register) 1–0 VRANGE[1:0] 0x4000 ADC12A_0INTF 15–9 – 0x00 – – 07a8 (ADC12A Ch.0 OVIF Cleared by writing 1. Interrupt Flag AD7CIF Register) AD6CIF AD5CIF AD4CIF AD3CIF AD2CIF AD1CIF AD0CIF Seiko Epson Corporation AP-A-30 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 355: 0X4000 07C0-0X4000 07C2 Temperature Sensor

    07c0 (TSRVR Ch.0 7–1 – 0x00 Temperature Sensor TEMPEN Control Register) 0x4000 TSRVR_0VCTL 15–8 – 0x00 – – 07c2 (TSRVR Ch.0 7–2 – 0x00 Reference Voltage Generator Control 1–0 VREFAMD[1:0] Register) Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-31 (Rev. 1.1)
  • Page 356 0810 (LCD8D Interrupt Flag 7–1 – 0x00 – Register) FRMIF Cleared by writing 1. 0x4000 LCD8DINTE 15–8 – 0x00 – – 0812 (LCD8D Interrupt 7–1 – 0x00 – Enable Register) FRMIE Seiko Epson Corporation AP-A-32 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 357: 0X4000 0840-0X4000 0850 R/F Converter (Rfc) Ch.0

    31–24 – 0x00 – – 1000 (DMAC Status 23–21 – – Register) 20–16 CHNLS[4:0] * Number of channels implemented - 1 15–8 – 0x00 – – 7–4 STATE[3:0] 3–1 – – MSTENSTAT Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-33 (Rev. 1.1)
  • Page 358 – 3–0 PRSET[3:0] 0x4000 DMACPRCLR 31–24 – – – – 103c (DMAC Priority Clear 23–16 – – – Register) 15–8 – – – 7–4 – – – 3–0 PRCLR[3:0] – – Seiko Epson Corporation AP-A-34 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 359 – ERRIESET 0x4000 DMACERRIECLR 31–24 – 0x00 – – 2014 (DMAC Error Interrupt 23–16 – 0x00 – Enable Clear Register) 15–8 – 0x00 – 7–1 – 0x00 – ERRIECLR – – Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-A-35 (Rev. 1.1)

  • Page 360: Appendix B Power Saving

    • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-B-1 (Rev. 1.1)

  • Page 361: Other Power Saving Methods

    • Setting the LCD voltage regulator into heavy load protection mode (LCD8DPWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)
  • Page 362 Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-C-1 (Rev. 1.1)
  • Page 363 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C31W65 TECHNICAL MANUAL (Rev. 1.1)

  • Page 364: Appendix D Measures Against Noise

    The resistance value should be determined by evaluating it on the mounting board. When connecting a power supply directly to the VREFA pin, insert a 100 W resistor in series. This resistance does not affect the A/D converter characteristics. Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL AP-D-1 (Rev. 1.1)

  • Page 365: Revision History

    REVISION HISTORY Revision History Code No. Page Contents 414063300 New establishment 414063301 Whole Corrected the Cortex ® -M0+ register names. manual System control register → Cortex ® -M0+ System Control Register Cortex ® -M0+ Application Interrupt and Reset Control Register Vector table offset register →...
  • Page 366 REVISION HISTORY Code No. Page Contents 414063301 10-4 10.4.2 Real-Time Clock Counter Operations Corrective operation when a value out of the effective range is set Added a note. Note: Do not set the RTCMON.RTCMOL[3:0] bits to 0x0 if the RTCMON.RTCMOH bit = 0. 10-11 10.6 Control Registers RTCA Month/Day Register...
  • Page 367 Phone: +86-755-3299-0588 Fax: +86-755-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Epson Taiwan Technology & Trading Ltd. Phone: +49-89-14005-0 Fax: +49-89-14005-110 15F, No. 100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd.

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