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NEC PD78212 User Manual

8-bit single-chip microcomputer sub-series
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USER'S MANUAL
µ PD78214 SUB-SERIES
8-BIT SINGLE-CHIP MICROCOMPUTER
 NEC Corporation 1989
HARDWARE
µ PD78212
µ PD78213
µ PD78214
µ PD78P214
µ PD78212 (A)
µ PD78213 (A)
µ PD78214 (A)
µ PD78P214 (A)
Document No. IEU-1236H
(O. D. No. IEM-5119H)
Date Published September 1994 P
Printed in Japan

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  • Page 1 USER'S MANUAL µ PD78214 SUB-SERIES 8-BIT SINGLE-CHIP MICROCOMPUTER  NEC Corporation 1989 HARDWARE µ PD78212 µ PD78213 µ PD78214 µ PD78P214 µ PD78212 (A) µ PD78213 (A) µ PD78214 (A) µ PD78P214 (A) Document No. IEU-1236H (O. D. No. IEM-5119H)
  • Page 2 PIN FUNCTIONS CPU FUNCTION CLOCK GENERATOR PORT FUNCTIONS REAL-TIME OUTPUT FUNCTION TIMER/COUNTER UNITS A/D CONVERTER ASYNCHRONOUS SERIAL INTERFACE CLOCK SYNCHRONOUS SERIAL INTERFACE EDGE DETECTION FUNCTION INTERRUPT FUNCTIONS LOCAL BUS INTERFACE FUNCTION STANDBY FUNCTION RESET FUNCTION APPLICATION EXAMPLES PROGRAMMING FOR THE µ PD78214 INSTRUCTION OPERATIONS 78K/II SERIES PRODUCT LIST DEVELOPMENT TOOLS...
  • Page 3 MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.
  • Page 4 If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance.
  • Page 5 Main Revisions in This Edition Page Description P.55 and "Caution" have been added in (a) of Fig. 4-2. P.329 "Caution" has been added in (2) of Section 12.4.6. P.383 "Caution" has been added in (b) of Section 14.4.2. P.429 Appendix B has been modified as follows: •...
  • Page 6 Readers of this manual are assumed to have a general knowledge of electronics, logical circuits, and microcom- puters. When using this manual with the µ PD78212, µ PD78213, µ PD78P214, µ PD78212(A), µ PD78213(A), µ PD78214(A), or µ PD78P214(A): This manual describes the functions of the µ PD78212, µ PD78213, µ PD78214, µ PD78P214, µ PD78212(A), µ PD78213(A), µ...
  • Page 7 Numeric value: Binary Decimal Hexadecimal : ××××H µ PD78P214 µ PD78P214(A) PROM 16K µ PD78214 µ PD78214(A) ROM 16K RAM 512 µ PD78212 µ PD78212(A) ROM 8K RAM 384 : ××××B or ×××× : ×××× µ PD78213 µ PD78213(A) ROM-less RAM 512...
  • Page 8 Floating-Point Arithme- tic Operation Programs The encircled bit number indicates that the bit name × is used as reserved word by the NEC assembler and defined by the header file, sfrbit.h, by C compiler. Write operation Read operation Either 0 or 1 can be...
  • Page 9 • Documents related to development tools IE-78240-R-A In-Circuit Emulator User's Manual IE-78240-R In-Circuit Emulator User's Manual IE-78210-R In-Circuit Emulator Hardware Operator's Manual IE-78210-R In-Circuit Emulator Software Operator's Manual IE-78210-R In-Circuit Emulator System Software Operator's Manual RA78K Series Assembler Package User's Manual 78K Series Structured Assembler Preprocessor User's Manual CC78K Series C Compiler User's Manual SD78K/II Screen Debugger User's Manual for Operation under...
  • Page 10 • Other documents Package Manual SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Quality Assurance for Semiconductor Devices Caution The above documents may be revised without notice. Use the latest versions when you designing an application system.

  • Page 12: Table Of Contents

    1.10 DIFFERENCES BETWEEN THE µ PD78213 AND µ PD78214, AND THE µ PD78213(A) AND µ PD78214(A) ...22 1.11 DIFFERENCES BETWEEN THE µ PD78P214 AND µ PD78P214(A) ...22 1.12 DIFFERENCES BETWEEN THE µ PD78212, µ PD78213, µ PD78214, AND µ PD78P214 ... 23 1.12.1 Functional Differences ...23 1.12.2 Package Differences ...23 CHAPTER 2 PIN FUNCTIONS ...25...
  • Page 13 Contents NOTES ...53 CHAPTER 4 CLOCK GENERATOR ...55 CONFIGURATION AND FUNCTION ...55 NOTES ...56 4.2.1 Inputting an external clock ...56 4.2.2 Using the Crystal/Ceramic Oscillator ...56 CHAPTER 5 PORT FUNCTIONS ...59 DIGITAL I/O PORTS ...59 PORT 0 ...60 5.2.1 Hardware Configuration ...61 5.2.2 Setting the Input/Output Mode and Control Mode ...61 5.2.3 Operation ...62 5.2.4 Built-In Pull-Up Resistor ...62...
  • Page 14 5.8.4 Built-In Pull-Up Resistor ...93 5.8.5 Notes ...93 NOTES ...93 CHAPTER 6 REAL-TIME OUTPUT FUNCTION ...95 CONFIGURATION AND FUNCTION ...95 REAL-TIME OUTPUT CONTROL REGISTER (RTPC) ...97 ACCESS TO THE REAL-TIME OUTPUT PORT ...97 OPERATION ...99 APPLICATION EXAMPLE ...102 NOTES ...104 CHAPTER 7 TIMER/COUNTER UNITS ...107 16-BIT TIMER/COUNTER ...109...
  • Page 15 Contents 7.4.6 Sample Applications ...211 NOTES ...212 7.5.1 Common Notes on All Timers/Counters ...212 7.5.2 Notes on 16-Bit Timer/Counter ...219 7.5.3 Notes on 8-Bit Timer/Counter 2 ...219 7.5.4 Notes on Using In-Circuit Emulators ...222 CHAPTER 8 A/D CONVERTER ...225 CONFIGURATION ...225 A/D CONVERTER MODE REGISTER (ADM) ...228 OPERATION ...230 8.3.1 Basic A/D Converter Operation ...230...
  • Page 16 10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE ...265 10.4.1 Basic Operation Timing ...265 10.4.2 Operation When Only Transmission Is Permitted ...267 10.4.3 Operation When Only Reception Is Permitted ...267 10.4.4 Operation When Both Transmission and Reception Are Permitted ...267 10.4.5 Action to Be Taken When the Serial Clock and Shift Become Asynchronous ...268 10.5 SBI MODE ...268 10.5.1 Features of SBI ...268...
  • Page 17 Contents 12.3.4 Multiplexed-Interrupt Handling ...313 12.3.5 Interrupt Request and Macro Service Pending ...316 12.3.6 Interrupt and Macro Service Operation Timing ...317 12.4 MACRO SERVICE FUNCTION ...319 12.4.1 Macro Service Outline ...319 12.4.2 Macro Service Types ...320 12.4.3 Macro Service Basic Operation ...321 12.4.4 Macro Service Control Register ...322 12.4.5 Macro Service Type A ...323 12.4.6 Type B Macro Service ...327...
  • Page 18 CHAPTER 16 APPLICATION EXAMPLES ...395 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS ...395 16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES ...397 CHAPTER 17 PROGRAMMING FOR THE µ PD78P214 ...399 17.1 OPERATING MODE ...399 17.2 PROCEDURE FOR WRITING INTO PROM ...399 17.3 PROCEDURE FOR READING FROM PROM ...401 17.4 NOTE ...402 CHAPTER 18 INSTRUCTION OPERATIONS ...403 18.1 LEGEND ...403...
  • Page 19 Fig. No. I/O Circuits Provided for Pins ...34 Memory Map of µ PD78212 (EA Pin Driven High) ...38 Memory Map of µ PD78212 (EA Pin Driven Low) ...39 Memory Map of µ PD78213, µ PD78214, or µ PD78P214 (EA Pin Driven Low) ...40 Memory Map of µ...

  • Page 20: Fig. No

    Fig. No. 5-25 Connection of Pull-Up Resistors (Port 4) ...79 5-26 Example of Driving an LED Directly ...79 5-27 Block Diagram of Port 5 ...80 5-28 Port 5 Mode Register Format ...81 5-29 Port Specified as an Output Port ...81 5-30 Port Specified as an Input Port ...82 5-31...
  • Page 21 Contents Fig. No. 7-16 Example of Rewriting Compare Register CR00 ...124 7-17 Example of PWM Output Signal with a 100% Duty Factor ...124 7-18 Example of PPG Output Using TM0 ...125 7-19 PPG Output When CR00 = CR01 ...126 7-20 PPG Output When CR00 = 0000H ...126 7-21 Example of Rewriting Compare Register CR00 ...127...
  • Page 22 Fig. No. 7-62 Timing of Pulse Width Measurement ...156 7-63 Setting of Control Registers for Pulse Width Measurement ...157 7-64 Setting Procedure for Pulse Width Measurement ...158 7-65 Interrupt Request Handling for Pulse Width Calculation ...158 7-66 Block Diagram of 8-Bit Timer/Counter 2 ...162 7-67 Format of Timer Control Register 1 (TMC1) ...163 7-68...
  • Page 23 Contents Fig. No. 7-106 Interrupt Request Handling for Pulse Width Calculation ...197 7-107 Example of PWM Signal Output by 8-Bit Timer/Counter 2 ...197 7-108 Setting of Control Registers for PWM Output Operation ...198 7-109 Setting Procedure for PWM Output ...199 7-110 Changing Duty Factor of PWM Output ...199 7-111...
  • Page 24 Fig. No. Software-Started Scan-Mode A/D Conversion ...235 8-10 Example of Malfunction in a Hardware-Started A/D Conversion ...236 8-11 Select-Mode A/D Conversion Started by Hardware ...237 8-12 Scan-Mode A/D Conversion Started by Hardware ...238 8-13 Example of Capacitors Connected to the A/D Converter Pins ...240 8-14 Example of Malfunction in a Hardware-Started A/D Conversion ...241 Asynchronous Serial Interface Configuration ...244...
  • Page 25 Contents Fig. No. 11-1 Format of External Interrupt Mode Register 0 (INTM0) ...294 11-2 Format of External Interrupt Mode Register 1 (INTM1) ...295 11-3 Edge Detection on Pin P20 ...296 11-4 Edge Detection on Pins P21 to P26 ...297 11-5 Erroneously Detected Edges ...297 11-6 Erroneously Detected Edges ...299...
  • Page 26 13-4 Write Timing ...348 13-5 Accessing Expansion Data Memory ...349 Data Memory Expansion for µ PD78212 (When EA = L) ...351 13-6 Data Memory Expansion for µ PD78212 (When EA = H) ...352 13-7 Data Memory Expansion for µ PD78213 and µ PD78214 (When EA = L) ...353 13-8 Data Memory Expansion for µ...
  • Page 27 Contents Fig. No. 17-1 Timing Chart for PROM Write and Verify ... 400 17-2 Write Operation Flowchart ...401 17-3 PROM Read Timing Chart ...402 Title, Page - xvi -...
  • Page 28 Table No. Port 2 Functions ...27 Port 3 Operating Mode ...29 Port 6 Operating Mode ...30 Types of I/O Circuits and Unused-Pin Handling ...33 Vector Table ...42 Selecting a Register Bank ...46 Function Names and Absolute Names ...49 Special Function Registers (SFR) ...51 Port Functions ...60 Number of I/O Ports ...60 Functions of Port 2 ...63...

  • Page 29: Table No

    Contents Table No. Modes Generating the INTAD...225 A/D Conversion Time ...232 Conditions to Generate Interrupt Requests in Each A/D Converter Operating Mode ...239 Causes of Reception Errors ...250 Baud Rate Setting ...254 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used ...255 Example of Setting the Baud Rate When 8-Bit Timer/Counter 3 Is Used (Asynchronous Serial Interface) ...257 Examples of Setting the BRGC When an External Baud Rate Input (ASCK) Is Used ...258...

  • Page 30: Chapter 1 General

    D converter, and two independent serial interfaces. The µ PD78212 is the same as the µ PD78214 except that it offers an 8-KB ROM and 384-byte RAM. The µ PD78213 is the same as the µ PD78214 except that it has no built-in ROM.
  • Page 31 µ PD78214 Sub-Series...

  • Page 32: Features

    : 16KB ( µ PD78P214) PROM • RAM: 512 bytes ( µ PD78213, µ PD78214, and µ PD78P214), or 384 bytes ( µ PD78212) ° Number of I/O pins: 54 ( µ PD78212, µ PD78214, and µ PD78P214), or 36 ( µ PD78213) •...

  • Page 33: Ordering Information And Quality Grade

    Note Note QTOP microcomputers. QTOP microcomputers are a line of one-time PROM single-chip microcomputers that are fully supported by NEC, from writing of the program, through marking and screening, to verifying. Remark ××× indicates the ROM code number. Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 ×...

  • Page 34: Quality Grade

    NEC, from writing of the program, through marking and screening, to verifying. Remark ××× indicates the ROM code number. Refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209), published by NEC Corporation, for the specifications of the quality grade of the devices and the recommended applications.

  • Page 35: Pin Configuration (Top View)

    µ PD78214 Sub-Series 1.3 PIN CONFIGURATION (TOP VIEW) 1.3.1 Normal Operating Mode (1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window P67/REFRQ/AN7 P66/WAIT/AN6 P65/WR P64/RD P63/A19 P62/A18 P61/A17 P60/A16 RESET P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8...
  • Page 36 (2) 68-pin plastic QFJ P70/AN0 P34/TO0 P35/TO1 P36/TO2 P37/TO3 P67/REFRQ/AN7 P66/WAIT/AN6 P65/WR 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Remark The NC pin is not connected inside the chip. 1 68 67 66 65 64 63 62 61 µ...
  • Page 37 µ PD78214 Sub-Series (3) 64-pin plastic QFP (14 × 14 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P64/RD P63/A19 P62/A18 P61/A17 P60/A16 RESET P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P71/AN1 P72/AN2...
  • Page 38 (4) 74-pin plastic QFP (20 × 20 mm) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 ASTB P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Remark The NC pins are not connected inside the chip.
  • Page 39 µ PD78214 Sub-Series P00-P07 : Port 0 P20-P27 : Port 2 P30-P37 : Port 3 P40-P47 : Port 4 P50-P57 : Port 5 P60-P67 : Port 6 P70-P75 : Port 7 TO0-TO3 : Timer output : Clock input : Receive data : Transmit data : Serial clock ASCK...

  • Page 40: Prom Programming Mode

    1.3.2 PROM Programming Mode (P20/NMI = 12.5 V, RESET = L) (1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window RESET (Open) Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be handled as follows: : Connect the corresponding pin independently to V : Connect the corresponding pin to V...
  • Page 41 µ PD78214 Sub-Series (2) 68-pin plastic QFJ (Open) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be handled as follows: : Connect the corresponding pin independently to V : Connect the corresponding pin to V...
  • Page 42 (3) 64-pin plastic QFP (14 × 14 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RESET (Open) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be handled as follows: : Connect the corresponding pin independently to V...
  • Page 43 µ PD78214 Sub-Series (4) 74-pin plastic QFP (20 × 20 mm) (Open) P20/NMI 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be handled as follows: : Connect the corresponding pin independently to V : Connect the corresponding pin to V...
  • Page 44 : Programming power supply RESET : Reset D0-D7 : Data bus A0-A14 : Address bus : Ground : Output enable : Power supply : Chip enable P20/NMI : Port 2/non-maskable interrupt : Non-connection Chapter 1 General...

  • Page 45: Example Application System (Printer)

    µ PD78214 Sub-Series 1.4 EXAMPLE APPLICATION SYSTEM (PRINTER)

  • Page 46: Block Diagram

    Chapter 1 General 1.5 BLOCK DIAGRAM Bus control System control Data bus (8) Bus interface SFR address/data bus...

  • Page 47: Functions

    Driving a transistor directly Real-time output ports General-purpose registers Timer/counters Serial interface Note The number of I/O pins includes special-function pins. µ PD78212 µ PD78214 µ PD78P214 333 ns 8K bytes 16K bytes 384 bytes 512 bytes 64KB for program and 1MB for data...
  • Page 48 • BCD conversion • Others • 64-pin plastic shrink DIP (750 mil) for all products • 64-pin plastic QUIP for all products other than µ PD78212, µ PD78212(A), and µ PD78P214(A) • 68-pin plastic QFJ for all products other than µ PD78212, µ...

  • Page 49: Differences Between The Μ Pd78210 And Μ Pd78213

    µ PD78214 Sub-Series 1.7 DIFFERENCES BETWEEN THE µ PD78210 Product Item RAM capacity 128 bytes I/O pins • Software programmable pull-up resistors: Not supported • Transistor direct drive outputs: Not supported Timer/counter PWM/PPG output: Not supported Serial interface Scaler for the baud rate generator output: Not supported Interrupt Macro service can be applied to some...

  • Page 50: Differences Between The Μ Pd78214 Sub-Series And Μ Pd78218A Sub-Series

    • 64-pin plastic shrink DIP (750 mil) for all products • 64-pin plastic QUIP for all products other than µ PD78212, µ PD78212(A), and µ PD78P214(A) • 68-pin plastic QFJ for all products other than µ PD78212, µ PD78212(A), µ PD78213(A), and µ...

  • Page 51: Differences Between The Μ Pd78212 And Μ Pd78212(A)

    µ PD78214 Sub-Series 1.9 DIFFERENCES BETWEEN THE µ PD78212 AND µ PD78212(A) Product Item Quality grade Package 1.10 DIFFERENCES BETWEEN THE µ PD78213 AND µ PD78214, AND THE µ PD78213(A) AND µ PD78214(A) Product Item Quality grade Maximum period in which 74-...

  • Page 52: Differences Between The Μ Pd78212, Μ Pd78213, Μ Pd78214, And Μ Pd78P214

    1.12 DIFFERENCES BETWEEN THE µ PD78212, µ PD78213, µ PD78214, AND µ PD78P214 1.12.1 Functional Differences Product name Parameter Internal ROM 8KB masked ROM at 00000H to 01FFFH 384 bytes at 0FD80H Internal RAM to 0FEFFH Port 4 Used as both...

  • Page 54: Chapter 2 Pin Functions

    2.1 PIN FUNCTION LIST 2.1.1 Normal Operating mode (1) Ports Pin name for Input/Output secondary function P00-P07 Output — INTP0 INTP1 INTP2/CI Input INTP3 INTP4/ASCK INTP5 Input/Output SO/SB0 P34-P37 TO0-TO3 P40-P47 Note 1 Input/Output AD0-AD7 Note 1 P50-P57 Input/Output A8-A15 P60-P63 Output A16-A19...
  • Page 55 Designating ROM-less operation (access to the external memory mapped to the same area as the internal ROM). Set this pin to low for the µ PD78213, or to high for the µ PD78212 and µ PD78214. Analog voltage input for A/D converter...

  • Page 56: Prom Programming Mode

    2.1.2 PROM Programming Mode (only for the µ PD78P214, P20/NMI = 12.5 V, RESET = L) Input/output P20/NMI RESET Input A0-A14 D0-D7 Input/output Input — 2.2 PIN FUNCTIONS 2.2.1 Normal Operating mode (1) P00 to P07 (Port 0): Tristate outputs Port 0, an eight-bit output port with output latches, can directly drive transistors.
  • Page 57 µ PD78214 Sub-Series (a) When functioning as a port Signals applied to these pins can be read and these pins can be tested, regardless of whether these pins are acting as secondary function pins. (b) When functioning as control-signal input pins (i) NMI (non-maskable interrupt) Apply an external non-maskable interrupt request signal to this pin.

  • Page 58: Port 3 Operating Mode

    Table 2-2 Port 3 Operating Mode (n = 0 to 7) Mode PMC3 setting (a) Port mode Pins for which port mode is specified by the PMC3 can be used independently as input or output pins by specifying the port-3 mode register (PM3). (b) Control signal I/O mode Each pin can be used as a control signal pin by specifying the PMC3 register.

  • Page 59: Port 6 Operating Mode

    µ PD78214 Sub-Series (6) P60 to P67 (port 6): Output (P60 to P63) and tristate inputs/outputs (P64 to P67) Port 6 is an eight-bit I/O port with output latches. Pins P64 to P67 are provided with software-programmable pull-up resistors. The pins of port 6 also function as control signal input pins, as listed in Table 2-3. To use these pins as control signal input pins, set up is required.

  • Page 60: Prom Programming Mode

    When this signal is high, the internal ROM is accessed. When low, the external memory is accessed in ROM- less mode. In the case of the µ PD78212, µ PD78214, and µ PD78P214, always apply a high-level signal to this pin.
  • Page 61 µ PD78214 Sub-Series (9) V Ground. (10) NC (non-connection) Not connected inside the chip.

  • Page 62: I/O Circuits And Unused-Pin Handling

    2.3 I/O CIRCUITS AND UNUSED-PIN HANDLING Table 2-4 lists the types of I/O circuits provided for each pin and describes how pins are handled when not used. Fig. 2-1 illustrates the I/O circuit types. Table 2-4 Types of I/O Circuits and Unused-Pin Handling Type of I/O circuit P00-P07 P20/NMI...

  • Page 63: I/O Circuits Provided For Pins

    µ PD78214 Sub-Series Type 1 Type 2 Schmitt trigger input with hysteresis characteristics Type 4 Data Output disable Push-pull output which can output high impedance (both the positive and negative channels are off.) Type 8-A Pull-up enable Data Output disable Type 10-A Pull-up enable...

  • Page 64: Notes

    2.4 NOTES (1) While the RESET signal is being applied, pins P60 to P63 are high impedance. When the RESET signal is released, the output of these pins is low level. Design the peripheral circuit so that it operates satisfactorily when pins P60 to P63 initially output the low level.

  • Page 66: Chapter 3 Cpu Function

    The mapping of program memory depends on the status of the EA pin. The EA pin of the µ PD78213 must be tied low. (1) µ PD78212 Program memory is mapped to the internal ROM (8K bytes: 00000H to 01FFFH) and external memory (56704 bytes: 02000H to 0FD7FH).

  • Page 67: Memory Map Of Μ Pd78212 (Ea Pin Driven High)

    µ PD78214 Sub-Series Fig. 3-1 Memory Map of µ PD78212 (EA Pin Driven High) FFFFFH 10000H 0FFFFH Special function registers (SFR) 0FFDFH Note 2 0FFD0H 0FF00H 0FEFFH 0FD80H 0FD7FH 02000H 01FFFH 00000H Notes 1. Accessed in 1M-byte expansion mode. 2. External SFR area Remark The shaded areas indicate internal memory.

  • Page 68: Memory Map Of Μ Pd78212 (Ea Pin Driven Low)

    Fig. 3-2 Memory Map of µ PD78212 (EA Pin Driven Low) FFFFFH 10000H 0FFFFH Special function registers (SFR) 0FFDFH Note 2 0FFD0H 0FF00H 0FEFFH 0FD80H 0FD7FH 00000H Notes 1. Accessed in 1M-byte expansion mode. 2. External SFR area Remark The shaded areas indicate internal memory.

  • Page 69: Memory Map Of Μ Pd78213, Μ Pd78214, Or Μ Pd78P214 (Ea Pin Driven Low)

    µ PD78214 Sub-Series Fig. 3-3 Memory Map of µ PD78213, µ PD78214, or µ PD78P214 (EA Pin Driven Low) FFFFFH 10000H 0FFFFH Special function registers (SFR) 0FFDFH Note 2 0FFD0H 0FF00H 0FEFFH 0FD00H 0FCFFH 00000H Notes 1. Accessed in 1M-byte expansion mode. 2.

  • Page 70: Memory Map Of Μ Pd78214, Μ Pd78P214 (Ea Pin Driven High)

    Fig. 3-4 Memory Map of µ PD78214, µ PD78P214 (EA Pin Driven High) FFFFFH 10000H 0FFFFH Special function registers (SFR) 0FFDFH Notes 2, 3 0FFD0H 0FF00H 0FEFFH 0FD00H 0FCFFH 04000H 03FFFH 00000H Notes 1. Accessed in 1M-byte expansion mode. 2. Accessed in external memory expansion mode 3.

  • Page 71: Internal Program Memory Area

    3.1.1 Internal Program Memory Area In the area from 00000H to 03FFFH (00000H to 01FFFH for the µ PD78212), a 16K × 8 bit ROM (8K × 8 bit ROM for the µ PD78212) is incorporated. Programs and table data are stored in this area. Usually, the program counter (PC) is used for addressing.

  • Page 72: Internal Ram Area

    3.1.5 External Memory Space The area from 04000H to 0FCFFH (02000H to 0FD7FH for the µ PD78212) is an external memory space that can be accessed by setting a memory expansion mode register (MM). In this area, programs and table data can be stored and peripheral I/O devices can be mapped.

  • Page 73: Sample Data Transfer Between Banks

    µ PD78214 Sub-Series To access the space, specify the bank to be used (high-order four bits of address, A16 to A19) in the bank register (P60 to P63 of register P6, or PM60 to PM63 of register PM6). Then, execute an instruction which allows extended addressing.

  • Page 74: Registers

    3.2 REGISTERS 3.2.1 Program Counter (PC) This 16-bit binary counter holds the address of the program to be executed next (see Fig. 3-6). Usually, the address is automatically incremented according to the number of bytes of the instruction to be fetched.

  • Page 75: Stack Pointer (Sp)

    µ PD78214 Sub-Series (3) Register bank selection flags (RBS0, RBS1) These two flags are used to select one of four register banks (see Table 3-2). The flags hold two-bit information indicating the register bank selected by the SEL RBn instruction. (4) Auxiliary carry flag (AC) If an operation generates a carry from bit 3 or a borrow into bit 3, this flag is set (1).

  • Page 76: General-Purpose Registers

    PUSH rp instruction Stack SP ← SP – 2 SP – 2 Register pair, low ↑ SP – 1 Register pair, high ↑ SP ⇒ Fig. 3-10 Data Restored from the Stack Area POP rp instruction Stack SP ⇒ Register pair, low ↓...

  • Page 77: Configuration Of General-Purpose Registers

    µ PD78214 Sub-Series Fig. 3-11 Configuration of General-Purpose Registers (8-bit processing) 0FEE0H 0FEFFH To specify the register bank to be used to execute an instruction, use the CPU control instruction (SEL RBn). When RESET is input, register bank 0 is specified. The current register bank can be checked by reading the register bank selection flags (RBS0, RBS1) in the PSW.

  • Page 78: Function Names And Absolute Names

    (2) Function General-purpose registers can be operated in units of eight bits. They can also be operated in units of 16 bits, that is, a pair of eight-bit registers can be operated as a single unit (AX, BC, DE, HL). Each register can temporarily hold operation results or can be used as an operand of an arithmetic/logical instruction between registers.

  • Page 79: Special Function Registers (Sfr)

    Table 3-4 lists the special function registers (SFR). The following column headings are used: • Symbol : Symbol indicating the built-in SFR. This is a reserved word for NEC’s assembler (RA78K/II). For the C compiler (CC78K/II), the #pragma sfr instruction allows this symbol to be used as an sfr variable.

  • Page 80: Special Function Registers (Sfr)

    Table 3-4 Special Function Registers (SFR) (1/2) Address Name of special function register (SFR) 0FF00H Port 0 0FF02H Port 2 Port 3 0FF03H 0FF04H Port 4 0FF05H Port 5 0FF06H Port 6 0FF07H Port 7 0FF0AH Port 0 buffer register 0FF0BH Port 0 buffer register 0FF0CH...
  • Page 81 µ PD78214 Sub-Series Table 3-4 Special Function Registers (SFR) (2/2) Address Name of special function register (SFR) 0FF50H 16-bit timer register 0 0FF51H 8-bit timer register 1 0FF52H 0FF54H 8-bit timer register 2 0FF56H 8-bit timer register 3 0FF5CH Prescaler mode register 0 0FF5DH Timer control register 0 0FF5EH...

  • Page 82: Notes

    3.3 NOTES (1) A program fetch from the internal RAM area is prohibited. (2) Operation of the stack pointer In stack addressing, the entire 64K bytes can be accessed. No stack area can be mapped into the SFR area or internal ROM area. (3) Special function register (SFR) Never access an address to which no SFR is mapped in the area from 0FF00H to 0FFFFH.

  • Page 84: Chapter 4 Clock Generator

    4.1 CONFIGURATION AND FUNCTION A clock generator generates and controls the internal system clock (CLK) sent to the CPU. Fig. 4-1 shows the configuration of the clock generator. Fig. 4-1 Block Diagram of Clock Generator Remarks f : Crystal/ceramic oscillation frequency : External clock frequency : Internal system clock frequency (= 1/2·f The clock oscillator oscillates according to a crystal or ceramic resonator connected to pins X1 and X2.

  • Page 85: Notes

    µ PD78214 Sub-Series Remark Different uses of the crystal and ceramic resonator Generally, a crystal’s oscillation frequency is quite stable. Crystals are ideal for high-precision time management (for example, clock or frequency measurement). In comparison with crystals, ceramic resonators are less stable but offer three advantages: a shorter oscillation start time, smaller dimensions, and lower price.

  • Page 86: Notes On Connection Of The Oscillator

    Chapter 4 Clock Generator Fig. 4-4 Notes on Connection of the Oscillator µ PD78214 Cautions 1. Place the oscillator as close as possible to pins X1 and X2. 2. Do not let other signal lines cross the circuit enclosed in a dashed line. Fig.
  • Page 87 µ PD78214 Sub-Series (c) A varying high current flows too close to the signal line. µ PD78214 High current (e) A signal is being drawn from the oscillator. µ PD78214 (2) At power-on or return from STOP mode, some time is required for the oscillation to settle. Generally, a crystal requires a few milliseconds, and a ceramic resonator several hundreds of microseconds, for the oscillation to settle.

  • Page 88: Chapter 5 Port Functions

    5.1 DIGITAL I/O PORTS The µ PD78214 has the ports shown in Fig. 5-1. These ports can be used for various types of control. Table 5-1 lists the function of each port. For ports 2 through 6, software can specify whether to use a built-in pull-up resistor for inputs.

  • Page 89: Port 0

    µ PD78214 Sub-Series Name Pin name Port 0 P00-P07 Port 2 P20-P27 Port 3 P30-P37 Note Port 4 P40-P47 Note Port 5 P50-P57 Note Port 6 P60-P63 P64-P67 Port 7 P70-P75 Note For µ PD78213, P40 through P47, P50 through P57, P64, or P65 does not function as ports. Total Port Software-specified pull-up resistors...

  • Page 90: Hardware Configuration

    5.2.1 Hardware Configuration Fig. 5-2 shows the hardware configuration of port 0. RTPC Real-time output port control register P0LM (P0HM) RTPC Port 0 mode register PM0n (PM0m) Buffer register (P0Hm) 5.2.2 Setting the Input/Output Mode and Control Mode The port 0 mode register (PM0) sets the I/O mode of port 0, as shown in Fig. 5-3. This register is set by an 8-bit data transfer instruction.

  • Page 91: Operation

    µ PD78214 Sub-Series 5.2.3 Operation Port 0 is an output-only port. Once port 0 is put in the output mode, the output latch becomes operable, enabling data transfer between the output latch and accumulator according to a transfer instruction. The output latch can be loaded with any data by a logical operation instruction.

  • Page 92: Port 2

    5.3 PORT 2 Port 2 is an 8-bit input-only port. P22 through P27 have a software-programmable built-in pull-up resistor. In addition to functioning as an input port, port 2 functions as a control signal input pin such as for external interrupts (see Table 5-3).

  • Page 93: Hardware Configuration

    µ PD78214 Sub-Series 5.3.1 Hardware Configuration Fig. 5-6 shows the configuration of port 2 Interrupt and control signals 3-wire serial I/O mode Note P20 or P21 does not have a circuit enclosed in a dotted box. 5.3.2 Setting the Input Mode and Control Mode Port 2 is an input-only port.

  • Page 94: Built-In Pull-Up Resistor

    Caution For the in-circuit emulator, the level of each port 2 pin from which noise has not been removed can be read and tested. 5.3.4 Built-In Pull-Up Resistor P22 through P27 have built-in pull-up resistors. When they must be pulled up, the built-in pull-up resistors should be used.

  • Page 95: Port 3

    µ PD78214 Sub-Series Fig. 5-9 Connection of Pull-Up Resistors (Port 2) Caution P22 through P26 are not pulled up immediately after a reset. In this case, INTP1 through INTP5 (one of the multiple functions assigned to P22 to P26) may set interrupt request flags. To avoid this problem, specify use of the pull-up resistors in the initialization routine, before clearing the interrupt flags.

  • Page 96: Port 3 Operating Modes

    The SO pin outputs serial data (during three-wire serial I/O mode). The SB0 pin is a serial bus I/O pin (during the SBI mode). Remark For bit 3 (P33) of port 3, “SB0” is a reserved word in the NEC assembly program package. The bit is also defined in a header file named sfrbit.h by the C compiler.

  • Page 97: Hardware Configuration

    µ PD78214 Sub-Series 5.4.1 Hardware Configuration Fig. 5-10 through 5-13 show the configuration of port 3. PM30 PMC30 PMC30 RxD input Fig. 5-10 Block Diagram of P30 (Port 3) Pull-up resistor option register PUO3 Port 3 mode register PM30 PMC30...

  • Page 98: Block Diagram Of P31, And P34 Through P37 (Port 3)

    Fig. 5-11 Block Diagram of P31, and P34 through P37 (Port 3) Pull-up resistor option register PUO3 Port 3 mode register PM3n PM3n PMC3n PMC3n PMC3n TO, TxD output Output latch Chapter 5 Port Functions n = 1, 4, 5, 6, 7...

  • Page 99: Block Diagram Of P32 (Port 3)

    µ PD78214 Sub-Series PM32 PMC32 PMC32 Fig. 5-12 Block Diagram of P32 (Port 3) Pull-up resistor option register PUO3 Port 3 mode register PM32 PMC32 External output Output latch SCK input...

  • Page 100: Setting The I/O Mode And Control Mode

    PM33 PMC33 PMC33 Output latch SB0 input 5.4.2 Setting the I/O Mode and Control Mode The port 3 mode register (PM3) can put each pin of port 3 in either the input or output mode independently of the other pins, as shown in Fig. 5-14. The PM3 register is loaded with data using an 8-bit data transfer instruction;...

  • Page 101: Port 3 Mode Register Format

    µ PD78214 Sub-Series PM37 PM36 PM35 Fig. 5-15 Port 3 Mode Control Register (PMC3) Format PMC3 PMC37 PMC36 PMC35 Fig. 5-14 Port 3 Mode Register Format PM34 PM33 PM32 PM31 PM30 PM3n Specifies I/O mode of pin PM3n (n = 0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) PMC34...

  • Page 102: Operation

    5.4.3 Operation Port 3 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 3 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can be transferred between the output latch and the accumulator using a transfer instruction. The output latch can be loaded with any data by a logical operation instruction.

  • Page 103: Built-In Pull-Up Resistor

    µ PD78214. Remark For bit 3 (P33) of port 3, “SB0” is a reserved word in the NEC assembly program package. The bit is also defined in a header file named sfrbit.h by the C compiler.

  • Page 104: Port 4

    Fig. 5-20 Connection of Pull-Up Resistors (Port 3) 5.5 PORT 4 Port 4 is an 8-bit I/O port with an output latch. The memory expansion mode register (MM) can put all 8 bits of this port in either the input or output mode at one time. Each pin has a software-programmable built-in pull-up resistor, and can drive an LED directly.

  • Page 105: Hardware Configuration

    µ PD78214 Sub-Series 5.5.1 Hardware Configuration Fig. 5-21 shows the hardware configuration of port 4. 5.5.2 Setting the I/O Mode and Control Mode The memory expansion mode register (MM, see Fig 13-1) specifies the operating mode of port 4, as listed in Table 5-5.

  • Page 106: Operation

    5.5.3 Operation Port 4 is an I/O port. It functions also as an address/data bus (AD0 through AD7). (1) Output port When port 4 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can be transferred between the output latch and the accumulator using a transfer instruction.

  • Page 107: Built-In Pull-Up Resistor

    µ PD78214 Sub-Series (3) Address/data bus (AD0 through AD7) Port 4 is used as the address/data automatically for external access. Do not execute I/O instructions for port 4. 5.5.4 Built-In Pull-Up Resistor Port 4 has built-in pull-up resistors. When port 4 must be pulled up, the built-in pull-up resistors should be used. Use of the built-in pull-up resistors can reduce the number of the required components and the required installation space.

  • Page 108: Driving Leds Directly

    Fig. 5-25 Connection of Pull-Up Resistors (Port 4) 5.5.5 Driving LEDs Directly For port 4, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directly on an active-low signal. Fig. 5-26 is an example of such an output buffer. Fig.

  • Page 109: Port 5

    µ PD78214 Sub-Series 5.6 PORT 5 Port 5 is an 8-bit I/O port with an output latch. The port 5 mode register (PM5) can put each bit of this port in either the input or output mode, independently of the other bits. Each pin has a software-programmable built-in pull- up resistor, and can drive an LED directly.

  • Page 110: Port 5 Mode Register Format

    PM57 PM56 PM55 EA pin For the µ PD78213, port 4 functions only as the address/data bus (AD8 through AD15). 5.6.3 Operation Port 5 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 5 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can be transferred between the output latch and the accumulator using a transfer instruction.

  • Page 111: Built-In Pull-Up Resistor

    µ PD78214 Sub-Series Caution Although its ultimate purpose is to manipulate only 1 bit, a bit manipulation instruction accesses a port in 8-bit units. If a bit manipulation instruction is used for a port some pins of which are in the output mode and the other pins of which are in the input mode, the contents of the output latch corresponding to the pin in the input mode become undefined (except for the bits manipulated by the SET1 or CLR1 instruction).

  • Page 112: Driving Leds Directly

    Fig. 5-32 Connection of Pull-Up Resistors (Port 5) 5.6.5 Driving LEDs Directly For port 5, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directly on an active-low signal. Fig. 5-33 is an example of such an output buffer. Fig.

  • Page 113: Port 6

    µ PD78214 Sub-Series 5.7 PORT 6 Port 6 is an 8-bit I/O port with an output latch. P64 through P67 have a software-programmable built-in pull-up resistor. In addition to the port functions, port 5 works as I/O pins for various control signals as listed in Table 5-7. Each control pin is operated by the corresponding function.

  • Page 114: Hardware Configuration

    (vi) AN6 and AN7 (analog input) These pins receive analog signals for the A/D converter. 5.7.1 Hardware Configuration Fig. 5-34 through 5-37 show the hardware configuration of port 6. Fig. 5-34 Block Diagram of P60 through P63 (Port 6) Memory expansion mode register Port 6 mode register PM6n Memory reference...
  • Page 115 µ PD78214 Sub-Series Fig. 5-35 Block Diagram of P64 and P65 (Port 6) PM64, PM65 External extended mode P64, P65 Pull-up resistor option register PUO6 Port 6 mode register (P65) RD signal (WR signal) Output latch PM64 (PM65) (P65)
  • Page 116 Fig. 5-36 Block Diagram of P66 (Port 6) Pull-up resistor option register PUO6 PM66 Port 6 mode register PM66 External wait specification Output latch Wait input Chapter 5 Port Functions A/D converter...

  • Page 117: Setting The I/O Mode And Control Mode

    µ PD78214 Sub-Series PM67 5.7.2 Setting the I/O Mode and Control Mode The port 6 mode register (PM6) can put port 6 in either the input or output mode as shown in Fig. 5-38. Table 5- 8 lists the operations needed to make port 6 function as control pins. P66 and P67 can always receive analog signals.

  • Page 118: Port 6 Mode Register Format

    Cautions 1. To use P60 through P63 as an output port, it is necessary to reset the PM60 through PM63 bits to 0. If they are not 0, the in- circuit emulator may not work. 2. To use the P66/WAIT pin as the WAIT pin, it is necessary to put P66 in the input mode using the PM6 register. PM67 PM66 PM65...

  • Page 119: Operation

    µ PD78214 Sub-Series 5.7.3 Operation Port 6 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 6 is in the output mode, the contents of its output latch are output, and data can be transferred between the output latch and the accumulator using a transfer instruction.

  • Page 120: Built-In Pull-Up Resistor

    (3) Control pins When port 6 function as control pins, they cannot be manipulated or tested by software. (4) Analog inputs (P66 and P67 only) When port 6 is used as analog input pins (AN6 and AN7), the level of each pin can be read and tested. 5.7.4 Built-In Pull-Up Resistor P64 through P67 have built-in pull-up resistors.

  • Page 121: Note

    µ PD78214 Sub-Series 5.7.5 Note When P66 and P67 are used as analog input pins AN6 and AN7 respectively or when A/D conversion is not performed, do not apply a voltage out of the range AV for ANI0 through ANI2 of the A/D converter mode register (ADM). See Chapter 8 for details.

  • Page 122: Operation

    5.8.3 Operation Port 7 is an input-only port, and the level of its pins can be read and tested. 5.8.4 Built-In Pull-Up Resistor Port 0 has no built-in pull-up resistor. 5.8.5 Notes (1) When P70 through P75 are used as analog input pins AN0 and AN5 respectively or when A/D conversion is not performed, do not apply a voltage out of the range AV ANI0 through ANI2 of the A/D converter mode register (ADM).
  • Page 123 µ PD78214 Sub-Series (4) P22 through P26 are not pulled up immediately after a reset, and the interrupt request flag may be set depending on the function of a dual-function pin (INTP1 through INTP5). Therefore, specify connection of a pull-up resistor in the initialization routine, before clearing the interrupt request flag. (5) With an in-circuit emulator, the level of each pin of port 2 can be read and tested before noise is removed.

  • Page 124: Chapter 6 Real-Time Output Function

    CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.1 CONFIGURATION AND FUNCTION The real-time output function is implemented by the hardware centering around port 0 and the buffer register (P0H and P0L) as shown in Fig. 6-1. The term real-time output function refers to a function that transfers data in the buffer register to the output latch by hardware for output to the outside simultaneously when a timer interrupt or external interrupt occurs.
  • Page 125 µ PD78214 Sub-Series Selector Selector...

  • Page 126: Real-Time Output Control Register (Rtpc)

    6.2 REAL-TIME OUTPUT CONTROL REGISTER (RTPC) The real-time output control register (RTPC) is an 8-bit register to specify the functions of port 0. An 8-bit manipulation instruction and a bit manipulation instruction can be used to read data from and write data to the RTPC register.

  • Page 127: Port 0 Operating Modes And Operations Needed For The Port 0 Buffer Registers

    µ PD78214 Sub-Series Table 6-1 Port 0 Operating Modes and Operations Needed for the Port 0 Buffer Registers Register Operating mode 8-bit port mode 8-bit real-time output port mode 4-bit separate real-time output port mode P00-P03: Port P04-P07: Real-time output port mode P00-P03: Real-time output port mode P04-P07: Port...

  • Page 128: Output Trigger For The Real-Time Output Port

    6.4 OPERATION When port 0 is in the real-time output port mode, the contents of the buffer registers (P0H and P0L) are sent to the output latches for output to the pins of port 0 in synchronization with the occurrence of a trigger condition listed in Table 6-2.

  • Page 129: Real-Time Output Port Operation Timing

    µ PD78214 Sub-Series Fig. 6-4 Real-Time Output Port Operation Timing 8-bit timer/ counter 1 Timer starts INTC11 interrupt request CPU operation Buffer register (P0H) Output latches (P07-P04) The contents of the buffer register and compare register are rewritten by software processing or macro service (see Section 12.4).

  • Page 130: Real-Time Output Port Operation Timing (Controlling 2 Channels Independently Of Each Other)

    Fig. 6-5 Real-Time Output Port Operation Timing (Controlling 2 Channels Independently of Each Other) 8-bit timer/ counter 1 CR11 Timer starts INTC11 interrupt request INTC10 interrupt request CPU operation Buffer register (P0H) Buffer register (P0L) Output latches (P07-P04) Output latches (P03-P00) The contents of the buffer register and compare register are rewritten by software processing or macro service (see Section 12.4).

  • Page 131: Application Example

    µ PD78214 Sub-Series 6.5 APPLICATION EXAMPLE This section describes an example of application in which P00 through P03 are used as a 4-bit real-time output port. Each time TM1 for 8-bit timer/counter 1 coincides with the contents of CR10, the contents of the P0L are output to P00 through P03.

  • Page 132: Contents Of The Control Register For The Real-Time Output Function

    Fig. 6-7 Contents of the Control Register for the Real-Time Output Function RTPC Fig. 6-8 Real-Time Output Function Setting Procedure Set the value to be output next in the P0L buffer register Chapter 6 Real-Time Output Function Uses pins P00 to P03 as real-time output ports Disables data transfer by INTP0 from the buffer register to the output latch Uses pins P04 to P07 as ordinary output ports...

  • Page 133: Interrupt Request Handling When The Real-Time Output Function Is Used

    µ PD78214 Sub-Series Fig. 6-9 Interrupt Request Handling When the Real-Time Output Function Is Used 6.6 NOTES (1) When the P0ML or P0MH is set to 1, the output buffer for the corresponding output port is turned on to output the contents of the port 0 output latch, regardless of the contents of the port 0 mode register (PM0).
  • Page 134 Chapter 6 Real-Time Output Function (4) With an in-circuit emulator, digital noise cannot be eliminated normally from the INTP0 pin. When it is specified that data transfer from the buffer register to the output latch be performed according to a signal from the INTP0 pin, data transfer may occur according to an erroneously detected edge.

  • Page 136: Chapter 7 Timer/Counter Units

    The µ PD78214 contains one 16-bit timer/counter unit (channel) and three 8-bit timer/counter units (channels). Table 7-1 Timer/Counter Types and Functions Types and functions Types Interval timer External event counter One-shot timer Functions Timer output Toggle output PWM/PPG output Real-time output Pulse width measurement Number of interrupt requests Serial interface clock source...

  • Page 137: Block Diagrams Of Timer/Counter Units

    µ PD78214 Sub-Series Fig. 7-1 Block Diagrams of Timer/Counter Units 16-bit timer/counter unit Edge detector INTP3 8-bit timer/counter unit 1 INTP0 Edge detector 8-bit timer/counter unit 2 INTP2 /CI Edge detector Edge detector INTP1 8-bit timer/counter unit 3 INTP4 Edge detector ASCK Timer register TM0 Compare register CR00...

  • Page 138: Functions

    7.1 16-BIT TIMER/COUNTER 7.1.1 Functions The 16-bit timer/counter can function as an interval timer and can also be used for programmable square wave output and pulse width measurement. In addition to these basic functions, the 16-bit timer/counter can be used for the following: •...
  • Page 139 µ PD78214 Sub-Series...

  • Page 140: Bit Timer/Counter Control Registers

    (1) 16-bit timer 0 (TM0) TM0 is a count-up timer using a count clock of f The count operation of TM0 can be enabled or disabled by timer control register 0 (TMC0). TM0 allows only read operation using a 16-bit manipulation instruction. When the RESET signal is applied, TM0 is cleared to 0000H, and count operation stops.

  • Page 141: Format Of Timer Control Register 0 (Tmc0)

    µ PD78214 Sub-Series Fig. 7-3 Format of Timer Control Register 0 (TMC0) TMC0 Remark (2) Capture/compare control register 0 (CRC0) The CRC0 register is used to specify the condition for enabling the clear operation of TM0 to be performed by a coincidence between the value of the CR01 compare register and the count value of TM0. The CRC0 register is also used to specify a timer output (TO0, TO1) mode.

  • Page 142: Format Of Timer Output Control Register (Toc)

    (3) Timer output control register (TOC) The TOC register is an 8-bit register for specifying the active level of timer output and for enabling/disabling timer output. The lower 4 bits control the timer output operation (on the TO0 and TO1 pins) of the 16-bit timer/counter. (The higher 4 bits control the timer output operation (on the TO2 and TO3 pins) of 8-bit timer/counter 2.) The TOC register allows only write operation using an 8-bit manipulation instruction.

  • Page 143: Operation Of 16-Bit Timer 0 (Tm0)

    µ PD78214 Sub-Series 7.1.4 Operation of 16-Bit Timer 0 (TM0) (1) Basic operation The 16-bit timer/counter performs count operation by counting up with a count clock of f When the RESET signal is applied, TM0 is cleared to 0000H, and count operation stops. Bit 3 (CE0) of timer control register 0 (TMC0) is used to enable/disable count operation.

  • Page 144: Tm0 Cleared By A Coincidence With Compare Register (Cr01)

    (2) Clear operation After a coincidence with the CR01 compare register, 16-bit timer 0 (TM0) can be automatically cleared. If a TM0 clear cause occurs, TM0 is cleared to 0000H by the next count clock pulse. This means that even if a TM0 clear cause occurs, TM0 holds the value existing at that time until the next count clock pulse is applied.

  • Page 145: Clear Operation When The Ce0 Bit Is Reset To 0

    µ PD78214 Sub-Series Fig. 7-8 Clear Operation When the CE0 Bit Is Reset to 0 (a) Basic operation Count clock (b) Restart after 0 is set in TM0 cleared Count clock When the CE0 bit is set to 1 after this count clock, counting starts from 0 on the count clock input after the CE0 bit has been set.

  • Page 146: Compare Register And Capture Register Operations

    7.1.5 Compare Register and Capture Register Operations (1) Compare operation The 16-bit timer/counter performs an operation to compare the values set in the compare registers with timer count values. When the values set in the compare registers (CR00, CR01) coincide with count values of 16-bit timer 0 (TM0), the coincidence signal is sent to the output control circuit.

  • Page 147: Tm0 Cleared After A Coincidence Is Detected

    µ PD78214 Sub-Series Fig. 7-10 TM0 Cleared After a Coincidence Is Detected count value Count starts CE0←1 INTC00 interrupt request INTC01 interrupt request (2) Capture operation The 16-bit timer/counter performs a capture operation to load the count value of the timer into the capture register in synchronism with an external trigger.

  • Page 148: Basic Operation Of Output Control Circuit

    count value Count starts CE0←1 INTP3 pin input INTP3 interrupt request Capture register (CR02) OVF0 Remark Dn: TM0 count value (n = 0, 1, 2, ...) CLR01 = 0 Caution With an in-circuit emulator, digital noise on the INTP3 pin cannot be removed correctly. When the capture function is used, the operation described below is performed if an edge is detected erroneously.

  • Page 149: Timer Output (To0, To1) Operation

    µ PD78214 Sub-Series...

  • Page 150: Toggle Output Operation

    (1) Basic operation By setting ENTOn (n = 0, 1) of the timer output control register (TOC) to 1, the timer outputs (TO1, TO0) can be changed with the timing determined by MOD0, MOD1, and CLR01 of capture/compare control register 0 (CRC0).

  • Page 151: Pwm Pulse Output

    µ PD78214 Sub-Series 7.1.7 PWM Output The PWM output function outputs a PWM signal whose period coincides with the full-count period of 16-bit timer 0 (TM0). The pulse width of TO0 is determined by the value of CR00, and the pulse width of TO1 is determined by the value of CR01.

  • Page 152: Example Of Pwm Output Using Tm0

    Fig. 7-14 Example of PWM Output Using TM0 FFFFH count value CR00 INTC00 INTC01 Remark ALV0 = 0, ALV1 = 0 Fig. 7-15 PWM Output When CR00 = FFFFH FFFFH Count clock period T count value INTO00 OVF flag Pulse width Pulse period = 65536T Remark ALV0 = 0 Chapter 7 Timer/Counter Units...

  • Page 153: Example Of Rewriting Compare Register Cr00

    µ PD78214 Sub-Series Even if the value of a compare register (CR00, CR01) coincides with the value of 16-bit timer 0 (TM0) more than once during one period of PWM output, the output levels on the timer outputs (TO0, TO1) do not change. Fig.

  • Page 154: Example Of Ppg Output Using Tm0

    2. If timer output is disabled (ENTOn = 0: n = 0, 1), the output level on the TOn (n = 0, 1) pin is the inverted value of the value set in ALVn (n = 0, 1). Accordingly, note that if timer output is disabled when the PWM output function is selected, the active level is output.

  • Page 155: Ppg Output When Cr00 = Cr01

    µ PD78214 Sub-Series Count period T count value INTC00 INTC01 Pulse width = nT Pulse period = (n + 1)T count value INTC00 INTC01 Pulse width = 2/f Fig. 7-19 PPG Output When CR00 = CR01 Fig. 7-20 PPG Output When CR00 = 0000H Pulse period = (n + 1)T Remark ALV0 = 0...

  • Page 156: Example Of Ppg Output Signal With A 100% Duty Factor

    Even if the value of the CR00 compare register coincides with the value of 16-bit timer 0 (TM0) more than once during one period of PPG output, the output levels on the timer outputs (TO0, TO1) are not inverted. Fig. 7-21 Example of Rewriting Compare Register CR00 count value CR00 Remark ALV0 = 1...

  • Page 157: Example Of Ppg Output Period Made Longer

    µ PD78214 Sub-Series 2. If the current value of the CR01 compare register is decreased below the value of 16-bit timer 0 (TM0), the PPG period becomes as long as the full-count time of TM0. At this time, if CR01 is rewritten after the value of the CR00 compare register coincides with the value of TM0, the inactive level is output until TM0 overflows to 0, then normal PPG output is resumed.

  • Page 158: Sample Applications

    7.1.9 Sample Applications (1) Interval timer operation (1) By free running 16-bit timer 0 (TM0), and adding a value to a compare register (CR00, CR01) in an interrupt handling routine, the 16-bit timer/counter can be used as an interval timer whose period is as long as the added value.

  • Page 159: Setting Of Control Registers For Interval Timer Operation (1)

    µ PD78214 Sub-Series Fig. 7-25 Setting of Control Registers for Interval Timer Operation (1) TMC0 CRC0 Fig. 7-26 Setting Procedure for Interval Timer Operation (1) (a) Timer control register 0 (TMC0) × (b) Capture/compare control register 0 (CRC0) Interval timer (1) Set count value in CR00 register CR00←n Set CRC0 register...

  • Page 160: Interrupt Request Handling For Interval Timer Operation (1)

    Fig. 7-27 Interrupt Request Handling for Interval Timer Operation (1) (2) Interval timer operation (2) The 16-bit timer/counter can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand. (See Fig. 7-28.) This interval timer has a resolution of 1.3 µ...

  • Page 161: Setting Of Control Registers For Interval Timer Operation (2)

    µ PD78214 Sub-Series Fig. 7-29 Setting of Control Registers for Interval Timer Operation (2) TMC0 CRC0 Fig. 7-30 Setting Procedure for Interval Timer Operation (2) (3) Pulse width measurement operation In pulse width measurement, the width of the high level or low level of an external pulse signal applied to the external interrupt request (INTP3) input pin is measured.

  • Page 162: Timing Of Pulse Width Measurement

    Fig. 7-31 Timing of Pulse Width Measurement count value Captured Count starts CE0¨ 1 INTP3 external input signal INTP3 interrupt request CR02 OVF0 Remark D : TM0 count value (n = 0, 1, 2, ...) Fig. 7-32 Setting of Control Registers for Pulse Width Measurement (a) Timer control register 0 (TMC0) ×...

  • Page 163: Setting Procedure For Pulse Width Measurement

    µ PD78214 Sub-Series (c) External interrupt mode register 1 (INTM1) INTM1 Fig. 7-33 Setting Procedure for Pulse Width Measurement Fig. 7-34 Interrupt Request Handling for Pulse Width Calculation × × × × × : Don't care Pulse width measurement Set CRC0 register CRC0←10H Set INTM1 register and MK0L register...

  • Page 164: Example Of Pwm Signal Output By 16-Bit Timer/Counter

    (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare register is output. (See Fig. 7-35.) The duty factor of a PWM output signal can be changed in steps of 1/65536 from 1/65536 to 65535/65536. In addition, 16-bit timer 0 (TM0) has two compare registers, so that two types of PWM signals can be output.

  • Page 165: Setting Procedure For Pwm Output

    µ PD78214 Sub-Series Fig. 7-38 Changing Duty Factor of PWM Output Fig. 7-37 Setting Procedure for PWM Output PWM output Set CRC0 register CRC0←90H Set TOC register Set P34 pin in control mode PMC3.4←1 Set initial value in compare register Start counting CE0←1 Preprocessing for...

  • Page 166: Example Of Ppg Signal Output By 16-Bit Timer/Counter

    (5) PPG output operation In PPG output operation, a pulse signal with a period and duty factor determined by the values set in the compare registers is output. (See Fig. 7-39.) Fig. 7-40 shows the setting of control registers. Fig. 7-41 shows the setting procedure. Fig. 7-42 shows the procedure for changing the duty factor of PPG output.

  • Page 167: Setting Procedure For Ppg Output

    µ PD78214 Sub-Series Fig. 7-42 Changing Duty Factor of PPG Output Fig. 7-41 Setting Procedure for PPG Output PPG output Set CRC0 register CRC0←D8H Set TOC register Set P34 pin in control mode PMC3.4←1 Set period in compare register CR01 Set duty factor in compare register CR00 Start counting...

  • Page 168: Functions

    7.2 8-BIT TIMER/COUNTER 1 7.2.1 Functions Eight-bit timer/counter 1 can function as an interval timer and can also be used for pulse width measurement. In addition to these basic functions, 8-bit timer/counter 1 can be used as a timer for generating an output trigger on a real-time output port.

  • Page 169: Configuration

    µ PD78214 Sub-Series 7.2.2 Configuration Eight-bit timer/counter 1 consists of one 8-bit timer 1 (TM1), one 8-bit compare register (CR10), and one 8-bit capture/compare register (CR11). Fig. 7-43 shows the block diagram of 8-bit timer/counter 1.
  • Page 170 Chapter 7 Timer/Counter Units...
  • Page 171 µ PD78214 Sub-Series (1) 8-bit timer 1 (TM1) TM1 is a timer for counting up with the count clock specified by the lower 4 bits of prescaler mode register 1 (PRM1). The count operation of TM1 can be enabled or disabled by timer control register 1 (TMC1). TM1 allows only read operation using an 8-bit manipulation instruction.

  • Page 172: Bit Timer/Counter 1 Control Registers

    7.2.3 8-Bit Timer/Counter 1 Control Registers (1) Timer control register 1 (TMC1) The TMC1 register is an 8-bit register for controlling the count operations of 8-bit timer 1 (TM1) and 8-bit timer 2 (TM2). The lower 4 bits control the count operation of TM1 of 8-bit timer/counter 1. (The higher 4 bits control the count operation of TM2 of 8-bit timer/counter 2.) The TMC1 register allows both read and write operations using an 8-bit manipulation instruction.

  • Page 173: Format Of Prescaler Mode Register 1 (Prm1)

    µ PD78214 Sub-Series Fig. 7-45 Format of Prescaler Mode Register 1 (PRM1) PRM1 PRS23 PRS22 PRS21 PRS20 Remark f : System clock frequency (3) Capture/compare control register 1 (CRC1) The CRC1 register is used to specify the operation of the CR11 capture/compare register and the condition for enabling the clear operation of 8-bit timer 1 (TM1).

  • Page 174: Operation Of 8-Bit Timer 1 (Tm1)

    7.2.4 Operation of 8-Bit Timer 1 (TM1) (1) Basic operation Eight-bit timer/counter 1 performs count operation by counting up with the count clock specified by the lower 4 bits of prescaler mode register 1 (PRM1). When the RESET signal is applied, TM1 is cleared to 00H, and count operation stops. Bit 3 (CE1) of timer control register 1 (TMC1) is used to enable/disable count operation.

  • Page 175: Tm1 Cleared By A Coincidence With Compare Register (Cr1M)

    µ PD78214 Sub-Series (2) Clear operation After a coincidence with a compare register (CR1m: m = 0, 1) or capture operation, 8-bit timer 1 (TM1) can be automatically cleared. If a TM1 clear cause occurs, TM1 is cleared to 00H by the next count clock pulse. This means that even if a TM1 clear cause occurs, TM1 holds the value existing at that time until the next count clock pulse is applied.

  • Page 176: Tm1 Cleared After Capture Operation

    Fig. 7-49 TM1 Cleared after Capture Operation Count clock INTP0 TM1 is captured to CR11 here TM1 can also be cleared by software when the CE1 bit of the timer control register (TMC1) is reset to 0. Similarly, clear operation is performed by the count clock pulse following the resetting of CE1 bit to 0. If the CE1 bit is set to 1 before TM1 is reset to 0 by the resetting of the CE1 bit to 0 (that is, before the first count clock pulse is applied after the CE1 bit is reset to 0), two operations are simultaneously performed: one operation is an operation to clear TM1 to 0, and the other operation is a count operation starting with the counting of...

  • Page 177: Compare Register And Capture/Compare Register Operations

    µ PD78214 Sub-Series (b) Restart after 0 is set in TM1 cleared Count clock (c) Restart before 0 is set in TM1 cleared Count clock 7.2.5 Compare Register and Capture/Compare Register Operations (1) Compare operation Eight-bit timer/counter 1 performs an operation to compare the values set in the compare registers with timer count values.

  • Page 178: Compare Operation

    count value INTC10 interrupt request INTC11 interrupt request OVF1 Remark CLR10 = 0, CLR11 = 0, CM = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.5.4. Fig. 7-52 TM1 Cleared After a Coincidence Is Detected count value Count starts CE1←1...

  • Page 179: Capture Operation

    µ PD78214 Sub-Series count value Count starts INTP0 pin input INTP0 interrupt request Capture/compare register(CR11) OVF1 Remark Fig. 7-53 Capture Operation : TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1...

  • Page 180: Tm1 Cleared After Capture Operations

    Fig. 7-54 TM1 Cleared after Capture Operations count value Captured INTP0 pin input INTP0 interrupt request Capture/compare register (CR11) Remark 7.2.6 Sample Applications (1) Interval timer operation (1) By free running 8-bit timer 1 (TM1), and adding a value to a compare register (CR10, CR11) in an interrupt handling routine, 8-bit timer/counter 1 can be used as an interval timer whose period is as long as the added value.

  • Page 181: Timing Of Interval Timer Operation (1)

    µ PD78214 Sub-Series Fig. 7-55 Timing of Interval Timer Operation (1) count value Timer starts Compare register (CR10) INTC10 interrupt request Remark Interval = n × x/f x = 16, 32, 64, 128, 256, 512 Fig. 7-56 Setting of Control Registers for Interval Timer Operation (1) TMC1 PRM1 (c) Capture/compare control register 1 (CRC1)

  • Page 182: Setting Procedure For Interval Timer Operation (1)

    Fig. 7-57 Setting Procedure for Interval Timer Operation (1) Fig. 7-58 Interrupt Request Handling for Interval Timer Operation (1) (2) Interval timer operation (2) Eight-bit timer/counter 1 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand.

  • Page 183: Timing Of Interval Timer Operation (2)

    µ PD78214 Sub-Series Fig. 7-59 Timing of Interval Timer Operation (2) (When CR11 Is Used As a Compare Register) count value Count starts Compare register (CR11) INTC11 interrupt request Remark Interval = (n + 1) × x/f Fig. 7-60 Setting of Control Registers for Interval Timer Operation (2) ×...

  • Page 184: Setting Procedure For Interval Timer Operation (2)

    Chapter 7 Timer/Counter Units Fig. 7-61 Setting Procedure for Interval Timer Operation (2) Interval timer (2) Set PRM1 register Set count value in CR11 register CR11←n Set CRC1 register CRC1←08H Start counting ; Sets bit 3 of TMC1 to 1 CE1←1 INTC11 interrupt (3) Pulse width measurement operation...

  • Page 185: Timing Of Pulse Width Measurement

    µ PD78214 Sub-Series Fig. 7-62 Timing of Pulse Width Measurement (When CR11 Is Used As a Capture Register) count value Count starts CE1←1 INTP0 external input signal INTP0 interrupt request Capture/compare register (CR11) OVF1 Remark D : TM1 count value (n = 0, 1, 2, ...) X = 16, 32, 64, 128, 256, 512 Captured Captured...

  • Page 186: Setting Of Control Registers For Pulse Width Measurement

    Fig. 7-63 Setting of Control Registers for Pulse Width Measurement (a) Timer control register 1 (TMC1) × × × TMC1 (b) Prescaler mode register 1 (PRM1) × × × × PRM1 (c) Capture/compare control register 1 (CRC1) CRC1 (d) External interrupt mode register 0 (INTM0) ×...

  • Page 187: Interrupt Request Handling For Pulse Width Calculation

    µ PD78214 Sub-Series Fig. 7-64 Setting Procedure for Pulse Width Measurement Fig. 7-65 Interrupt Request Handling for Pulse Width Calculation Pulse width measurement Set PRM1 register Set CRC1 register CRC1←04H Set INTM0 register and MK0L register Initialize buffer memory for capture value ←0 Start counting CE1←1...

  • Page 188: Functions

    7.3 8-BIT TIMER/COUNTER 2 7.3.1 Functions Eight-bit timer/counter 2 has two functions not available with the other three timers/counters: • External event counter • One-shot timer This section describes the following four basic functions in sequence: • Interval timer • Programmable square wave output •...

  • Page 189: Programmable Square Wave Output Setting Range Of 8-Bit Timer/Counter 2

    µ PD78214 Sub-Series (2) Programmable square wave output Eight-bit timer/counter 2 outputs a square wave separately on the TO2 and TO3 timer output pins. Table 7-12 Programmable Square Wave Output Setting Range of 8-Bit Timer/Counter 2 Caution The values in Table 7-12 assume the use of an internal clock. (3) Pulse width measurement Eight-bit timer/counter 2 measures the pulse width of a signal applied to the external interrupt input pin INTP1.

  • Page 190: Block Diagram Of 8-Bit Timer/Counter 2

    (4) External event counter Eight-bit timer/counter 2 counts clock pulses (CI pin input pulses) applied to the external interrupt input pin (INTP2). Table 7-14 indicates the clock signals that can be applied to 8-bit timer/counter 2. Table 7-14 Clock Signals That Can Be Applied to 8-Bit Timer/Counter 2 Maximum frequency Minimum pulse width (high and low level)
  • Page 191 µ PD78214 Sub-Series...

  • Page 192: Bit Timer/Counter 2 Control Registers

    (5) Output control circuit When the value of CR20 or CR21 coincides with the value of TM2, timer output can be inverted. By setting the higher 4 bits of the timer output control register (TOC), a square wave can be output on a timer output pin (TO2, TO3).

  • Page 193: Format Of Prescaler Mode Register 1 (Prm1)

    µ PD78214 Sub-Series (2) Prescaler mode register 1 (PRM1) The PRM1 register is an 8-bit register used to specify a count clock for 8-bit timer 1 (TM1) and 8-bit timer 2 (TM2). The higher 4 bits are used to specify a count clock for TM2 of 8-bit timer/counter 2. (The lower 4 bits are used to specify a count clock for TM1 of 8-bit timer/counter 1.) The PRM1 register allows only write operation using an 8-bit manipulation instruction.

  • Page 194: Format Of Capture/Compare Control Register 2 (Crc2)

    (3) Capture/compare control register 2 (CRC2) The CRC2 register is used to specify the condition for enabling the clear operation of 8-bit timer 2 (TM2) with the CR21 compare register or CR22 capture register, and also specify a timer output (TO2, TO3) mode. The CRC2 register allows only write operation using an 8-bit manipulation instruction.

  • Page 195: Format Of Timer Output Control Register (Toc)

    µ PD78214 Sub-Series (4) Timer output control register (TOC) The TOC register is an 8-bit register for controlling the active level of timer output and for enabling/disabling timer output. The higher 4 bits control the timer output operation (on the TO2 and TO3 pins) of 8-bit timer/counter 2. (The lower 4 bits control the timer output operation (on the TO0 and TO1 pins) of the 16-bit timer/counter.) The TOC register allows only write operation using an 8-bit measurement instruction.

  • Page 196: Operation Of 8-Bit Timer 2 (Tm2)

    7.3.4 Operation of 8-Bit Timer 2 (TM2) (1) Basic operation Eight-bit timer/counter 2 performs count operation by counting up with the count clock specified by the higher 4 bits of prescaler mode register 1 (PRM1). Bit 7 (CE2) of timer control register 1 (TMC1) is used to enable/disable count operation. (The higher 4 bits of the TMC1 register are used to control the operation of 8-bit timer/counter 2.) When the CE2 bit is set to 1 by software, TM2 is cleared to 00H by the first count clock pulse, then count-up operation starts.

  • Page 197: Tm2 Cleared By A Coincidence With Compare Register (Cr21)

    µ PD78214 Sub-Series (2) Clear operation After a coincidence with the CR21 compare register or capture operation, 8-bit timer 2 (TM2) can be automatically cleared. If a TM2 clear cause occurs, TM2 is cleared to 00H by the next count clock pulse. This means that even if a TM2 clear cause occurs, TM2 holds the value existing at that time until the next count clock pulse is applied.

  • Page 198: Clear Operation When The Ce2 Bit Is Reset To 0

    TM2 can also be cleared by software when the CE2 bit of the timer control register (TMC1) is reset to 0. Similarly, clear operation is performed by the count clock pulse following the resetting of CE2 bit to 0. If the CE2 bit is set to 1 before TM2 is reset to 0 by the resetting of the CE2 bit to 0 (that is, before the first count clock pulse is applied after the CE2 bit is reset to 0), two operations are simultaneously performed: one operation is an operation to clear TM2 to 0, and the other operation is a count operation starting with the counting of...

  • Page 199: External Event Counter Function

    µ PD78214 Sub-Series (c) Restart before 0 is set in TM2 cleared Count clock 7.3.5 External Event Counter Function Eight-bit timer/counter 2 can count clock pulses externally applied to the CI pin. The external event counter operation mode requires no particular selection method. TM2 functions as an external event counter when external count input is specified for the count clock of TM2 by setting the higher 4 bits of prescaler mode register 1 (PRM1).

  • Page 200: External Event Count Timing Of 8-Bit Timer/Counter 2

    Fig. 7-75 External Event Count Timing of 8-Bit Timer/Counter 2 (1) When occurrences of one edge are counted (maximum frequency = f 12/f (Min.) 12/f Countable timing of TM2 Count clock of Remark ICI: CI input signal after passing through the edge detector (2) When occurrences of both edges are counted (maximum frequency = f 16/f (Min.)

  • Page 201: Interrupt Request Generation Using External Event Counter

    µ PD78214 Sub-Series The count operation of TM2 is controlled by the CE2 bit of the TMC1 register as in the case of basic operation. When the CE2 bit is set to 1 by software, TM2 is cleared to 00H by the first count clock pulse, then count-up operation starts.

  • Page 202: Example Where Input Of No Valid Edge Cannot Be Distinguished From Input Of Only One Valid Edge With External Event Counter

    Fig. 7-77 Example Where Input of No Valid Edge Cannot Be Distinguished from Input of Only One Valid Edge with External Event Counter Cannot be distinguished Count starts Fig. 7-78 How to Distinguish Input of No Valid Edge from Input of Only One Valid Edge with External Event Counter Chapter 7 Timer/Counter Units (a) Count start processing...
  • Page 203 µ PD78214 Sub-Series Reads count value Read contents of TM2 3. With an in-circuit emulator, digital noise on the CI/INTP2 pin cannot be removed correctly. When the event counter function is used, the operation described below is performed if an edge is detected erroneously. •...

  • Page 204: One-Shot Timer Function

    7.3.6 One-Shot Timer Function Eight-bit timer/counter 2 has an operation mode in which the full-count (FFH) is reached as the result of count operation. count value Count starts CE2←1 INTC21 OVF2 As shown in Fig. 7-79, a one-shot interrupt is generated when the value (00H-FFH) set in the CR20 or CR21 register coincides with the value of TM2.

  • Page 205: Compare Register And Capture Register Operations

    µ PD78214 Sub-Series 7.3.7 Compare Register and Capture Register Operations (1) Compare operation Eight-bit timer/counter 2 performs an operation to compare the values set in the compare registers with timer count values. When the values set in the compare registers (CR20, CR21) coincide with count values of 8-bit timer 2 (TM2), the coincidence signal is sent to the output control circuit.

  • Page 206: Tm2 Cleared After A Coincidence Is Detected

    Fig. 7-81 TM2 Cleared After a Coincidence Is Detected count value Count starts CE2←1 CLR21←0 INTC20 INTC21 TO2 pin output ENTO2←1 Inactive level ALV2←1 TO3 pin output ENTO3←1 Inactive level ALV3←1 OVF2 Remark CLR22 = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.5.4. (2) Capture operation Eight-bit timer/counter 2 performs a capture operation to load the count value of the timer into the capture register in synchronism with an external trigger.

  • Page 207: Capture Operation

    µ PD78214 Sub-Series count value Count starts CE←1 INTP1 pin input INTP1 interrupt request Capture register (CR22) OVF2 CPU operation Fig. 7-82 Capture Operation Interrupt accepted Interrupt accepted (undefined) Reads CR22 Reads CR22 Remark : TM2 count value (n = 0, 1, 2, ...) CLR21 = 0, CLR22 = 0 (undefined)

  • Page 208: Tm2 Cleared After Capture Operation

    Fig. 7-83 TM2 Cleared after Capture Operation count value Captured INTP1 pin output INTP1 interrupt request Capture/compare register (CR22) Remark CLR21 = 0, CLR22 = 1 7.3.8 Basic Operation of Output Control Circuit The output control circuit controls the levels of the timer outputs (TO2, TO3) according to the coincidence signal from the compare registers.

  • Page 209: Timer Output (To2, To3) Operation

    µ PD78214 Sub-Series...

  • Page 210: Toggle Output Operation

    (1) Basic operation By setting ENTOn (n = 2, 3) of the timer output control register (TOC) to 1, the timer outputs (TO2, TO3) can be changed with the timing determined by MOD0, MOD1, and CLR21 of capture/compare control register 2 (CRC2).

  • Page 211: Pwm Pulse Output

    µ PD78214 Sub-Series Table 7-16 TO2 and TO3 Toggle Output (f Count clock Caution When using an in-circuit emulator, see the notes described in Section 7.5.4. 7.3.9 PWM Output The PWM output function outputs a PWM signal whose period coincides with the full-count period of 8-bit timer 2 (TM2).

  • Page 212: Example Of Pwm Output Using Tm2

    Table 7-17 PWM Output on TO2 and TO3 (f Count clock Minimum pulse width /128 /256 /512 Fig. 7-86 shows an example of 2-channel PWM output. Fig. 7-87 shows PWM output when FFH is set in the CR20 compare register. Fig.

  • Page 213: Pwm Output When Cr20 = Ffh

    µ PD78214 Sub-Series Count clock period T count value INTO20 OVF flag Remark ALV2 = 0 Even if the value of a compare register (CR20, CR21) coincides with the value of 8-bit timer 2 (TM2) more than once during one period of PWM output, the output levels on the timer outputs (TO2, TO3) are not inverted. Fig.

  • Page 214: Example Of Pwm Output Signal With A 100% Duty Factor

    Cautions 1. If a value less than the value of 8-bit timer 2 (TM2) is set in a compare register (CR20, CR21), a PWM signal with a 100% duty factor is output. Rewrite the CR20 or CR21 compare register, if required, by using an interrupt generated by a coincidence between TM2 and the compare register.

  • Page 215: Example Of Ppg Output Using Tm2

    µ PD78214 Sub-Series Fig. 7-90 shows an example of PPG output using 8-bit timer 2 (TM2). Fig. 7-91 shows an example of PPG output when CR20 = CR21. Fig. 7-92 shows an example of PPG output when CR20 = 00H. count value Count starts INTC20...

  • Page 216: Ppg Output When Cr20 = Cr21

    Fig. 7-91 PPG Output When CR20 = CR21 Count period T count value INTC20 INTC21 Pulse width = nT Pulse period = (n + 1)T Fig. 7-92 PPG Output When CR20 = 00H count value INTC20 INTC21 Pulse period = (n + 1)T Pulse width = 2/f Chapter 7 Timer/Counter Units...

  • Page 217: Example Of Rewriting Compare Register Cr20

    µ PD78214 Sub-Series Even if the value of the CR20 compare register coincides with the value of 8-bit timer 2 (TM2) more than once during one period of PPG output, the output level on the timer output (TO2) is not inverted. Fig.

  • Page 218: Example Of Ppg Output Period Made Longer

    2. If the current value of the CR21 compare register is decreased below the value of 8-bit timer 2 (TM2), the PPG period becomes as long as the full-count time of TM2. At this time, if CR21 is rewritten after the value of the CR20 compare register coincides with the value of TM2, the inactive level is output until TM2 overflows to 0, then normal PPG output is resumed.

  • Page 219: Sample Applications

    µ PD78214 Sub-Series 7.3.11 Sample Applications (1) Interval timer operation (1) By free running 8-bit timer 2 (TM2), and adding a value to a compare register (CR20, CR21) in an interrupt handling routine, 8-bit timer/counter 2 can be used as an interval timer whose period is as long as the added value.

  • Page 220: Setting Of Control Registers For Interval Timer Operation (1)

    Fig. 7-97 Setting of Control Registers for Interval Timer Operation (1) (a) Prescaler mode register 1 (PRM1) PRM1 PRS23 PRS22 PRS21 PRS20 (b) Capture /compare control register 0 (CRC0) CRC0 (c) Timer control register 1 (TMC1) × TMC1 Fig. 7-98 Setting Procedure for Interval Timer Operation (1) Interval timer (1) Set PRM1 register Set count value in CR20 register...

  • Page 221: Interrupt Request Handling For Interval Timer Operation (1)

    µ PD78214 Sub-Series Fig. 7-99 Interrupt Request Handling for Interval Timer Operation (1) (2) Interval timer operation (2) Eight-bit timer/counter 2 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand. (See Fig. 7-100.) Fig.

  • Page 222: Setting Of Control Registers For Interval Timer Operation (2)

    Fig. 7-101 Setting of Control Registers for Interval Timer Operation (2) (a) Prescaler mode register 1 (PRM1) PRM1 PRS23 PRS22 PRS21 PRS20 (b) Capture/compare control register 2 (CRC2) CRC2 (c) Timer control register 1 (TMC1) × TMC1 Chapter 7 Timer/Counter Units ×...

  • Page 223: Setting Procedure For Interval Timer Operation (2)

    µ PD78214 Sub-Series Fig. 7-102 Setting Procedure for Interval Timer Operation (2) Interval timer Set PRM1 register Set count value in CR21 register CR21←n Set CRC2 register CRC2←18H Set TMC1 register ; Sets bit 7 of TMC1 to 1 CE2←1 Sets normal mode (CMD2 = 0) CMD2←0 INTC21 interrupt...

  • Page 224: Timing Of Pulse Width Measurement

    Fig. 7-103 Timing of Pulse Width Measurement count value Captured Count starts INTP1 external input signal INTP1 interrupt request Capture register (CR22) OVF2 Remark D : TM2 count value (n = 0, 1, 2, ...) Fig. 7-104 Setting of Control Registers for Pulse Width Measurement (a) Prescaler mode register 1 (PRM1) PRM1 PRS23...

  • Page 225: Setting Procedure For Pulse Width Measurement

    µ PD78214 Sub-Series TMC1 (d) External interrupt mode register 0 (INTM0) INTM0 Fig. 7-105 Setting Procedure for Pulse Width Measurement (c) Timer control register 1 (TMC1) × × × × × × Pulse width measurement Set CRC1 register CRC2←10H Set INTM0 register and MK0L register Initialize buffer memory for capture value ←0...

  • Page 226: Example Of Pwm Signal Output By 8-Bit Timer/Counter 2

    Fig. 7-106 Interrupt Request Handling for Pulse Width Calculation (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare register is output. (See Fig. 7-107.) The duty factor of a PWM output signal can be changed in steps of 1/256 from 1/256 to 255/256. In addition, 8-bit timer 2 (TM2) has two compare registers, so that two types of PWM signals can be output.

  • Page 227: Setting Of Control Registers For Pwm Output Operation

    µ PD78214 Sub-Series Fig. 7-108 Setting of Control Registers for PWM Output Operation TMC1 PRM1 PRS23 PRS22 PRS21 PRS20 (c) Capture/compare control register 2 (CRC2) CRC2 × PMC3 (a) Timer control register 1 (TMC1) × × (b) Prescaler mode register 1 (PRM1) ×...

  • Page 228: Changing Duty Factor Of Pwm Output

    Fig. 7-109 Setting Procedure for PWM Output PWM output Set CRC2 register CRC2←90H Set TOC register Set P34 pin in control mode PMC3.4←1 Set count clock in PRM1 Set initial value in compare register Start counting CE2←1 (5) PPG output operation In PPG output operation, a pulse signal with a period and duty factor determined by the values set in the compare registers is output.

  • Page 229: Setting Of Control Registers For Ppg Output Operation

    µ PD78214 Sub-Series Fig. 7-112 Setting of Control Registers for PPG Output Operation TMC1 PRM1 PRS23 (c) Capture/compare control register 2 (CRC2) CRC2 × × PMC3 (a) Timer control register 1 (TMC1) × × (b) Prescaler mode register 1 (PRM1) ×...

  • Page 230: Changing Duty Factor Of Ppg Output

    Fig. 7-113 Setting Procedure for PPG Output PPG output Set CRC2 register CRC2←D8H Set TOC register Set P34 pin in control mode PMC3.6←1 Set count clock in PRM1 Set period in compare register CR21 Set duty factor in compare register CR21 Start counting CE2←1 (6) External event counter operation...

  • Page 231: Setting Of Control Registers For External Event Counter Operation

    µ PD78214 Sub-Series Fig. 7-116 Setting of Control Registers for External Event Counter Operation PRM1 (b) External interrupt mode register 0 (INTM0) INTM0 TMC1 Fig. 7-117 Setting Procedure for External Event Counter Operation (a) Prescaler mode register 1 (PRM1) × ×...

  • Page 232: One-Shot Timer Operation

    (7) One-shot timer operation When functioning as a one-shot timer, 8-bit timer/counter 2 generates only one interrupt when a specified count time has elapsed after the start of 8-bit timer 2 (TM2). (See Fig. 7-118.) An additional one-shot timer operation can be started by clearing the OVF2 bit of timer control register 1 (TMC1).

  • Page 233: Setting Procedure For One-Shot Timer Operation

    µ PD78214 Sub-Series Fig. 7-120 Setting Procedure for One-Shot Timer Operation Fig. 7-121 Procedure for Starting an Additional One-Shot Timer Operation One-shot timer Set one-shot timer mode ; Sets bit 5 of TMC1 to 1 CMD2←1 Set PRM1 register Set count value in CR21 register CR21←n Set CRC2 register CRC2←10H...

  • Page 234: Functions

    7.4 8-BIT TIMER/COUNTER 3 7.4.1 Functions Eight-bit timer/counter 3 can be used as an interval timer, and also as a counter for generating a clock signal used with the baud rate generator. When operating as an interval timer, 8-bit timer/counter 3 generates an internal interrupt at specified intervals. Table 7-19 indicates the interval setting range.

  • Page 235: Block Diagram Of 8-Bit Timer/Counter 3

    µ PD78214 Sub-Series Fig. 7-122 Block Diagram of 8-Bit Timer/Counter 3 ES41,ES40 INTP4/ASCK /512 /256 /128 Prescaler mode PRS3 PRS2 register (PRM0) (1) 8-bit timer 3 (TM3) TM3 is a timer for counting up with the count clock specified by the lower 4 bits of prescaler mode register 0 (PRM0).

  • Page 236: Bit Timer/Counter 3 Control Registers

    7.4.3 8-Bit Timer/Counter 3 Control Registers (1) Timer control register 0 (TMC0) The TMC0 register is an 8-bit register for controlling the count operation of 8-bit timer 3 (TM3). The higher 4 bits control the count operation of TM3 of 8-bit timer/counter 3. (The lower 4 bits control the count operation of TM0 of the 16-bit timer/counter.) The TMC0 register allows both read and write operations using an 8-bit manipulation instruction.

  • Page 237: Operation Of 8-Bit Timer 3 (Tm3)

    µ PD78214 Sub-Series 7.4.4 Operation of 8-Bit Timer 3 (TM3) (1) Basic operation Eight-bit timer/counter 3 performs count operation by counting up with the count clock specified by the higher 4 bits of prescaler mode register 0 (PRM0). When the RESET signal is applied, TM3 is cleared to 00H, and count operation stops. Bit 7 (CE3) of timer control register 0 (TMC0) is used to enable/disable count operation.

  • Page 238: Tm3 Cleared By A Coincidence With Compare Register (Cr30)

    (2) Clear operation After a coincidence with the CR30 compare register, 8-bit timer 3 (TM3) can be automatically cleared. If a TM3 clear cause occurs, TM3 is cleared to 00H by the next count clock pulse. This means that even if a TM3 clear cause occurs, TM3 holds the value existing at that time until the next count clock pulse is applied.

  • Page 239: Compare Register Operation

    µ PD78214 Sub-Series (b) Restart after 0 is set in TM3 cleared Count clock When the CE3 bit is set to 1 after this count clock, counting starts from 0 on the count clock input after the CE3 bit has been set. (c) Restart before 0 is set in TM3 cleared Count clock 7.4.5 Compare Register Operation...

  • Page 240: Timing Of Interval Timer Operation

    count value Count starts CE←1 INTC30 interrupt request 7.4.6 Sample Applications (1) Interval timer operation Eight-bit timer/counter 3 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand. Eight-bit timer/counter 3 can also be used for baud rate generation. This interval timer has a resolution from 1.3 µ...

  • Page 241: Common Notes On All Timers/Counters

    µ PD78214 Sub-Series Fig. 7-130 Setting of Control Registers for Interval Timer Operation × TMC0 PRS3 PRM0 Fig. 7-131 Setting Procedure for Interval Timer Operation 7.5 NOTES 7.5.1 Common Notes on All Timers/Counters (1) When the registers listed below are rewritten while a counter is operating (with the CEm bit of register TMCn is set), the counter can malfunction.
  • Page 242 (2) The OVFm flag for holding an overflow from a timer/counter is contained in register TMCn used to control the operation of the timer/counter. When a read/modify/write instruction (such as AND TMCn,#7FH) is executed, for example, the OVFm flag may be cleared. (Even if the OVFm flag is 0 when the OVFm flag is read by the CPU, the OVFm flag may already be set to 1 by a timer/counter overflow when the OVFm flag is rewritten to by the CPU.

  • Page 243: Count Start Operation

    µ PD78214 Sub-Series Fig. 7-132 Count Start Operation Count clock TMn (n = 0 to 3) Actual counting starts ←1) Count start instruction by software (CE (5) Even when an instruction is executed to stop a timer (CEn ← 0), the value of TMn is not cleared to 0 immediately.

  • Page 244: Maximum Number Of Wait States Inserted When Registers Associated With Timers/Counters Are Accessed

    (6) When a register associated with a timer/counter is accessed, wait states as many as the maximum number Note of clock pulses indicated below are automatically inserted. Note One wait state: 1/f Table 7-20 Maximum Number of Wait States Inserted When Registers Associated with Timers/Counters Are Accessed (7) While an instruction for writing to compare register CRnm (n = 0 to 3, m = 0, 1) is being executed, no coincidence is detected between the CRnm register being written to and TMn (n = 0 to 3).

  • Page 245: Example Of Pwm Output Signal With A 100% Duty Factor

    µ PD78214 Sub-Series (9) When PWM is used, a PWM signal with a 100% duty factor is output if a value less than the value of TMn (n = 0, 2) is set in compare register CRnm (n = 0, 2, m = 0, 1). CRnm rewrite operation must be performed using an interrupt generated by a coincidence between TMn and CRnm to be rewritten.

  • Page 246: Example Of Ppg Output Signal With A 100% Duty Factor

    (10)Notes on compare register rewrite operation when PPG output is used (a) If a value less than the value of TMn is written into compare register CRn0 (n = 0, 2) before the value of the CRn0 register coincides with the value of TMn (n = 0, 2), a PPG signal with a 100% duty factor is output in that period.

  • Page 247: Example Of Ppg Output Period Made Longer

    µ PD78214 Sub-Series Fig. 7-137 Example of PPG Output Period Made Longer CRn0 CRn1 (p = 0,2) Remark ALVp = 1 (c) If the PPG period is too short for interrupt acceptance, the measures described in (a) and (b) above do not lead to solution.

  • Page 248: Notes On 16-Bit Timer/Counter

    (14) With an in-circuit emulator, digital noise cannot be removed correctly. When a timer/counter is used together with edge detection function, note the point below. (a) When IE-78210-R is used Operations are performed on an erroneously detected edge. (b) When other in-circuit emulators are used •...

  • Page 249: Interrupt Request Generation Using External Event Counter

    µ PD78214 Sub-Series Fig. 7-138 Interrupt Request Generation Using External Event Counter 8 to 12 clocks Countable timing of Count clock of Coincidence between INTP2 and ICI (2) When 8-bit timer/counter 2 is used as an external event counter, TM2 alone cannot distinguish between the state where no valid edge is applied and the state where only one valid edge has been applied.

  • Page 250: How To Distinguish Input Of No Valid Edge From Input Of Only One Valid Edge With External Event Counter

    Fig. 7-140 How to Distinguish Input of No Valid Edge from Input of Only One Valid Edge with External Event Counter (a) Count start processing (b) Count value read processing Chapter 7 Timer/Counter Units Count starts Clear INTP2 interrupt request flag ;...

  • Page 251: Notes On Using In-Circuit Emulators

    µ PD78214 Sub-Series (3) With an in-circuit emulator, digital noise cannot be removed correctly. When the timer/counter is used together with edge detection function, note the point below. • When IE-78210-R is used All functions are performed on an erroneously detected edge. •...

  • Page 252: Interrupt Generation Timing Change By An Erroneously Detected Edge

    Fig. 7-141 Interrupt Generation Timing Change by an Erroneously Detected Edge count value (n = 1,2) µ For PD78214 Interrupt generation timing when CRnm = n1 (n = 1,2, m = 0,1) Emulator other than IE-78210-R µ For PD78214 Interrupt generation timing when CRnm = n2 (n = 1,2, m = 0,1) Emulator other...
  • Page 253 µ PD78214 Sub-Series (c) Event counter function (with only 8-bit timer/counter 2) An erroneously detected edge causes no change in the value of the timer/counter. However, the timing for generating an interrupt by a coincidence between the value of the timer/counter and the value of a compare register becomes faster by the number of edges detected erroneously.

  • Page 254: Chapter 8 A/D Converter

    The µ PD78214 contains an analog-to-digital (A/D) converter with eight multiplexed analog input pins (AN0 through AN7). This A/D converter uses successive approximation The conversion result is stored in an 8-bit A/D conversion result register (ADCR). Conversion can be performed at high speed (with conversion time of 30 µ s and at f and with high accuracy.
  • Page 255 µ PD78214 Sub-Series selector selector Input...

  • Page 256: Example Of Capacitors Connected To The A/D Converter Pins

    Cautions 1. To prevent malfunction due to noise, insert a capacitor between each analog input pins (AN0 through AN7) and the AV and between the reference voltage input pin (AV Fig. 8-2 Example of Capacitors Connected to the A/D Converter Pins Analog input Reference voltage input...

  • Page 257: A/D Converter Mode Register (Adm)

    µ PD78214 Sub-Series (7) Edge detector The edge detector detects the valid edge of an input at the interrupt request input pin (INTP5) and generates an external interrupt request signal (INTP5) and an external trigger for A/D conversion. The valid edge of an input at the INTP5 pin is specified by external interrupt mode register 1 (INTM1) (see Fig. 11-2).

  • Page 258: A/D Converter Mode Register (Adm) Format

    Fig. 8-3 A/D Converter Mode Register (ADM) Format Note F : System clock frequency ANI2 ANI1 ANI0 ANI2 ANI1 ANI0 Scan mode Select mode Controls conversion speed Note 180/f Note 120/f Controls external terminal trigger Disables external trigger Enables external trigger Controls A/D conversion Stops A/D conversion Starts A/D conversion...

  • Page 259: Basic A/D Converter Operation

    µ PD78214 Sub-Series 8.3 OPERATION 8.3.1 Basic A/D Converter Operation (1) A/D conversion sequence The A/D converter operates as follows: (a) The input selector selects one of the analog input pins (AN0 through AN7) according to the mode of operation specified in the A/D converter mode register (ADM). (b) The sample and hold circuit samples the voltage at the analog input pin selected by the input selector.

  • Page 260: Relations Between Analog Input Voltages And A/D Conversion Results

    A/D conversion continues until the CS bit is reset by software. If data is written to the ADM register during conversion, conversion is initialized. If the CS bit is 1, conversion is started from the beginning. When the RESET signal is input, the ADCR register contents become undefined. (2) Input voltage and conversion result The analog voltages input to the analog input pins (AN0 through AN7) are related to the A/D conversion result (value held in the ADCR), as follows:...

  • Page 261: Select Mode

    µ PD78214 Sub-Series (3) A/D conversion time The time required for A/D conversion is determined by the system clock frequency (f ADM register. To maintain A/D conversion accuracy above a certain level, it is necessary to set the FR bit as listed in Table 8-2 according to the system clock frequency.

  • Page 262: Scan Mode

    8.3.3 Scan Mode In the scan mode, signals input from the analog input pins, specified by bits 1 through 3 (ANI0 through ANI2) of the A/D converter mode register (ADM), are selected successively for conversion. For example, when the ANI2 through ANI0 bits of the ADM register are 001, the AN0 and AN1 pins are scanned repeatedly, starting at the ANI0 pin in the sequence: AN0 →...

  • Page 263: A/D Conversion Activated By Software Start

    µ PD78214 Sub-Series 2. If the ADM register is set after registers related to interrupts have been set during the scan mode, an unwanted interrupt may occur, thus causing the storage location of the conversion result to appear to have shifted. To prevent this, take the actions listed below in the stated order.

  • Page 264: A/D Conversion Activated By Hardware Start

    (2) Scan-mode A/D conversion When triggered, conversion begins with the signal input to the AN0 pin. When the conversion sequence for the AN0 pin is completed, the signal at the next analog input pin is converted. Each time a conversion sequence is completed, an interrupt request (INTAD) is generated.

  • Page 265: Example Of Malfunction In A Hardware-Started A/D Conversion

    µ PD78214 Sub-Series Fig. 8-10 Example of Malfunction in a Hardware-Started A/D Conversion INTP5 Conversion trigger A/D converter operatioon ADCR INTAD Notes 1. When the operation is normal, the result of conversion 2 is stored. If a malfunction occurs, however, value 7FH is stored. 2.

  • Page 266: Select-Mode A/D Conversion Started By Hardware

    Fig. 8-11 Select-Mode A/D Conversion Started by Hardware INTP5 pin input (rising edge valid) A/D conversion Standby state ADM writing CS←1, TRG←1 ADCR INTAD Remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 (2) Scan-mode A/D conversion When A/D conversion is started, the analog signal input to the AN0 pin is converted.
  • Page 267 µ PD78214 Sub-Series...

  • Page 268: Interrupt Request From The A/D Converter

    8.4 INTERRUPT REQUEST FROM THE A/D CONVERTER The A/D converter generates an A/D conversion end interrupt request (INTAD), each time a conversion sequence is completed, except for the select mode. The interrupt control flags are shared by the INTAD interrupt and the INTP5 external interrupt. Therefore, the timing at which an interrupt request occurs varies depending on the mode of A/D conversion specified in the ADM register, as listed in Table 8-3.

  • Page 269: Example Of Capacitors Connected To The A/D Converter Pins

    µ PD78214 Sub-Series (2) About hardware-started A/D conversion (a) Eight to twelve system clocks are required from when a valid edge appears at the INTP5 pin until A/D conversion is actually started. Take this delay into consideration when designing your application. See Chapter 11 for details of the edge detection function.

  • Page 270: Example Of Malfunction In A Hardware-Started A/D Conversion

    Fig. 8-14 Example of Malfunction in a Hardware-Started A/D Conversion INTP5 Conversion trigger A/D converter operatioon ADCR INTAD Notes 1. When the operation is normal, the result of conversion 2 is stored. If a malfunction occurs, however, value 7FH is stored. 2.

  • Page 272: Chapter 9 Asynchronous Serial Interface

    CHAPTER 9 ASYNCHRONOUS SERIAL INTERFACE The µ PD78214 contains an asynchronous serial interface, UART (Universal Asynchronous Receiver Transmitter). This interface transmits 1-byte data following a start bit and is capable of full-duplex transmission. The µ PD78214 also contains a baud rate generator for UART, which allows data to be transmitted at a wide baud rate range.
  • Page 273 µ PD78214 Sub-Series Selector...

  • Page 274: Asynchronous Serial Interface Control Register

    (1) Reception buffer (RXB) The reception buffer holds the receive data. Each time the shift register receives 1 byte of data, it sends it to this reception buffer. If the data length is specified to be 7 bits, the receive data is sent to bits 0 through 6 of the RXB. The MSB of the RXB is always kept as 0.

  • Page 275: Format Of The Asynchronous Serial Interface Mode Register (Asim)

    µ PD78214 Sub-Series Fig. 9-2 Format of the Asynchronous Serial Interface Mode Register (ASIM) ASIM Cautions 1. The asynchronous serial interface mode register (ASIM) must not be modified during transmission. If the ASIM register is modified during transmission, further transmission becomes impossible (inputting the RESET signal resumes normal operation).

  • Page 276: Asynchronous Serial Interface Operations

    Fig. 9-3 Format of the Asynchronous Serial Interface Status Register (ASIS) ASIS Caution Be sure to read the reception buffer (RXB) contents, even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the error status will persist. 9.3 ASYNCHRONOUS SERIAL INTERFACE OPERATIONS 9.3.1 Data Format Fig.

  • Page 277: Transmission

    µ PD78214 Sub-Series • Odd parity In contrast to even parity, the parity bit for odd parity is controlled so that the number of 1 bits in the transmit data becomes odd. When data is received, the number of 1 bits in it is counted, and if the number of 1 bits is even, a parity error is detected.

  • Page 278: Reception

    9.3.4 Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set to 1, reception is enabled, and the input to the RxD pin is sampled. Sampling at the RxD pin is performed using the serial clock specified in the ASIM register. When the input to the RxD pin becomes low, the 1/16 frequency division counter starts counting.

  • Page 279: Reception Error Timing

    µ PD78214 Sub-Series Reception error Parity error Framing error Overrun error Note Reception assumes that only one stop bit is used. Therefore, if the transmission end uses a two-stop bit format, and the second stop bit is low when received, no reception error is detected; it is recognized as the start bit of the next data. RxD (Input) INTSR INTSER...

  • Page 280: Baud Rate Generator

    9.4 BAUD RATE GENERATOR 9.4.1 Configuration of the Baud Rate Generator for UART Fig. 9-8 shows the configuration of the baud rate generator. Fig. 9-8 Baud Rate Generator Clock Configuration Asynchronous serial interface Clock synchronous serial interface (1) 4-bit counter The 4-bit counter counts the internal system clock (f by the lower four bits of the baud rate generator control register (BRGC).

  • Page 281: Baud Rate Generator Control Register (Brgc) Format

    µ PD78214 Sub-Series Fig. 9-9 Baud Rate Generator Control Register (BRGC) Format BRGC TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 TPS2 TPS1 TPS0 Frequency divider tap 1/n Operations of 4-bit counter and frequency divider Stop Counting operation Input clock of baud rate generator External clock input (ASCK)

  • Page 282: Operation Of The Baud Rate Generator For Uart

    9.4.3 Operation of the Baud Rate Generator for UART The baud rate generator for UART starts operating, when the CE bit of the baud rate generator control register (BRGC) is set to 1. The baud rate clock to be generated is a signal obtained by dividing either the internal system clock (f ) or the clock input from the external baud rate input (ASCK) pin.

  • Page 283: Example Of Setting The Brgc Register When The Baud Rate Generator For Uart Is Used

    µ PD78214 Sub-Series 9.5 BAUD RATE SETTING The baud rate can be set by three methods listed in Table 9-2. The table indicates the ranges of baud rates that can be generated by each method, the baud rate calculation formulas, and the selection methods. Baud rate clock source Baud rate Internal...
  • Page 284 Chapter 9 Asynchronous Serial Interface...

  • Page 285: Example Of Setting The Baud Rate When 8-Bit Timer/Counter 3 Is Used

    µ PD78214 Sub-Series 9.5.2 Example of Setting the Baud Rate When 8-bit Timer/Counter 3 Is Used Table 9-4 lists examples of setting the baud rate when 8-bit timer/counter 3 is used. When using 8-bit timer/ counter 3, reset the SCK bit of the asynchronous serial interface mode register (ASIM) to 0. See Section 7.4 for how to use 8-bit timer/counter 3.
  • Page 286 Chapter 9 Asynchronous Serial Interface...

  • Page 287: Example Of Setting The Brgc When The External Baud Rate Input (Asck Is Used

    µ PD78214 Sub-Series 9.5.3 Example of Setting the BRGC When the External Baud Rate Input (ASCK) Is Used Table 9-5 lists examples of setting the BRGC register when an external baud rate input (ASCK) is used. To use the ASCK input, set the SCK bit of the asynchronous serial interface mode register (ASIM) to 1. Table 9-5 Examples of Setting the BRGC When an External Baud Rate Input (ASCK) Is Used 9.6 NOTES (1) The asynchronous serial interface mode register (ASIM) must not be modified during transmission.

  • Page 288: Function

    In this mode, the device can communicate with two or more devices via two lines, the serial clock (SCK) and serial data bus line (SB0). This mode conforms to the NEC serial bus format. In SBI mode, an address for selecting a target device for serial communication, a command specifying the operation of the target device, and actual data can be output on the serial data bus.
  • Page 289 µ PD78214 Sub-Series Selector...
  • Page 290 (1) Shift register (SIO) Converts 8-bit serial data into 8-bit parallel data and vice versa. The SIO is used for both transmission and reception. Data is shifted in (received) or shifted out (transmitted) from the MSB. The actual transmission/reception is controlled by writing or reading the contents of the SIO. The 8-bit manipulation instruction can read or write the contents of this register.

  • Page 291: Control Registers

    µ PD78214 Sub-Series 10.3 CONTROL REGISTERS 10.3.1 Clock Synchronous Serial Interface Mode Register (CSIM) This 8-bit register specifies a serial interface operation mode, serial clock and wake-up function. The 8-bit manipulation instruction and bit manipulation instruction can read and write the contents of the CSIM register.

  • Page 292: Serial Bus Interface Control Register (Sbic)

    10.3.2 Serial Bus Interface Control Register (SBIC) The SBIC register consists of bits that control the status of the serial bus, as well as bits that indicate the status of the data input from the serial bus. This 8-bit register can be used only in SBI mode, not in three-wire serial I/O mode.

  • Page 293: Format Of Serial Bus Interface Control Register (Sbic)

    µ PD78214 Sub-Series Fig. 10-3 Format of Serial Bus Interface Control Register (SBIC) SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT Trigger output control for bus release signal (REL) Not output Output CMDT Trigger output control for command signal (CMD) Not output Output RELD...

  • Page 294: Operations In The Three-Wire Serial I/O Mode

    10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE In three-wire serial I/O mode, the device can communicate with a device having a conventional clock synchronous serial interface. Basically, communication is performed over three lines of serial clock (SCK), serial data output (SO) and serial data input (SI).

  • Page 295: Timing In Three-Wire Serial I/O Mode

    µ PD78214 Sub-Series Fig. 10-5 Timing in Three-Wire Serial I/O Mode Note SI (input) SO (output) INTCSI Notes In three-wire serial I/O mode, the SO pin sends a CMOS push-pull output. Remark When connecting the device to a device having two-wire serial I/O, connect a buffer to the SO pin as shown in Fig. 10-6. In the example shown in Fig.

  • Page 296: Operation When Only Transmission Is Permitted

    10.4.2 Operation When Only Transmission Is Permitted Transmission is enabled when the CTXE bit of the clock synchronous serial interface mode register (CSIM) is set (1). If the CTXE bit is set, writing the contents of the shift register (SIO) invokes the start of transmission. If the CTXE bit is reset (0), the output from the SO pin goes to the high-impedance state.

  • Page 297: Action To Be Taken When The Serial Clock And Shift Become Asynchronous

    10.5 SBI MODE SBI (serial bus interface) is a high-speed serial interface conforming to the NEC serial bus format. SBI is a high-speed serial bus with a single master, consisting of a clock synchronous serial I/O and a bus configuration function.

  • Page 298: Sample Serial Bus Configured With Sbi

    (2) Function to select a chip by its address The master sends an address to select a slave chip. (3) Wake-up function Using the wake-up function (which can be set or released by software), a slave device can easily detect whether it receives the address (chip select).

  • Page 299: Configuration Of The Serial Interface

    µ PD78214 Sub-Series 10.5.2 Configuration of the Serial Interface Fig. 10-9 is a block diagram of the µ PD78214. The serial clock pin (SCK) and serial data bus pin SB0 are configured as shown in Fig. 10-8. (1) SCK: Pin to input/output the serial clock •...
  • Page 300 Chapter 10 Clock Synchronous Serial Interface Selector...

  • Page 301: Detecting An Address Match

    µ PD78214 Sub-Series 10.5.3 Detecting an Address Match SBI communication is started when a slave device is selected according to the address sent by the master device. The software detects whether the address of a slave device matches the sent address. In the wake-up state (WUP set to 1), the slave device generates a serial transfer completion interrupt request only when it receives the address.

  • Page 302: Format Of Clock Synchronous Serial Interface Mode Register (Csim)

    Fig. 10-10 Format of Clock Synchronous Serial Interface Mode Register (CSIM) CSIM CTXE CRXE Caution Do not change CTXE from 0 to 1 or CRXE from 1 to 0, or vice versa, by means of a single instruction. If this is attempted, the serial clock counter will malfunction and the first communication after the change will be terminated before the eighth bit is sent.

  • Page 303: Format Of Sbic Register

    µ PD78214 Sub-Series (2) Serial bus interface control register (SBIC) This 8-bit register consists of bits controlling the serial bus statuses and flags indicating the statuses of data input from the serial bus. The 8-bit manipulation instruction and bit manipulation instruction can read and write the contents of the register.
  • Page 304 Fig. 10-11 Format of SBIC Register (2/2) Acknowledge trigger bit (W) When this bit is set after transfer, ACK is output in synchronization with the next SCK. After the ACK signal is output, this bit is automatically cleared to 0. Do not set this bit to 1 before serial transfer is completed.

  • Page 305: Configuration Of Shift Register And Related Components

    µ PD78214 Sub-Series (3) Shift register (SIO) This 8-bit shift register is used for parallel-serial conversion. The data written into the SIO is output to the serial data bus. The data on the serial data bus is read into the SIO.

  • Page 306: Sbi Communication And Signals

    10.6 SBI COMMUNICATION AND SIGNALS This section describes the format of the SBI serial data and signals to be used. Serial data transferred via SBI can be divided into three groups: address, command, and data. Each frame of serial data is formed as shown below: (bus release signal) + (command signal) + 8-bit data + ACK + (BUSY) Fig.

  • Page 307: Address

    µ PD78214 Sub-Series 10.6.2 Command Signal (CMD) The command signal is the SB0 line going from high to low while the SCK line is high (the serial clock is not output). The master device outputs this signal. The slave device contains the hardware to detect the command signal. 10.6.3 Address The master device outputs an address, which is 8-bit data, to select one of the slave devices connected to the bus line.

  • Page 308: Command And Data

    10.6.4 Command and Data The master device sends commands to, and sends or receives data to or from, the slave device selected according to the specified address. Command signal The 8-bit data following the command signal is defined as a command. The 8-bit data without the command signal is defined as data.

  • Page 309: Busy Signal (Busy) And Ready Signal (Ready)

    µ PD78214 Sub-Series 10.6.6 Busy Signal (BUSY) and Ready Signal (READY) The busy signal informs the master device that the slave device is preparing for data transmission or reception. The ready signal informs the master device that the slave device is ready for data transmission or reception. In SBI mode, the slave device drives the SB0 line low to inform the master device that the slave is busy.

  • Page 310: Ackt Operation

    ACKT Caution Do not set ACKT before transfer has been completed. (a) When ACKE is set to 1 at the end of transfer ACKE (b) When ACKE is set after transfer has been completed ACKE (c) When ACKE is set to 0 at the end of transfer ACKE Chapter 10 Clock Synchronous Serial Interface Fig.

  • Page 311: Ackd Operations

    µ PD78214 Sub-Series (d) When ACKE is set to 1 for a short period of time ACKE (a) When the ACK signal is output during the ninth cycle of the SCK clock ACKD (b) When the ACK signal is output after the ninth pulse of the SCK clock ACKD (c) Clear timing when a transfer start is specified in the busy state ACKD...

  • Page 312: Bsye Operation

    Chapter 10 Clock Synchronous Serial Interface Fig. 10-26 BSYE Operation BUSY BSYE When BSYE = 1 at this point When reset operation is executed during this period and BSYE = 0 at the falling edge of SCK.
  • Page 313 µ PD78214 Sub-Series...
  • Page 314 Chapter 10 Clock Synchronous Serial Interface...
  • Page 315 µ PD78214 Sub-Series...

  • Page 316: Communication

    10.6.8 Communication In SBI communication, the master device outputs an address on the serial bus and, usually, one target slave device is selected out of two or more devices according to the address. Once the target device has been determined, commands and data are transferred between the master device and slave device to implement serial communication.
  • Page 317 µ PD78214 Sub-Series...
  • Page 318 Chapter 10 Clock Synchronous Serial Interface...
  • Page 319 µ PD78214 Sub-Series...
  • Page 320 Chapter 10 Clock Synchronous Serial Interface...

  • Page 321: Notes

    µ PD78214 Sub-Series 10.7 NOTES (1) Do not change CTXE from 0 to 1 and CRXE from 1 to 0, or vice versa, by means of a single instruction. If this is attempted, the serial clock counter will malfunction and the first communication after the change will be terminated before the eighth bit is sent.

  • Page 322: External Interrupt Mode Registers (Intm0, Intm1)

    CHAPTER 11 EDGE DETECTION FUNCTION Pins P20 to P26 support an edge detection function to program a rising or falling edge. The detected edge is sent to the internal hardware. Table 11-1 shows the relationship between pins P20 to P26, and the use of the detected edge.

  • Page 323: Format Of External Interrupt Mode Register 0 (Intm0)

    µ PD78214 Sub-Series Fig. 11-1 Format of External Interrupt Mode Register 0 (INTM0) INTM0 ES21 ES20 ES11 ES10 ES01 ES00 ESNMI ESNMI Specifies edge to be detected on P20 (NMI) Falling edge Rising edge Specifies edge to be detected on P21 (INTP0, CR11 ES01 ES00 capture trigger, real-time output port output trigger)

  • Page 324: Format Of External Interrupt Mode Register 1 (Intm1)

    Fig. 11-2 Format of External Interrupt Mode Register 1 (INTM1) INTM1 ES51 Caution If an edge is input while a valid edge is changing, it is not known whether the new edge is judged as being a valid edge. Chapter 11 Edge Detection Function ES50 ES41 ES40...

  • Page 325: Edge Detection On Pin P20

    µ PD78214 Sub-Series 11.2 EDGE DETECTION ON PIN P20 An edge on pin P20 is detected after noise elimination by means of analog delay. A pulse width of at least 10 µ s is required to detect the edge. P20 input P20 after noise rejection Rising edge detection signal...

  • Page 326: Edge Detection On Pins P21 To P26

    11.3 EDGE DETECTION ON PINS P21 TO P26 An edge on pins P21 to P26 is detected after digital noise elimination by means of clock sampling. The digital noise elimination is performed by means of sampling with the f eliminated as noise if an identical level is not obtained three or more times in a row (even if an identical level is consecutively obtained twice).

  • Page 327: Notes

    µ PD78214 Sub-Series (b) Erroneously detected edge during input of a high signal INTPn input (n = 0 to 6) After noise rejection Falling edge detection Rising edge detection If the IE-78210-R is used, the real-time output port, timer/counter, and A/D converter operate according to the erroneously detected edge.

  • Page 328: Erroneously Detected Edges

    (5) If noise input to pins P21 to P26 is synchronized with the f as being noise. If the input of such noise is possible, add a filter to the input pin so that the noise can be eliminated. (6) An in-circuit emulator cannot successfully eliminate digital noise. It may erroneously detect a falling edge due to noise during the input of a low signal and a rising edge due to the noise during the input of a high signal (see Fig.
  • Page 329 µ PD78214 Sub-Series • Compare operation of the timer/counter : If the mode for carrying out a clear operation after a capture operation is selected, or if timer/counter 2 is used as an external event counter, the erroneously detected edge causes the timing of match interrupt generation to be changed.

  • Page 330: Chapter 12 Interrupt Functions

    CHAPTER 12 INTERRUPT FUNCTIONS The µ PD78214 has the following two interrupt handling modes. Either mode can be selected by the program. Interrupt handling by a macro service is limited to the interrupt request sources provided with a macro service handling mode listed in Table 12-1.

  • Page 331: Software Interrupt Request

    µ PD78214 Sub-Series 12.1 INTERRUPT REQUEST SOURCES The µ PD78214 has 19 interrupt request sources shown in Table 12-2. Each of these sources is assigned an interrupt vector table. Interrupt Default request type priority Software None BRK instruction execution Nonmaskable None NMI (edge input to the pin is detected) Maskable...

  • Page 332: Nonmaskable Interrupt Request

    12.1.2 Nonmaskable Interrupt Request A nonmaskable interrupt request is input to the NMI pin. When a valid edge, specified by bit 0 (ESNMI) of external interrupt mode register 0 (INTM0), is input to the NMI pin, an interrupt request is generated. A nonmaskable interrupt request is accepted unconditionally, even in an interrupt disabled state.

  • Page 333: Interrupt Handling Control Registers

    µ PD78214 Sub-Series (2) Selecting INTP5 or INTAD Interrupt INTP5 or INTAD is selected by the A/D converter mode register (ADM). (Either of these interrupts is selected automatically, according to the mode of operation specified for the A/D converter.) Both 8-bit manipulation instruction and bit manipulation instruction can be used to read data from and write data to the ADM register.

  • Page 334: Interrupt Request Flag Register (If0)

    Table 12-3 Flags for Interrupt Request Sources Interrupt request source INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC21 INTP4 INTC30 INTP5 INTAD INTC20 INTSER INTSR INTST INTCSI 12.2.1 Interrupt Request Flag Register (IF0) The IF0 register is a 16-bit register consisting of interrupt request flags. Each interrupt request flag is set to 1, when the corresponding interrupt request occurs.

  • Page 335: Interrupt Mask Register (Mk0)

    µ PD78214 Sub-Series 12.2.2 Interrupt Mask Register (MK0) The MK0 register is a 16-bit register consisting of interrupt mask flags. Each interrupt mask flag enables or disables the corresponding interrupt request. When the RESET signal is input, the register is set to FFFFH, thus disabling all maskable interrupts. If an interrupt mask flag is set to 1, it inhibits acceptance of the corresponding interrupt request.

  • Page 336: Interrupt Status Register (Ist)

    When a low-priority vectored interrupt is being handled, vectored interrupt requests with lower and higher priorities are accepted for multiple-interrupt handling provided that interrupts are enabled. When a high-priority interrupt is being handled, high-priority vectored interrupts are accepted for multiple-interrupt handling provided that interrupts are enabled.

  • Page 337: Interrupt Handling

    µ PD78214 Sub-Series 12.2.6 Program Status Word (PSW) The PSW is a register that holds the result of instruction execution and the current status of interrupt requests. The register is mapped with the IE flag that specifies whether to enable maskable interrupts and the ISP flag to control multiple-interrupt handling.

  • Page 338: Accepting An Nmi Interrupt Request

    Resetting the NMIS bit to 0 during execution of a nonmaskable interrupt service program enables multiple- interrupt handling for nonmaskable interrupt requests. If the NMIS bit is 0, a new nonmaskable interrupt request is accepted even when a nonmaskable interrupt service program is running. Fig.
  • Page 339 µ PD78214 Sub-Series (c) If a new NMI request occurs during execution of an NMI service program (when the NMIS bit is reset to 0 by the current NMI service program after the NMI request occurs) Main routine NMI request (d) If two new NMI requests occur during execution of an NMI service program (when the NMIS bit is not manipulated by the current NMI service program) Main routine...

  • Page 340: Accepting Maskable Interrupts

    3. Nonmaskable interrupts are always accepted except during execution of the nonmaskable interrupt handling program (except when multiple-interrupt handling for nonmaskable interrupts have been enabled by resetting the NMIS bit of the IST register to 0 during execution of the nonmaskable interrupt handling program) and except a period between a special instruction described in Section 12.3.5 and an instruction that follows that special instruction.

  • Page 341: Interrupt Handling Algorithm

    µ PD78214 Sub-Series Interrupt request pending Is there a high-priority interrupt Interrupt request pending Macro service processing Interrupt request pending Fig. 12-10 Interrupt Handling Algorithm ××IF = 1? ××MK = 0? Yes (high priority) ××PR = 0? among interrupts for ××PR = 0 that have occurred Interrupts for simultaneously?

  • Page 342: Multiple-Interrupt Handling

    12.3.4 Multiple-Interrupt Handling The µ PD78214 performs multiple-interrupt handling in which another interrupt request is accepted during one interrupt is already being handled. Multiple-interrupt handling runs according to priority. Priority control is based on either default priority or programmable priority specified in the priority specification flag register (PR0).

  • Page 343: Example Of Handling An Interrupt Request When An Interrupt Is Already Being Handled

    µ PD78214 Sub-Series Fig. 12-11 Example of Handling an Interrupt Request When an Interrupt Is Already Being Handled (1/2) Vectored interrupt request a (low priority) Vectored interrupt request e (high priority) Main routine [Nesting 1] [Nesting 2] Processing a Processing b Macro service →...
  • Page 344 Fig. 12-11 Example of Handling an Interrupt Request When an Interrupt Is Already Being Handled (2/2) Main routine Vectored interrupt request i (low priority) Vectored interrupt request k (low priority) Vectored interrupt request m (low priority) Vectored interrupt request o (high priority) Vectored interrupt request q (high priority)

  • Page 345: Interrupt Request And Macro Service Pending

    µ PD78214 Sub-Series Fig. 12-12 Example of Handling Interrupts That Occur Simultaneously • Vectored interrupt request a (low priority) • Macro service request b (high priority) • Macro service request c (low priority) • Vectored interrupt request d (high priority) Default priority: a >...

  • Page 346: Interrupt And Macro Service Operation Timing

    Example of correct coding (2) • • • LOOP: BT IF0H.3, $NEXT Remark The BTCLR would be more convenient than the BR $LOOP ← NEXT: Interrupts or macro services will not be kept pending long, because they are processed after the BR is executed. •...

  • Page 347: Macro Service Processing Time

    µ PD78214 Sub-Series 3. “Peripheral RAM” corresponds to the internal RAM at addresses 0FC80H through 0FDFFH (for the µ PD78212, 0FD80H through 0FDFFH). 4. 1 clock = 1/f (167 ns at 12 MHz). (3) Macro service processing time The time required to process a macro service varies, depending on the type of the macro service, as listed in Table 12-6.

  • Page 348: Macro Service Function

    12.4 MACRO SERVICE FUNCTION 12.4.1 Macro Service Outline Macro service is one of the interrupt handling methods. When a vectored interrupt is processed, the contents of the program counter (PC) and the program status word (PSW) are saved in the stack and the PC is loaded with the vector address retrieved from the vector table.

  • Page 349: Macro Service Types

    µ PD78214 Sub-Series 12.4.2 Macro Service Types The macro service can be used by the 17 types of interrupts listed in Table 12-7 (of which, 15 types can use macro services simultaneously). In addition, three modes of operation are available, and each should be selected according to the application.

  • Page 350: Macro Service Basic Operation

    (3) Type C Transfers 1-byte data from memory to the real-time output port and the compare register for 8-bit timer/ counter 1 upon each interrupt request. When a specified number of data transfers are performed, a vectored interrupt request is generated. Type C macro service transfers data to two locations upon one interrupt request.

  • Page 351: Macro Service Control Register

    µ PD78214 Sub-Series 12.4.4 Macro Service Control Register (1) Macro service control word The macro service function of the µ PD78214 is controlled using the macro service mode registers and macro service channel pointers. The macro service mode registers specify the mode of macro service processing, and the macro service channel pointer specifies the address of a macro service channel to be used.

  • Page 352: Macro Service Type A

    (2) Macro service mode register A macro service mode register is an 8-bit register that specifies the mode of macro service operation. It is mapped in internal RAM as part of macro service control word (see Fig 12-16). Fig. 12-17 shows the format of the macro service mode register. Fig.

  • Page 353: Interrupt Requests That Can Specify Macro Service And Related Sfrs (Type A)

    µ PD78214 Sub-Series Table 12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A) Interrupt request specifying the type A macro service Caution When the external memory is expanded (or always with the µ PD78213), an illegal write access operation may occur during the type A macro service.

  • Page 354: Flow Of Data Transfer By Macro Service (Type A)

    Fig. 12-18 Flow of Data Transfer by Macro Service (Type A) Accepts macro service request Read contents of macro service mode register Other factors Identify channel type TYPE A Read channel pointer contents (m) Read MSC contents (n) Buffer address calculation m – n Identify transfer direction Memory→SFR Read contents of buffer and transfer read data...

  • Page 355: Type A Macro Service Channel

    µ PD78214 Sub-Series (2) Macro service channel configuration A channel pointer and a macro service counter (MSC) specify the addresses of transfer source and destination buffers in the internal RAM (at FE00H through FEFFH). (See Fig. 12-19.) The SFR to be accessed is predetermined for each interrupt request. (See Table 12-8.) Macro service channel Macro service control word (Macro service buffer address) = (Channel pointer) –...

  • Page 356: Type B Macro Service

    (3) Example of using the type A macro service The following example shows how data received through an asynchronous serial interface is transferred to a buffer area in the internal RAM. RXB/P30 12.4.6 Type B Macro Service (1) Operation The type B macro service transfers data between a data area in the memory specified by the macro service channel and an SFR.

  • Page 357: Flow Of Data Transfer By Macro Service (Type B)

    µ PD78214 Sub-Series Fig. 12-21 Flow of Data Transfer by Macro Service (Type B) Accepts macro service request Read contents of macro service mode register Identify channel type Read channel pointer contents (m) Identify transfer direction Select transfer source SFR by SFR pointer Read data from SFR and write it to the memory addressed by MP Increment MP...

  • Page 358: Type B Macro Service Channel

    (2) Macro service channel configuration The macro service pointer (MP) indicates a data buffer area in the 64K memory space as a transfer source or destination. The SFR pointer (SFRP) is set with the lower 8 bits of the address of an SFR used as a transfer source or destination.

  • Page 359: Parallel Data Input In Synchronization With An External Interrupt

    µ PD78214 Sub-Series (3) Example of using the type B macro service The following example shows how parallel data is input from port 3 in synchronization with an external signal. The external signal is input to the external interrupt pin (INTP4). Fig.

  • Page 360: Macro Service Type C

    12.4.7 Macro Service Type C (1) Operation The type C macro service controls 8-bit timer/counter 1 and the real-time output port simultaneously. This macro service transfers data to both the compare register for 8-bit timer/counter 1 and the buffer register for the real-time output port upon one interrupt request.

  • Page 361: Flow Of Data Transfer By Macro Service (Type C)

    µ PD78214 Sub-Series Fig. 12-25 Flow of Data Transfer by Macro Service (Type C) Accepts macro service request Read contents of macro service mode register Identify channel type Read channel pointer contents (m) Read memory addressed by MPT Automatic addition? Transfer data to compare register Retains MPT? Increment MPTL...
  • Page 362 Ring control? Decrement ring counter Ring counter = 0? Subtract modulo register contents from low-order 8-bits of macro service pointer for data (MPDL) and return pointer to the first address Reload modulo register contents to ring counter MSC←MSC – 1 MSC = 0? Vectored interrupt request occurs Chapter 12 Interrupt Functions...

  • Page 363: Type C Macro Service Channel

    µ PD78214 Sub-Series (2) Macro service channel configuration There are two types of type C macro service channels, as shown in Fig. 12-26. The timer macro service pointer (MPT) indicates a data buffer area in the 64K memory space from which data is transferred to, or added to the contents of, the compare register for 8-bit timer/counter 1.
  • Page 364 (b) With ring control Lower address Macro service counter ↑ (MSC) Ring counter (RC) Modulo register (MR) Data macro service pointer, low (MPDL) Data macro service pointer, high (MPDH) Timer macro service pointer, low (MPTL) Timer macro service pointer, high (MPTH) Mode register ↓...

  • Page 365: Open-Loop Control For A Stepper Motor By The Real-Time Output Port

    µ PD78214 Sub-Series (3) Example of using the type C macro service The following example shows a pattern output to the real-time output port and how the output interval is controlled directly. Update data is transferred from two data areas previously set in the 64K-byte space to the buffer registers (P0H and P0L) and compare registers (CR10 and CR11) for the real-time output port.

  • Page 366: Data Transfer Control Timing

    TM1 count value INTC10 timer interrupt Compare register (CR10) Buffer register (4) Example of using automatic addition control and ring control (a) Automatic addition control The automatic addition control function adds the output timing data (∆t) specified by a macro service pointer (MPT) to the contents of a compare register and writes the sum to the compare register.

  • Page 367: Four-Phase Stepping Motor With Phase 1 Excitation

    µ PD78214 Sub-Series Fig. 12-29 Four-Phase Stepping Motor with Phase 1 Excitation Phase A Phase B Phase C Phase D Fig. 12-30 Four-Phase Stepping Motor with Phases 1 and 2 Excitation Phase A Phase B Phase C Phase D 1 cycle (4 patterns) 1 cycle (8 patterns)
  • Page 368 Fig. 12-31 Block Diagram 1 for Automatic Addition Control Plus Ring Control (Constant-Speed Rotation with Phases 1 and 2 Excitation) 64K memory space 0B000 0B001 Output data (8 pieces) • • • • • • 0B007 • • • ∆t Output timing: 0B100 Addition Compare register...
  • Page 369 µ PD78214 Sub-Series Fig. 12-32 Timing Chart 1 for Automatic Addition Control Plus Ring Control (Constant-Speed Rotation with Phases 1 and 2 Excitation) TM1 count value ∆t Count starts INTC10 Compare register T0+∆t T1+∆t T2+∆t T3+∆t T4+∆t T5+∆t T6+∆t T7+∆t T8+∆t T9+∆t (CR10)
  • Page 370 Fig. 12-33 Block Diagram 2 for Automatic Addition Control Plus Ring Control (with the Output Timing Varied by Phase 2 Excitation) 64K memory space 0B000 0B001 Output data (4 pieces) • • • • • • 0B007 • • • ∆t0 Output timing: 0B100 ∆t1...
  • Page 371 µ PD78214 Sub-Series Fig. 12-34 Timing Chart 2 for Automatic Addition Control Plus Ring Control (with the Output Timing Varied by Phase 2 Excitation) ∆t7 ∆t6 ∆t5 ∆t4 ∆t3 TM1 count value ∆t2 ∆t1 ∆t9 ∆t8 Count starts INTC10 Compare register (CR10) T0+∆t1 T1+∆t2...

  • Page 372: Notes

    12.5 NOTES (1) Do not use the RETI instruction to return from the software interrupt. (2) A macro service request is accepted and processed even when a nonmaskable interrupt service program is running. To disable macro service processing during execution of the nonmaskable interrupt service program, cause the nonmaskable interrupt service program to manipulate the mask register so that no macro service will not occur.

  • Page 373: Illegal Write Access Conditions And Corresponding Operations

    µ PD78214 Sub-Series Example of correct coding (2) • • • LOOP: BT IF0H.3, $NEXT BR $LOOP NEXT: • • • (6) In addition, when you have to use a coding of the instructions listed in Section 12.3.5 consecutively, yet expect frequent occurrence of interrupts and macro services, insert NOP instructions in the coding to allow time during which interrupts and macro service are accepted.

  • Page 374: Chapter 13 Local Bus Interface Function

    CHAPTER 13 LOCAL BUS INTERFACE FUNCTION The local bus interface function is provided to connect external memories (ROM and RAM) and I/Os. External memories (ROM and RAM) and I/Os are accessed by using the RD, WR, and ASTB signals, a multiplexed address/data bus consisting of lines AD0 to AD7, and an address bus consisting of lines A8 to A19.

  • Page 375: Memory Expansion Mode Register (Mm)

    µ PD78214 Sub-Series 13.1 CONTROL REGISTERS 13.1.1 Memory Expansion Mode Register (MM) The MM register is an 8-bit register for controlling externally expanded memory, specifying the number of wait states (address space: 00000H to 0FFFFH), and controlling the internal fetch cycle. The MM register can be read and written with 8-bit manipulation instructions and bit manipulation instructions.

  • Page 376: Programmable Wait Control Register (Pw)

    13.2 MEMORY EXPANSION FUNCTION 13.2.1 External Memory Expansion Function The µ PD78214 allows additional 48384-byte memory (for the µ PD78212, 56704-byte memory) and I/Os to be connected according to the setting of the memory expansion mode register (MM). When the memory space is expanded externally, P50 to P57 function as an address bus, and P40 to P47 function as a multiplexed address/data bus.

  • Page 377: M-Byte Expansion Function

    Caution External devices cannot be mapped to the same addresses as those of the internal RAM area ( µ PD78213, µ PD78214, and µ PD78P214: 0FD00H to 0FEFFH, µ PD78212: 0FD80H to 0FEFFH) and SFR area (0FF00H to 0FFFFH, excluding the external SFR area (0FFD0H to 0FFDFH)).

  • Page 378: Accessing Expansion Data Memory

    Fig. 13-5 Accessing Expansion Data Memory Fetch cycle A16-A19 (output) A8-A15 Higher address (output) Lower Hi-Z Hi-Z Program AD0-AD7 address (output) ASTB (output) RD (output) Fetch cycle A16-A19 (output) A8-A15 Higher address (output) Lower Hi-Z Hi-Z Program AD0-AD7 address (input) (output) ASTB (output) RD (output)

  • Page 379: Memory Mapping With Expanded Memory

    µ PD78214 Sub-Series 13.2.3 Memory Mapping with Expanded Memory Figs. 13-6 to 13-9 show the memory maps when the memory has been expanded. Even when the memory has been expanded, external devices at the same addresses as those of the internal ROM area, internal RAM area, or SFR area (excluding the external SFR area (0FFD0H to 0FFDFH)) cannot be accessed.

  • Page 380: Data Memory Expansion For Μ Pd78212 (When Ea = L)

    Fig. 13-6 Data Memory Expansion for µ PD78212 (When EA = L) MM6 = 0 00000H External memory 0FD7FH 0FD80H Internal RAM 0FEFFH 0FF00H 0FFD0H External SFR area 0FFDFH 0FFFFH 10000H FFFFFH Chapter 13 Local Bus Interface Function MM6 = 1...

  • Page 381: Data Memory Expansion For Μ Pd78212 (When Ea = H)

    µ PD78214 Sub-Series Fig. 13-7 Data Memory Expansion for µ PD78212 (When EA = H) MM2, MM1, MM0 = 0, 0, 0 or 0, 0, 1 MM6 = 0 00000H Internal ROM 01FFFH 02000H 0FD7FH 0FD80H Internal RAM 0FEFFH 0FF00H...

  • Page 382: Data Memory Expansion For Μ Pd78213 And Μ Pd78214 (When Ea = L)

    Fig. 13-8 Data Memory Expansion for µ PD78213 and µ PD78214 (When EA = L) MM6 = 0 00000H External memory 0FCFFH 0FD00H Internal RAM 0FEFFH 0FF00H 0FFD0H External SFR area 0FFDFH 0FFFFH Chapter 13 Local Bus Interface Function MM6 = 1 External memory Internal RAM External SFR area...

  • Page 383: Data Memory Expansion For Μ Pd78214 And Μ Pd78P214 (When Ea = H)

    µ PD78214 Sub-Series Fig. 13-9 Data Memory Expansion for µ PD78214 and µ PD78P214 (When EA = H) MM2, MM1, MM0 = 0, 0, 0 or 0, 0, 1 MM6 = 0 00000H Internal ROM 03FFFH 04000H 0FCFFH 0FD00H Internal RAM 0FEFFH 0FF00H 0FFD0H...

  • Page 384: Example Of Connecting Memories

    µ PD43256AC-15, can be used as RAM in place of the µ PD43256AC-12. Chapter 13 Local Bus Interface Function : 0000H-FCFFH ( µ PD78213) 2000H-0FD7FH ( µ PD78212) 4000H-FCFFH ( µ PD78214) FFD0H-FFDFH as an external SFR area : 10000H-17FFFH...

  • Page 385: Example Of Connecting Memories To Μ Pd78214

    µ PD78214 Sub-Series Fig. 13-10 Example of Connecting Memories to µ PD78214 74HC04 µ PD78214 74HC375 ST ST A8-A14 ASTB AD0-AD7 Remark Pull-up resistors must be connected to the address and address/data bus lines. 74HC32 74HC138 74HC573 Q0-Q7 D0-D7 µ PD23C4000A WORD/BYTE O0-O7...

  • Page 386: Internal Rom High-Speed Fetch Function

    13.3 INTERNAL ROM HIGH-SPEED FETCH FUNCTION The µ PD78212, µ PD78214, and µ PD78P214 contain an internal ROM. The internal ROM can be accessed quickly without having to use the bus control circuit. Usually, internal ROM is fetched at the same speed as external ROM.

  • Page 387: Wait Control Space Of Μ Pd78212 (When Ea = L)

    µ PD78214 Sub-Series Fig. 13-11 Wait Control Space of µ PD78212 (When EA = L) FFFFFH 10000H 0FFFFH 0FFDFH 0FFD0H 0FF00H 0FEFFH 0FD80H 0FD7FH 00000H Space subject Expansion data to wait control memory by PW register External SFR area Internal RAM...

  • Page 388: Wait Control Space Of Μ Pd78212 (When Ea = H)

    Fig. 13-12 Wait Control Space of µ PD78212 (When EA = H) Expansion data memory 10000H 0FFFFH 0FFDFH External SFR area 0FFD0H 0FF00H 0FEFFH Internal RAM 0FD80H 0FD7FH External memory 02000H 01FFFH Internal ROM 00000H Chapter 13 Local Bus Interface Function...

  • Page 389: Wait Control Space Of Μ Pd78213 And Μ Pd78214 (When Ea = L)

    µ PD78214 Sub-Series Fig. 13-13 Wait Control Space of µ PD78213 and µ PD78214 (When EA = L) FFFFFH 10000H 0FFFFH 0FFDFH 0FFD0H 0FF00H 0FEFFH 0FD00H 0FCFFH 00000H Space subject Expansion data to wait control memory by PW register External SFR area Internal RAM Space subject to wait control...

  • Page 390: Wait Control Space Of Μ Pd78214 And Μ Pd78P214

    Fig. 13-14 Wait Control Space of µ PD78214 and µ PD78P214 FFFFFH Expansion data memory 10000H 0FFFFH 0FFDFH External SFR area 0FFD0H 0FF00H 0FEFFH Internal RAM 0FD00H 0FCFFH External memory 04000H 03FFFH Internal ROM 00000H Chapter 13 Local Bus Interface Function Space subject to wait control by PW register...

  • Page 391: Read Timing Of Programmable Wait Function

    µ PD78214 Sub-Series Fig. 13-15 Read Timing of Programmable Wait Function (1/2) (a) When zero wait states are set Note A8-A15 Higher address (output) Lower Hi-Z Hi-Z Hi-Z address Data (input) AD0-AD7 (output) ASTB (output) RD (output) (b) When one wait state is set Note A8-A15 Higher address...
  • Page 392 Chapter 13 Local Bus Interface Function Fig. 13-15 Read Timing of Programmable Wait Function (2/2) (c) When two wait states are set Note A8-A15 Higher address (output) Lower Hi-Z Hi-Z address Data (input) AD0-AD7 (output) ASTB (output) RD (output) Note f : System clock frequency (f...

  • Page 393: Write Timing Of Programmable Wait Function

    µ PD78214 Sub-Series Fig. 13-16 Write Timing of Programmable Wait Function (1/2) Note A8-A15 (output) AD0-AD7 (output) ASTB (output) WR (output) Note A8-A15 (output) Hi-Z AD0-AD7 (output) ASTB (output) WR (output) (a) When zero wait states are set Higher address Hi-Z Hi-Z Lower...
  • Page 394 Fig. 13-16 Write Timing of Programmable Wait Function (2/2) (c) When two wait states are set Note A8-A15 (output) Hi-Z Hi-Z Lower AD0-AD7 address (output) ASTB (output) WR (output) Note f : System clock frequency (f Chapter 13 Local Bus Interface Function Higher address Data Hi-Z...

  • Page 395: Timing When External Wait Signal Is Used

    µ PD78214 Sub-Series Fig. 13-17 Timing When External Wait Signal Is Used Note A8-A15 (output) Lower address AD0-AD7 (output) ASTB (output) RD (output) WAIT (input) Note A8-A15 (output) Lower AD0-AD7 address (output) ASTB (output) WR (output) WAIT (input) Note f : System clock frequency (f (a) Read timing Higher address...

  • Page 396: Pseudo Static Ram Refresh Function

    13.5 PSEUDO STATIC RAM REFRESH FUNCTION 13.5.1 Function The µ PD78214 provides the pseudo static RAM refresh function to enable pseudo static RAM to be connected directly. The pseudo static RAM refresh function outputs refresh pulses at arbitrary intervals. The refresh pulse output cycle period is specified in the refresh mode register (RFM), and the external access cycle is changed to the refresh bus cycle that matches the pseudo static RAM bus cycle.

  • Page 397: Pulse Refresh When Internal Memory Is Accessed

    µ PD78214 Sub-Series 13.5.3 Operation (1) Pulse refresh operation To support the pulse refresh cycle of pseudo static RAM, the REFRQ pin outputs refresh pulses, synchronized with the bus cycle. Adjust the oscillator frequency and bits 1 and 0 (RFT1 and RFT0) of the refresh mode register (RFM) so that at least 512 refresh pulses are output in 8 ms.

  • Page 398: Pulse Refresh When External Memory Is Accessed

    (b) Accessing External Memory The refresh bus cycle is generated at the intervals specified with the refresh mode register (RFM). Pseudo static RAM may malfunction if the access timing overlaps the refresh pulse output timing; therefore, the µ PD78214 generates a refresh bus cycle of three clock pulses, synchronized with the bus cycle.

  • Page 399: Restoration Timing From Self-Refresh

    µ PD78214 Sub-Series (2) Self-refresh Self-refresh is performed to retain the contents of pseudo static RAM when in standby mode. (a) Setting self-refresh mode When bit 4 (RFEN) of the RFM register is set to 1, and bit 7 (RFLV) is set to 0, pin REFRQ outputs a low-level signal, requesting pseudo static RAM to enter self-refresh mode.

  • Page 400: Return From Self-Refresh

    Caution If the RFEN bit of the refresh mode register (RFM) is already set to 1 (or is simultaneously set to 1) when the RFLV bit is changed from 0 to 1, pin REFRQ may output a glitch, having a peak level of approximately 2.6 V, for approximately 10 ns. When setting the RFLV bit to 1, follow the steps shown in Fig.

  • Page 401: Example Of Connecting Pseudo Static Ram

    (2) External devices cannot be mapped onto the same addresses as those of the internal RAM area ( µ PD78213, µ PD78214, and µ PD78P214: 0FD00H to 0FEFFH, µ PD78212: 0FD80H to 0FEFFH) and SFR area (0FF00H to 0FFFFH, excluding the external SFR area (0FF00H to 0FFDFH)).

  • Page 402: Conditions And Operations For Illegal Write Access

    (3) When macro service Type A or Type C is used in external memory expansion mode (the µ PD78213 always uses external memory), an illegal write access may occur. This occurs when any of the following three conditions is satisfied: (a) Data is transferred from memory to an SFR using macro service Type A, and the transfer data is D0H to DFH.

  • Page 403: Glitch Observed On Pins A16 To A19 During Emulation

    µ PD78214 Sub-Series (6) When using the in-circuit emulator, note the following points: • When the RD signal or WR signal is active, a glitch may occur on pins A16 to A19. Fig. 13-25 Glitch Observed on Pins A16 to A19 during Emulation An (n = 16 -19) RD or WR signal •...

  • Page 404: Preventing Problems That May Occur During Emulation

    Fig. 13-27 Preventing Problems That May Occur during Emulation Target probe ASTB Chapter 13 Local Bus Interface Function 74HC375 To target circuit...

  • Page 406: Function Overview

    14.1 FUNCTION OVERVIEW The µ PD78214 supports a standby function to reduce the system’s power consumption. With the standby function, two modes are available: • HALT mode: In this mode, only the CPU clock is stopped. Intermittent operation, when combined with normal operating mode, can reduce overall system power consumption.
  • Page 407 µ PD78214 Sub-Series...

  • Page 408: Standby Control Register (Stbc)

    14.2 STANDBY CONTROL REGISTER (STBC) The standby control register (STBC) is an 8-bit register which controls standby mode. The STBC register can be both read and written. Only a specified instruction (MOV STBC, #byte), however, can be used for writing to the register, to prevent the application system stopping unintentionally as a result of a program crash.

  • Page 409: Releasing Halt Mode

    µ PD78214 Sub-Series 14.3.2 Releasing HALT Mode HALT mode can be released by any of the following three sources: • Nonmaskable interrupt request (NMI) • Maskable interrupt request (vectored interrupt or macro service) • RESET input Table 14-2 lists the sources used for releasing HALT mode and the operations that are performed after HALT mode is released by each source.

  • Page 410: Release Of Halt Mode By A Maskable Interrupt Request

    (2) Release by a maskable interrupt request Only maskable interrupts with 0 in the interrupt mask flag can be used to release HALT mode. If the interrupt priority status flag (ISP) is set to 0 (only high-priority interrupts are enabled), only interrupts with 0 in the priority designation flag (high priority) can release HALT mode.

  • Page 411: Stop Mode

    µ PD78214 Sub-Series 14.4 STOP MODE 14.4.1 Specifying STOP Mode and Operation States in STOP Mode The system enters STOP mode when the STP bit of the STBC register is set to 1. The STBC register can be written only with a specified 8-bit data write instruction. To specify STOP mode, execute the “MOV STBC, #02H”...

  • Page 412: Releasing Stop Mode With An Nmi Signal

    Fig. 14-4 Releasing STOP Mode with an NMI Signal Oscillator STP flip-flop 1 STP flip-flop 2 NMI input (effective at rising edge) Caution If another effective edge of the NMI signal is detected during the oscillation settling time, the oscillation settling time counter is cleared and restarts counting, resulting in a longer wait time than usual.

  • Page 413: Notes On Using Stop Mode

    µ PD78214 Sub-Series 14.4.3 Notes on Using STOP Mode Check the following items to ensure that current consumption is appropriately reduced in STOP mode: (1) Is the output level of each output pin appropriate? The appropriate output level of each pin depends on the circuit of the next stage. Select an output level that minimizes current consumption.

  • Page 414: Example Of Address Bus Arrangement

    Fig. 14-6 Example of Address Bus Arrangement Power supply backed up µ PD78214 (n = 8 to 15) The outputs of the address/data bus pins are high-impedance in STOP mode. The address/data bus pins are usually pulled up with pull-up resistors. If a pull-up resistor is connected to a power supply which is backed up, current flows through the pull-up resistor to an external circuit that is connected to a power supply that is not backed up, if the circuit has low input impedance.

  • Page 415: Example Arrangement For Analog Input Pin

    µ PD78214 Sub-Series Fig. 14-8 Example Arrangement for Analog Input Pin Signal source The voltage input to the AN0 to AN7 pins must be maintained at a level between V falling outside this range increases the current consumption as well as adversely affecting the reliability of the microcomputer.

  • Page 416: Example Of Longer Oscillation Settling Time

    Fig. 14-9 Example of Longer Oscillation Settling Time (effective at falling edge) CPU operation STOP mode Count value of oscillation settling time counter Chapter 14 Standby Function Wait for oscillation to settle Normal operation Cleared by effctive edge Oscillation settling time is extended by this period.

  • Page 418: Reset Function

    15.1 RESET FUNCTION When the signal applied to the RESET input pin is low, the system is reset, and each hardware component is set to the state indicated in Table 15-2. All pins, except the power supply pin, assume the high-impedance state. Table 15-1 lists the states of pins during reset and after the reset state is released.

  • Page 419: Pin States During Reset And After Reset State Is Released

    µ PD78214 Sub-Series Table 15-1 Pin States during Reset and After Reset State Is Released Pin name P00-P07 P20/NMI-27/SI P30/RxD-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD, P65/WR P66/WAIT/AN6, P67/REFRQ/AN7 P70/AN0-P75/AN5 ASTB Note When ROM-less mode is specified (EA pin = 0), these pins function as an address/data bus and output signals for fetching the reset vector address from address 0000H (see Fig.

  • Page 420: Hardware States After Reset

    Table 15-2 Hardware States after Reset (1/2) Hardware Program counter (PC) Stack pointer (SP) Program status word (PSW) Data memory Built-in General registers (X, A, C, B, E, D, L, H) Ports Port 0, 2, 3, 4, 5, and 7 Port 6 Port mode registers PM0, PM3, PM5...
  • Page 421 µ PD78214 Sub-Series Hardware Serial Mode register (CSIM) interface Shift register (SIO) Asynchronous mode register (ASIM) Asynchronous status register (ASIS) Serial bus control register (SBIC) Serial reception buffer (RXB) Serial transmission buffer (TXS) Baud rate generator control register (BRGC) Real-time output port control register (RTPC) Programmable wait control register (PW) Refresh mode register (RFM) Interrupts...

  • Page 422: Timing Charts For Reset Operation

    Fig. 15-3 Timing Charts for Reset Operation RESET (input) ASTB (output) A8-A19 (output) AD0-AD7 RD (output) WR output Other I/O ports RESET (input) ASTB (output) P60-P63 (output) Other I/O ports 15.2 NOTE When resetting the system at power-on, do not set the RESET signal high immediately after the supply voltage reaches the specified level.

  • Page 424: Chapter 16 Application Examples

    CHAPTER 16 APPLICATION EXAMPLES 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS This section provides an example of controlling stepper motors with the real-time output function, 8-bit timer/ counter 1, and the macro service function of the µ PD78214. Fig. 16-1 shows the functional blocks for controlling two stepper motors. An interrupt signal is generated when the value in 8-bit timer/counter 1 (TM1) is matched with the value in compare register CR10 or CR11.
  • Page 425 µ PD78214 Sub-Series...

  • Page 426: Serial Communication With Multiple Devices

    16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES Fig. 16-2 shows an example of a system configured with a serial bus interface. The serial bus interface can transfer addresses (for selecting devices), commands, and data, as well as acknowledge and busy signals, using only two lines: The serial clock and serial bus lines.

  • Page 427: Example Of Communication With Sbi

    µ PD78214 Sub-Series Fig. 16-3 Example of Communication with SBI Address Address Address Address Address : Bus release : Command trigger Selection of slave CPU (a feature of SBI) Address transfer Command transfer Data transfer Command Command Command Data Command Data Data Data...

  • Page 428: Chapter 17 Programming For The Μ Pd78P214

    CHAPTER 17 PROGRAMMING FOR THE µ PD78P214 The µ PD78P214 employs an electrically writable PROM of 16384 × 8 bits for program memory. Use the NMI and RESET pins to set the µ PD78P214 to PROM programming mode when programming the PROM. The µ...

  • Page 429: Timing Chart For Prom Write And Verify

    µ PD78214 Sub-Series Fig. 17-1 Timing Chart for PROM Write and Verify A0-A14 Hi-Z Data input D0-D7 +12.5 V +6 V CE (input) OE (input) Repetition of X times Write Verify Address input Hi-Z Data output Additional write Hi-Z Hi-Z Data input 3X ms...

  • Page 430: Procedure For Reading From Prom

    Write failure (up to 24th) < Last address 17.3 PROCEDURE FOR READING FROM PROM The contents of PROM can be read out to the external data bus (D0 to D7) by following the procedure below: (1) Fix the RESET pin to the low level. Apply +12.5 V to pin NMI. Handle unused pins as described in Section 1.3.2. (2) Apply +5 V to the V and V (3) Input the address of the data to be read into the A0 to A14 pins.

  • Page 431: Prom Read Timing Chart

    µ PD78214 Sub-Series Fig. 17-3 PROM Read Timing Chart Address input A0-A14 CE (input) OE (input) Hi-Z Hi-Z Data output D0-D7 17.4 NOTE When V is +12.5 V and V is +6 V, CE and OE must not be set to low at the same time.

  • Page 432: Chapter 18 Instruction Operations

    CHAPTER 18 INSTRUCTION OPERATIONS This chapter describes the operation of each instruction of the µ PD78214 sub-series. Refer to the 78K/II Series User’s Manual, Instructions (IEU-1311) for details of each operation, the corresponding machine language code (instruction code), and the number of clock states for each instruction. 18.1 LEGEND 18.1.1 Operand Field Code operands in the operand field for each instruction, using the specified operand representation format (for...

  • Page 433: Operation Field

    µ PD78214 Sub-Series saddr, saddr’ : Memory address indicated in short direct addressing mode; FE20H-FF1FH immediate data or label saddrp : Memory address indicated in short direct addressing pair mode; FE20H-FF1EH immediate data or label addr16 : 16-bit address; 0000H-FEFFH immediate data or label addr11 : 11-bit address;...

  • Page 434: Flag Field

    : Zero flag RBS1-RBS0 : Register bank selection flag : Interrupt request enable flag STBC : Standby control register jdisp8 : Signed 8-bit data (displacement: –128 to +127) : Contents at address enclosed in parentheses or at address indicated in register enclosed in parentheses ××H : Hexadecimal number...

  • Page 435: List Of Operations

    µ PD78214 Sub-Series 18.2 LIST OF OPERATIONS (1) 8-bit data transfer instructions: MOV, XCH Mnemonic Operand r, #byte saddr, #byte sfr, #byte r, r' A, r A, saddr saddr, A saddr, saddr A, sfr sfr, A A, mem A, & mem mem, A &...
  • Page 436 (2) 16-bit data transfer instructions: MOVW Mnemonic Operand MOVW rp, #word saddrp, #word sfrp, #word rp, rp' AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, mem1 AX, & mem1 mem1, AX & mem1, AX (3) 8-bit arithmetic/logical instructions: ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP Mnemonic Operand A, #byte...
  • Page 437 µ PD78214 Sub-Series Mnemonic Operand A, #byte saddr, #byte sfr, #byte r, r' A, saddr A, sfr saddr, saddr' A, mem A, & mem SUBC A, #byte saddr, #byte sfr, #byte r, r' A, saddr A, sfr saddr, saddr' A, mem A, &...
  • Page 438 Mnemonic Operand A, #byte saddr, #byte sfr, #byte r, r' A, saddr A, sfr saddr, saddr' A, mem A, & mem A, #byte saddr, #byte sfr, #byte r, r' A, saddr A, sfr saddr, saddr' A, mem A, & mem (4) 16-bit arithmetic/logical instructions: ADDW, SUBW, CMPW Mnemonic Operand...
  • Page 439 µ PD78214 Sub-Series (5) Multiply/divide instructions: MULU, DIVUW Mnemonic Operand MULU DIVUW (6) Increment/decrement instructions: INC, DEC, INCW, DECW Mnemonic Operand saddr saddr INCW DECW (7) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4 Mnemonic Operand r, n r, n RORC...
  • Page 440 (8) BCD conversion instructions: ADJBA, ADJBS Mnemonic Operand ADJBA ADJBS (9) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1 Mnemonic Operand MOV1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, X.bit CY, PSW.bit saddr.bit, CY sfr.bit, CY A.bit, CY X.bit, CY PSW.bit, CY AND1...
  • Page 441 µ PD78214 Sub-Series Mnemonic Operand XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, X.bit CY, PSW.bit SET1 saddr.bit sfr.bit A.bit X.bit PSW.bit CLR1 saddr.bit sfr.bit A.bit X.bit PSW.bit NOT1 saddr.bit sfr.bit A.bit X.bit PSW.bit No. of Operation bytes CY ← CY ∨ (saddr.bit) CY ←...
  • Page 442 (10) Call/return instructions: CALL, CALLF, CALLT, BRK, RET, RETI, RETB Mnemonic Operand CALL !addr16 CALLF !addr11 CALLT [addr5] RETI RETB (11) Stack manipulation instructions: PUSH, POP, MOVW, INCW, DECW Mnemonic Operand PUSH MOVW SP, #word SP, AX AX, SP INCW DECW (12) Unconditional branch instruction: BR Mnemonic...
  • Page 443 µ PD78214 Sub-Series (13) Conditional branch instructions: BC, BL, BNC, BNL, BZ, BE, BNZ, BNE, BT, BF, BTCLR, DBNZ Mnemonic Operand $ addr16 addr16 $ addr16 $ addr16 saddr.bit, $ addr16 sfr.bit, $ addr16 A.bit, $ addr16 X.bit, $ addr16 PSW.bit, $ addr16 saddr.bit, $ addr16 sfr.bit, $ addr16...
  • Page 444 (14) CPU control instructions: MOV, SEL, NOP, EI, DI Mnemonic Operand STBC, #byte Chapter 18 Instruction Operations No. of Operation bytes STBC ← byte RBS1 – 0 ← n, n = 0 – 3 No operation IE ← 1 (Enable interrupts) IE ←...

  • Page 445: Instruction Lists For Each Addressing Type

    µ PD78214 Sub-Series 18.3 INSTRUCTION LISTS FOR EACH ADDRESSING TYPE (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, and DBNZ Table 18-1 8-Bit Instructions for Each Addressing Type Second operand First...

  • Page 446: Bit Instructions For Each Addressing Type

    (2) 16-bit instructions MOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, and SHLW Table 18-2 16-Bit Instructions for Each Addressing Type Second operand # word First operand ADDW SUBW CMPW MOVW saddrp MOVW MOVW sfrp MOVW MOVW mem1 MOVW & mem1 MOVW MOVW saddrp...

  • Page 447: Bit Manipulation Instructions For Each Addressing Type

    µ PD78214 Sub-Series (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, and BTCLR Table 18-3 Bit Manipulation Instructions for Each Addressing Type Second operand First A. bit operand MOV1 AND1 XOR1 A. bit MOV1 X. bit MOV1 saddr.

  • Page 448: Call Instructions And Branch Instructions For Each Addressing Type

    (4) Call instructions and branch instructions CALL, CALLF, CALLT, BR, BC, BT, BF, BTCLR, DBNZ, BL, BNC, BNL, BZ, BE, BNZ, and BNE Table 18-4 Call Instructions and Branch Instructions for Each Addressing Type Instruction addressing operand Basic instruction Composite instruction Note BL, BNC, BNL, BZ, BF, BNZ, and BNE are the same as BC.

  • Page 450: Appendix A 78K/Ii Series Product List

    APPENDIX A 78K/II SERIES PRODUCT LIST The following pages list the 78K/II series products. For details, refer to each User’s Manual.
  • Page 451 4-bit output port 4-bit I/O port Note The ancillary function pins are included in the I/O pins. µ PD78214 Sub-Series µ PD78214 µ PD78212 µ PD78213 ( µ PD78P214) 65 (instructions common to all 78K/II series products) 333 ns 500 ns 333 ns Other than µ...
  • Page 452 µ PD78234 Sub-Series µ PD78233 µ PD78234 µ PD78237 ( µ PD78P238) 65 (instructions common to all 78K/II series products) 500 ns 333 ns 500 ns When the stack area is configured in the internal dual-port RAM: 6 Other cases: 8 = +5 V ±10% –40 to +85˚C, V 8 bits ×...
  • Page 453 BRG timer Baud rate generator External baud rate clock input Real-time output port µ PD78214 Sub-Series µ PD78214 µ PD78212 µ PD78213 ( µ PD78P214) None 8 bits × 8 Selected according to operating frequency 3.4 V to V Pins selected by bits ANI0 to ANI2 of the ADM register.
  • Page 454 µ PD78234 Sub-Series µ PD78238 µ PD78233 µ PD78234 µ PD78237 ( µ PD78P238) 12 bits × 2 None 8 bits × 8 Selected freely 3.4 V to V Pins subject to A/D conversion. Pin voltage is 0 V to AV conversion.
  • Page 455 • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic shrink • 68-pin plastic QFJ (except µ PD78212) • 64-pin plastic QFP • 64-pin plastic QFP (14 × 14 mm) • 74-pin plastic QFP (20 × 20 mm) •...
  • Page 456 µ PD78234 Sub-Series µ PD78238 µ PD78233 µ PD78234 µ PD78237 ( µ PD78P238) 2 levels (programmable), vector/macro service 8/16 bits selectable (except type A) Increments 16 bits Occurs when transferred data is D0H to DFH Depends on mode. Refer to the relevant user's manual. HALT/STOP mode Selected from two options Provided (refresh pulse width: 1/f...

  • Page 458: Appendix B Development Tools

    APPENDIX B DEVELOPMENT TOOLS The development tools described on the following pages are available for the development of systems using µ PD78214 sub-series.
  • Page 459 µ PD78214 Sub-Series...

  • Page 460: B.1 Hardware

    Note 2 EP-78210L Notes 1. µ PD78212, µ PD78213, µ PD78214, µ PD78P214, µ PD78212(A), µ PD78213(A), and µ PD78214(A) 2. These products are no longer produced and are not available from NEC. The IE-78240-R-A is an enhanced version of the IE-78210-R and IE-78240-R.
  • Page 461 µ PD78214 Sub-Series HARDWARE (2/2) EV-9200G-74 EV-9200GC-64 PG-1500 PA-78P214CW PA-78P214GC PA-78P214GJ PA-78P214GQ PA-78P214L Remarks 1. The EP-78210GC, EP-78210GJ, EP-78240GC-R, and EP-78240GJ-R are provided with one EV-9200G-74 or EV-9200GC-64. 2. The EV-9200G-74 and EV-9200GC-64 are supplied in batches of five. This socket is mounted on the board of the user system developed for the 74- pin QFP.

  • Page 462: B.2 Software

    B.2 SOFTWARE B.2.1 Language Processing Software (1/3) 78K/II series relocatable This relocatable assembler can be used for all the 78K/II series products. Its macro assembler (RA78K/II) functions enhance efficiency in software development. It also includes a struc- tured assembler, which makes the program control structure more comprehensive, thus improving software productivity and maintainability.
  • Page 463 µ PD78214 Sub-Series Language Processing Software (2/3) 78K/II series relocatable assembler (RA78K/II) 78K/II series C compiler (CC78K/II) Notes 1. The 8-inch 2D model has been superseded by the 5.25-inch 2HD and 3.5-inch 2HD models. Those users who have already purchased an 8-inch 2D model will be supplied with a 5.25-inch 2HC model when the product is next upgraded.

  • Page 464: B.2.2 Software For The In-Circuit Emulator

    Language Processing Software (3/3) 78K/II series C compiler This source program is used to modify the libraries supplied with CC78K/II to satisfy user specifications. library source file PC-9800 series IBM PC/AT or compatible HP9000 series300 SPARCstation EWS-4800 series (RISC) Note Versions 5.00 and 5.00A feature a task swap function.
  • Page 465 µ PD78214 Sub-Series Software for the In-Circuit Emulator (2/2) In-circuit emulator control program Note 1 IE78210 IE78240 Notes 1. When using the IE-78210-R or IE-78210-R-EM, the IE-78210 is also necessary. For the IE-78240-R or IE-78240-R- EM, the IE-78240 is necessary. When using the IE-78210-R together with the IE-78240-R-EM, the IE-78210 is necessary.

  • Page 466: B.2.3 Software For The Prom Programmer

    B.2.3 Software for the PROM Programmer PG-1500 controller This program provides the serial and parallel interfaces between PG-1500 and the host machine, enabling the host machine to control the PG-1500. PC-9800 series IBM PC/AT or compatible Notes 1. Versions 5.00 and 5.00A feature a task swap function. However, the task swap function cannot be used with this software.

  • Page 467: B.3 Upgrading Other In-Circuit Emulators To 78K/Ii Series Level

    Note 1 IE-78600-R Notes 1. This product is no longer produced, and is not available from NEC. 2. This board is used for emulation for the µ PD78214 series. Those users who already have the IE-78210-R-EM do not have to purchase this board.

  • Page 468: B.3.2 Upgrading To Ie-78240-R Level

    IE-78140-R IE-78230-R-A Notes 1. This product is no longer produced, and is not available from NEC. 2. This board is used for emulation for the µ PD78214 series. Those users who already have the IE-78210-R-EM do not have to purchase this board.

  • Page 469: B.3.3 Upgrading To Ie-78210-R Level

    IE-78350-R IE-78600-R Notes 1. This board is no longer produced, and is not available from NEC. Those users who do not have the IE-78210-R-EM, are recommended to upgrade to the IE-78240-R-A level, which includes the functions of IE-78240-R. 2. This product is no longer produced, and is not available from NEC.

  • Page 470: Appendix C Software For Embedded Applications

    APPENDIX C SOFTWARE FOR EMBEDDED APPLICATIONS C.1 FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM Fuzzy knowledge-data Supports input and editing, as well as the evaluation (simulation) of fuzzy knowl- creation tool edge-data (fuzzy rules and membership functions). PC-9800 series IBM PC/AT or compatible Translator This program converts fuzzy knowledge-data, obtained with the fuzzy knowledge...

  • Page 472: Appendix D Register Index

    APPENDIX D REGISTER INDEX D.1 REGISTER INDEX 16-bit capture register (CR02) ... 111 16-bit compare register (CR00,CR01) ... 111 16-bit timer 0 (TM0) ... 111 8-bit capture/compare register (CR11) ... 142 8-bit capture register (CR22) ... 161 8-bit compare register (CR10) ... 142 8-bit compare register (CR20) ...
  • Page 473 µ PD78214 Sub-Series Port 3 (P3) ... 66 Port 4 (P4) ... 75 Port 5 (P5) ... 80 Port 6 (P6) ... 84 Port 7 (P7) ... 92 Port 0 buffer register (P0L, P0H) ... 97 Port 0 mode register (PM0) ... 61 Port 3 mode control register (PMC3) ...

  • Page 474: D.2 Register Symbol Index

    D.2 REGISTER SYMBOL INDEX ADCR: A/D conversion result register ... 227 ADM: A/D converter mode register ... 229, 304 ASIM: Asynchronous serial interface mode register ... 245 ASIS: Asynchronous serial interface status register ... 246 BRGC: Baud rate generator control register ... 251 CR00: 16-bit compare register ...
  • Page 475 µ PD78214 Sub-Series PM0: Port 0 mode register ... 61 PM3: Port 3 mode register ... 72 PM5: Port 5 mode register ... 80 PM6: Port 6 mode register ... 89 PMC3: Port 3 mode control register ... 72 PR0: Priority specification flag register ...

  • Page 476: Appendix E Index

    E.1 INDEX 0 parity ... 247, 248 16-bit timer 0 ... 111, 114 16-bit timer/counter ... 109 1M-byte expansion function ... 348 4-bit counter ... 251 4-bit separate real-time output port ... 97 64-pin ceramic shrink DIP with window ... 6 64-pin plastic QFP ...
  • Page 477 µ PD78214 Sub-Series Clock synchronous serial interface mode register ... 262, 273 Command ... 279 Command detection flag ... 274 Command signal ... 278 Command trigger bit ... 274 Compare operation ... 117, 148, 176, 210 Compare register ... 111, 161, 142, 148, 206 Controlling multiple-interrupt handling ...
  • Page 478 Interrupt status register ... 304, 307 Interval timer ... 129, 151, 190, 192, 210, 211 Interval ... 109, 139, 159, 205 Local bus interface function ... 345 Loop counter ... 49 Macro service ... 301, 319 Macro service channel ... 321, 326, 329 Macro service channel pointer ...
  • Page 479 µ PD78214 Sub-Series Port 3 mode control register ... 72 Port 3 mode register ... 71 Port 4 ... 75 Port 5 ... 80 Port 5 mode register ... 80 Port 6 ... 84 Port 6 mode register ... 89 Port 7 ...
  • Page 480 Special function register ... 43, 50 Specifying 1M-byte expansion mode ... 346 Specifying the operation of the capture/compare register ... 144 Stack pointer ... 46 Standby control register ... 379 Standby function ... 377 Standby mode ... 377 Start bit ... 247 Stop bit ...

  • Page 481: E.2 Symbol Index

    µ PD78214 Sub-Series E.2 SYMBOL INDEX A ... 48 A0 ... 31 A1 ... 31 A2 ... 31 A3 ... 31 A4 ... 31 A5 ... 31 A6 ... 31 A7 ... 31 A8 ... 29, 31, 345 A9 ... 29, 31, 345 A10 ...
  • Page 482 CE2 ... 163, 167 CE3 ... 207, 208 CHT0 ... 323 CHT1 ... 323 CHT2 ... 323 CI ... 28, 161, 170 CIF00 ... 305 CIF01 ... 305 CIF10 ... 305 CIF11 ... 305 CIF20 ... 305 CIF21 ... 305 CISM00 ...
  • Page 483 µ PD78214 Sub-Series ES00 ... 294 ES01 ... 294 ES10 ... 294 ES11 ... 294 ES20 ... 294 ES21 ... 294 ES30 ... 295 ES31 ... 295 ES40 ... 295, 303 ES41 ... 295, 303 ES50 ... 295 ES51 ... 295 ESNMI ...
  • Page 484 µ PD78210 ... 20 µ PD78212 ... 1 µ PD78213 ... 1 µ PD78214 ... 1 µ PD78p214 ... 1, 399 NC ... 31, 32 NMI ... 428, 302, 303 NMIS ... 307 OE ... 31 OVE ... 247 OVF0 ... 112 OVF1 ...
  • Page 485 µ PD78214 Sub-Series PRS2 ... 207 PRS3 ... 207 PRS10 ... 144 PRS11 ... 144 PRS12 ... 144 PRS20 ... 164 PRS21 ... 164 PRS22 ... 164 PRS23 ... 164 PS0 ... 246 PS1 ... 246 PSW ... 45, 304, 308 PUO ...
  • Page 486 SO ... 29, 265 SO pin ... 267 SO latch ... 261 SP ... 46 Specifying HALT mode ... 379 Specifying STOP mode ... 382 SRIF ... 305 SRISM ... 306 SRMK ... 306 SRPR ... 307 STBC ... 379 STIF ...

This manual is also suitable for:

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