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NEC PD78076 User Manual

Pd78078 series; pd78078y series 8-bit single-chip microcontrollers
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User's Manual
PD78078, 78078Y Subseries
8-bit Single-chip Microcontrollers
PD78076
PD78078
PD78P078
PD78076Y
PD78078Y
PD78P078Y
Document No. U10641EJ4V0UM00 (4th edition)
Date Published December 1997 N
©
1994
Printed in Japan

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Summary of Contents for NEC PD78076

  • Page 1 User’s Manual PD78078, 78078Y Subseries 8-bit Single-chip Microcontrollers PD78076 PD78078 PD78P078 PD78076Y PD78078Y PD78P078Y Document No. U10641EJ4V0UM00 (4th edition) Date Published December 1997 N © 1994 Printed in Japan...
  • Page 2 [MEMO]...
  • Page 3 Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
  • Page 4 To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
  • Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 6 Major Revisions in This Edition Page Throughout The following products have been changed from “under development” to “already developed”. PD78078Y Subseries: PD78076Y, 78078Y, 78P078Y The following packages have been added to the PD78078Y Subseries. 100-pin plastic LQFP (Fine pitch) (14 p.
  • Page 7 This manual has been prepared for user engineers who understand the functions of the PD78078 and 78078Y Subseries and design and develop its application systems and programs. The PD78078 and 78078Y Subseries consist of the following members. • PD78078 Subseries: PD78076, 78078, 78P078 • PD78078Y Subseries: PD78076Y, 78078Y, 78P078Y Caution Purpose This manual is intended for users to understand the functions described in the Organization below.
  • Page 8 Chapter Organization: This manual divides the descriptions for the PD78078 and 78078Y Subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter 1 Outline ( PD78078 Subseries) Chapter 2 Outline ( PD78078Y Subseries) Chapter 3 Pin Function ( PD78078 Subseries) Chapter 4...
  • Page 9 However, preliminary versions are not marked as such. • Related documents for this subseries Document name PD78078, 78078Y Subseries User’s Manual PD78076, 78078 Data Sheet PD78P078 Data Sheet PD78076Y, 78078Y Data Sheet PD78P078Y Data Sheet 78K/0 Series User’s Manual—Instructions...
  • Page 10 • Development Tool Documents (User’s Manuals) Document Name RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package CC78K Series C Compiler CC78K0 C Compiler CC78K0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS PG-1500 Controller IBM PC Series (PC DOS IE-78K0-NS...
  • Page 11 • Other Documents IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Quality Assurance for Semiconductor Devices Microcomputer Product Series Guide Caution The above documents are subject to change without prior notice.
  • Page 12 [MEMO]...

  • Page 13: Table Of Contents

    CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) ... 33 Features ... 33 Application Fields ... 34 Ordering Information ... 34 Quality Grade ... 35 Pin Configuration (Top View) ... 36 78K/0 Series Expansion ... 42 Block Diagram ... 44 Outline of Function ... 45 Mask Options ...
  • Page 14 3.2.17 AV ... 76 3.2.18 RESET ... 76 3.2.19 X1 and X2 ... 76 3.2.20 XT1 and XT2 ... 76 3.2.21 V ... 77 3.2.22 V ... 77 3.2.23 V ( PD78P078 only) ... 77 3.2.24 IC (Mask ROM version only) ... 77 Input/output Circuits and Recommended Connection of Unused Pins ...
  • Page 15 Processor Registers ... 110 5.2.1 Control registers ... 110 5.2.2 General registers ... 113 5.2.3 Special function register (SFR) ... 114 Instruction Address Addressing ... 118 5.3.1 Relative addressing ... 118 5.3.2 Immediate addressing ... 119 5.3.3 Table indirect addressing ... 120 5.3.4 Register addressing ...
  • Page 16 CHAPTER 7 CLOCK GENERATOR ... 165 Clock Generator Functions ... 165 Clock Generator Configuration ... 166 Clock Generator Control Register ... 167 System Clock Oscillator ... 171 7.4.1 Main system clock oscillator ... 171 7.4.2 Subsystem clock oscillator ... 172 7.4.3 Divider ...
  • Page 17 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 ... 249 10.1 8-Bit Timer/Event Counters 5 and 6 Functions ... 249 10.2 8-Bit Timer/Event Counters 5 and 6 Configurations ... 252 10.3 8-Bit Timer/Event Counters 5 and 6 Control Registers ... 254 10.4 8-Bit Timer/Event Counters 5 and 6 Operations ...
  • Page 18 CHAPTER 16 D/A CONVERTER ... 309 16.1 D/A Converter Functions ... 309 16.2 D/A Converter Configuration ... 310 16.3 D/A Converter Control Registers ... 312 16.4 D/A Converter Operations ... 313 16.5 D/A Converter Cautions ... 314 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) ... 315 17.1 Serial Interface Channel 0 Functions ...
  • Page 19 CHAPTER 21 REAL-TIME OUTPUT PORT ... 495 21.1 Real-Time Output Port Functions ... 495 21.2 Real-Time Output Port Configuration ... 495 21.3 Real-Time Output Port Control Registers ... 497 CHAPTER 22 INTERRUPT FUNCTIONS ... 499 22.1 Interrupt Function Types ... 499 22.2 Interrupt Sources and Configuration ...
  • Page 20 CHAPTER 27 PD78P078, 78P078Y ... 569 27.1 Internal Memory Size Switching Register ... 570 27.2 Internal Extension RAM Size Switching Register ... 571 27.3 PROM Programming ... 572 27.3.1 Operating modes ... 572 27.3.2 PROM write procedure ... 574 27.3.3 PROM reading procedure ... 578 27.4 Erasure Procedure ( PD78P078KL-T and 78P078YKL-T Only) ...
  • Page 21 Memory Map ( PD78076, 78076Y) ... 101 Memory Map ( PD78078, 78078Y) ... 102 Memory Map ( PD78P078, PD78P078Y) ... 103 Data Memory Addressing ( PD78076, 78076Y) ... 107 Data Memory Addressing ( PD78078, 78078Y) ... 108 Data Memory Addressing ( PD78P078, 78P078Y) ... 109 Program Counter Configuration ...
  • Page 22 Figure No. Block Diagram of Clock Generator ... 166 Subsystem Clock Feedback Resistor ... 167 Processor Clock Control Register Format ... 168 Oscillation Mode Selection Register Format ... 170 Main System Clock Waveform due to Writing to OSMS ... 170 External Circuit of Main System Clock Oscillator ...
  • Page 23 Figure No. 8-26 Control Register Settings in External Event Counter Mode ... 211 8-27 External Event Counter Configuration Diagram ... 212 8-28 External Event Counter Operation Timings (with Rising Edge Specified) ... 212 8-29 Control Register Settings in Square-Wave Output Mode ... 213 8-30 Square-Wave Output Operation Timing ...
  • Page 24 Figure No. 10-14 8-Bit Timer Control Register Settings for PWM Output Operation ... 264 10-15 PWM Output Operation Timing (Active High Setting) ... 265 10-16 PWM Output Operation Timings (CRn0 = 00H, Active High Setting) ... 265 10-17 PWM Output Operation Timings (CRn0 = FFH, Active High Setting) ... 266 10-18 PWM Output Operation Timings (CRn0 Changing, Active High Setting) ...
  • Page 25 Figure No. 17-1 Serial Bus Interface (SBI) System Configuration Example ... 317 17-2 Serial Interface Channel 0 Block Diagram ... 318 17-3 Timer Clock Select Register 3 Format ... 322 17-4 Serial Operating Mode Register 0 Format ... 324 17-5 Serial Bus Interface Control Register Format ...
  • Page 26 Figure No. 18-10 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ... 385 18-11 2-Wire Serial I/O Mode Timings ... 388 18-12 RELT and CMDT Operations ... 389 18-13 Example of Serial Bus Configuration Using I 18-14 C Bus Serial Data Transfer Timing ... 391 18-15 Start Condition ...
  • Page 27 Figure No. 19-21 Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) ... 452 19-22 Operation Timing of the Bit Slippage Detection Function through the Busy Signal (BUSY0 = 1) ... 453 19-23 Automatic Data Transmit/Receive Interval ... 454 19-24 Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock ...
  • Page 28 Figure No. 22-13 Interrupt Request Acknowledge Processing Algorithm ... 517 22-14 Interrupt Request Acknowledge Timing (Minimum Time) ... 518 22-15 Interrupt Request Acknowledge Timing (Maximum Time) ... 518 22-16 Multiple Interrupt Example ... 520 22-17 Interrupt Request Hold ... 522 22-18 Basic Configuration of Test Function ...
  • Page 29 Figure No. 27-1 Internal Memory Size Switching Register Format ... 570 27-2 Internal Extension RAM Size Switching Register Format ... 571 27-3 Page Program Mode Flowchart ... 574 27-4 Page Program Mode Timing ... 575 27-5 Byte Program Mode Flowchart ... 576 27-6 Byte Program Mode Timing ...
  • Page 30 Table No. Mask Options of Mask ROM Versions ... 47 Differences between PD78078 Subseries and PD78054 Subseries ... 47 Mask Options of Mask ROM Versions ... 63 Differences between PD78078Y Subseries and PD78054Y Subseries ... 63 Pin Input/Output Circuit Types ... 78 Pin Input/Output Circuit Types ...
  • Page 31 Table No. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ... 243 9-10 Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ... 245 10-1 8-Bit Timer/Event Counters 5 and 6 Interval Times ...
  • Page 32 Table No. 20-3 Relationship between Main System Clock and Baud Rate ... 467 20-4 Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) ... 468 20-5 Relationship between Main System Clock and Baud Rate ... 476 20-6 Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) ...

  • Page 33: Chapter 1 Outline ( Pd78078 Subseries)

    CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) 1.1 Features Internal high-capacity ROM and RAM Type Program Memory (ROM) Part Number PD78076 48 Kbytes PD78078 60 Kbytes PD78P078 Note 1 60 Kbytes Notes 1. The capacity of internal PROM can be changed by means of the internal memory size switching register (IMS).

  • Page 34: Application Fields

    100-pin ceramic WQFN (14 x 20 mm) Note Under development Caution Two types of packages are available for the PD78076GC, 78078GC, and 78P078GC. For the suppliable package, contact an NEC sales representative. Remark xxx indicates ROM code suffix. Package Internal ROM...

  • Page 35: Quality Grade

    • PD78P078KL-T Remark xxx indicates ROM code suffix. Please refer to “Quality Grades on NEC Semiconductor Devices”(C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Package (for function evaluation only)

  • Page 36: Pin Configuration (Top View)

    CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) 1.5 Pin Configuration (Top View) (1) Normal operating mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) PD78076GC-xxx-7EA, 78078GC-xxx-7EA PD78P078GC-7EA 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) PD78076GC-xxx-8EU Note , 78078GC-xxx-8EU...
  • Page 37 CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) 99 98 97 96 95 94 93 92 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 P130/ANO0 P131/ANO1 REF1 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P80/A0 P81/A1 P82/A2 P83/A3 P84/A4 26 27 28 29 30 31 32 33 34 Cautions 1.
  • Page 38 CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) 100-pin plastic QFP (14 x 20 mm) PD78076GF-xxx-3BA, 78078GF-xxx-3BA PD78P078GF-3BA 100-pin ceramic WQFN (14 x 20 mm) PD78P078KL-T P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 IC (V XT1/P07 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6...
  • Page 39 CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) Pin Identifications A0 to A15 Address Bus AD0 to AD7 Address/Data Bus ANI0 to ANI7 Analog Input ANO0, ANO1 Analog Output ASCK Asynchronous Serial Clock ASTB Address Strobe Analog Power Supply , AV Analog Reference Voltage REF0 REF1 Analog Ground...
  • Page 40 CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) (2) PROM programming mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) PD78P078GC-7EA 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) PD78P078GC-8EU Note Note Under development Cautions 1.
  • Page 41 CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) 100-pin plastic QFP (14 x 20 mm) PD78P078GF-3BA 100-pin ceramic WQFN PD78P078KL-T Open Open RESET Cautions 1. (L) : Connect independently to V 2. V : Connect to the ground. 3. RESET : Set to the low level. 4.

  • Page 42: Series Expansion

    CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) 1.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Control 100-pin PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 80-pin PD780058 80-pin PD78058F 80-pin PD78054 64-pin PD780034 64-pin...
  • Page 43 CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) The following shows the major differences between subseries products. Function Subseries Name Capacity 8-bit 16-bit Watch WDT A/D Control PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch PD78078 48 K to 60 K PD78070A...

  • Page 44: Block Diagram

    CHAPTER 1 OUTLINE ( PD78078 SUBSERIES) 1.7 Block Diagram TO0/P30 16-bit TIMER/ TI00/INTP0/P00 Event Counter TI01/INTP1/P01 TO1/P31 8-bit TIMER/ Event Counter 1 TI1/P33 TO2/P32 8-bit TIMER/ Event Counter 2 TI2/P34 8-bit TIMER/ TI5/TO5/P100 Event Counter 5 8-bit TIMER/ TI6/TO6/P101 Event Counter 6 Watchdog Timer Watch Timer SI0/SB0/P25...

  • Page 45: Outline Of Function

    Notes 1. The capacity of the internal PROM can be changed using the internal memory size switching register (IMS). 2. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size switching register (IXS). PD78076 PD78078 Mask ROM 48 Kbytes...
  • Page 46 Non-maskable Software Test input Power supply voltage Operating ambient temperature Package Note Under development PD78076 PD78078 Internal: 15 External: 7 Internal: 1 Internal: 1 Internal: 1 External: 1 = 1.8 to 5.5 V = –40 to +85 C •...

  • Page 47: Mask Options

    1.9 Mask Options The mask ROM versions ( PD78076, 78078) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production.
  • Page 48 [MEMO]...

  • Page 49: Chapter 2 Outline ( Pd78078Y Subseries)

    CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 2.1 Features Internal high-capacity ROM and RAM Type Program Memory (ROM) Part Number PD78076Y 48 Kbytes 60 Kbytes PD78078Y PD78P078Y 60 Kbytes Note 1 Notes 1. The capacity of internal PROM can be changed using the internal memory size switching register (IMS).

  • Page 50: Application Fields

    CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 2.2 Application Fields Cellular phones, cordless telephones, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 2.3 Ordering Information Part number PD78076YGC-xxx-8EU Note 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) PD78076YGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm, resin thickness 2.7 mm) PD78078YGC-xxx-8EU...

  • Page 51: Quality Grade

    • PD78P078YKL-T Remark xxx indicates ROM code suffix. Please refer to “Quality Grades on NEC Semiconductor Devices”(C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Package (for function evaluation only)

  • Page 52: Pin Configuration (Top View)

    CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 2.5 Pin Configuration (Top View) (1) Normal operating mode 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) PD78076YGC-xxx-8EU Note , 78078YGC-xxx-8EU PD78P078YGC-8EU Note Note Under development Note...
  • Page 53 CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 99 98 97 96 95 94 93 92 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 P130/ANO0 P131/ANO1 REF1 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P80/A0 P81/A1 P82/A2 P83/A3 P84/A4 26 27 28 29 30 31 32 33 34 Cautions 1.
  • Page 54 CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 100-pin plastic QFP (14 x 20 mm) PD78076YGF-xxx-3BA PD78078YGF-xxx-3BA, 78P078YGF-3BA 100-pin ceramic WQFN (14 x 20 mm) PD78P078YKL-T P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 IC (V XT1/P07 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6...
  • Page 55 CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) Pin Identifications A0 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Serial Clock ASTB : Address Strobe : Analog Power Supply , AV : Analog Reference Voltage...
  • Page 56 CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) (2) PROM programming mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) PD78P078YGC-7EA 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) PD78P078YGC-8EU Note Note Under development Cautions 1.
  • Page 57 CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 100-pin plastic QFP (14 x 20 mm) PD78P078YGF-3BA 100-pin ceramic WQFN PD78P078YKL-T Open Open RESET Cautions 1. (L) : Connect independently to V 2. V : Connect to the ground. 3. RESET : Set to the low level. 4.

  • Page 58: Series Expansion

    CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 2.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Control 100-pin PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 80-pin PD780058 PD780058Y 80-pin PD78058F 80-pin PD78054 64-pin PD780034...
  • Page 59 CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) Major differences among Y subseries are tabulated below. Function Subseries Capacity Control PD78078Y 48K to 60K PD78070AY — PD780018AY 48K to 60K PD780058Y 24K to 60K PD78058FY 48K to 60K PD78054Y 16K to 60K PD780034Y 8K to 32K PD780024Y PD78018FY 8K to 60K...

  • Page 60: Block Diagram

    CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 2.7 Block Diagram TO0/P30 16-bit TIMER/ TI00/INTP0/P00 Event Counter TI01/INTP1/P01 TO1/P31 8-bit TIMER/ Event Counter 1 TI1/P33 TO2/P32 8-bit TIMER/ Event Counter 2 TI2/P34 8-bit TIMER/ P100/TI5/TO5 Event Counter 5 8-bit TIMER/ P101/TI6/TO6 Event Counter 6 Watchdog Timer Watch Timer SI0/SB0/SDA0/P25...

  • Page 61: Outline Of Function

    CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 2.8 Outline of Function Part Number Item Internal High-speed RAM memory Buffer RAM Expansion RAM Memory space General register Minimum With main system clock selected instruction execution With subsystem clock selected time Instruction set I/O port A/D converter D/A converter...
  • Page 62 CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) Part Number Item Vectored Maskable interrupt source Non-maskable Software Test input Power supply voltage Operating ambient temperature Package Note Under development PD78076Y PD78078Y Internal: 15 External: 7 Internal: 1 Internal: 1 Internal: 1 External: 1 = 1.8 to 5.5 V = –40 to +85 C •...

  • Page 63: Mask Options

    CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES) 2.9 Mask Options The mask ROM versions ( PD78076Y, 78078Y) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production. Using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving.
  • Page 64 [MEMO]...

  • Page 65: Chapter 3 Pin Function ( Pd78078 Subseries)

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Input Input/ Port 0. output 8-bit input/output port. Note 1 Input P10 to P17 Port 1. 8-bit input/output port. Input/ Input/output mode can be specified bit-wise.
  • Page 66 CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Port 3. Input/ 8-bit input/output port. output Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software.
  • Page 67 CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output Port 9. 7-bit input/output port. Input/ Input/output mode can be output specified bit-wise. Port 10. P100 4-bit input/output port. Input/ Input/output mode can be specified bit-wise. P101 output If used as an input port, an on-chip pull-up resistor can be connected...
  • Page 68 CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output INTP0 INTP1 INTP2 External interrupt request inputs with specifiable valid edges (rising edge, INTP3 Input falling edge, both rising and falling edges). INTP4 INTP5 INTP6 Input Serial interface serial data input Output Serial interface serial data output...

  • Page 69: Prom Programming Mode Pins ( Pd78P078 Only)

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input/Output A0 to A7 Output Low-order address bus when expanding external memory A8 to A15 Output High-order address bus when expanding external memory Strobe signal output for read operation from external memory Output...

  • Page 70: Description Of Pin Functions

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.

  • Page 71: P20 To P27 (Port 2)

    Serial interface serial data input/output pins (b) SCK0 and SCK1 Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins...

  • Page 72: P30 To P37 (Port 3)

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 73: P50 To P57 (Port 5)

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 74: P70 To P72 (Port 7)

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise.

  • Page 75: P90 To P96 (Port 9)

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.2.10 P90 to P96 (Port 9) These are 7-bit input/output ports. P90 to P93 can drive LEDs directly. They can be specified bit-wise as input or output ports with port mode register 9 (PM9). P90 to P93 are N-ch open-drain pins.

  • Page 76: P130 And P131 (Port 13)

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.2.13 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 2-bit input/output ports.

  • Page 77: Vdd

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.2.21 V Positive power supply pin 3.2.22 V Ground potential pin 3.2.23 V ( PD78P078 only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V in normal operating mode. 3.2.24 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78078 at delivery.

  • Page 78: Input/Output Circuits And Recommended Connection Of Unused Pins

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 2-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1.
  • Page 79 CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Circuit Type P50/A8 to P57/A15 P60 to P63 (Mask ROM version) 13-B P60 to P63 ( PD78P078) 13-D P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/A0 to P87/A7...

  • Page 80: List Of Pin Input/Output Circuits

    CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) Figure 3-1. List of Pin Input/Output Circuits (1/2) Type 2 Schmitt-Triggered Input with Hysteresis Characteristics Type 5-A pullup enable data P-ch output N-ch disable input enable Type 5-E pullup enable data P-ch output N-ch disable Type 8-A...
  • Page 81 CHAPTER 3 PIN FUNCTION ( PD78078 SUBSERIES) Figure 3-1. List of Pin Input/Output Circuits (2/2) Type 12-A pullup enable data P-ch output N-ch disable input P-ch enable analog output voltage N-ch Type 13-B Mask Option data N-ch output disable P-ch medium breakdown input buffer Type 13-D...
  • Page 82 [MEMO]...

  • Page 83: Chapter 4 Pin Function ( Pd78078Y Subseries)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Input Input/ Port 0. output 8-bit input/output port. Note 1 Input P10 to P17 Port 1. 8-bit input/output port. Input/ Input/output mode can be specified bit-wise.
  • Page 84 CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Port 3. Input/ 8-bit input/output port. output Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software.
  • Page 85 CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output Port 9. 7-bit input/output port. Input/ Input/output mode can be output specified bit-wise. Port 10. P100 4-bit input/output port. Input/ Input/output mode can be specified bit-wise. P101 output If used as an input port, an on-chip pull-up resistor can be connected...
  • Page 86 CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output INTP0 INTP1 INTP2 External interrupt request inputs with specifiable valid edges (rising edge, INTP3 Input falling edge, both rising and falling edges). INTP4 INTP5 INTP6 Input Serial interface serial data input Output Serial interface serial data output...

  • Page 87: Prom Programming Mode Pins ( Pd78P078Y Only)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input/Output A0 to A7 Output Low-order address bus when expanding external memory A8 to A15 Output High-order address bus when expanding external memory Strobe signal output for read operation from external memory Output...

  • Page 88: Description Of Pin Functions

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.

  • Page 89: P20 To P27 (Port 2)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions. The following operating modes can be specified bit-wise.

  • Page 90: P30 To P37 (Port 3)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 91: P50 To P57 (Port 5)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 92: P70 To P72 (Port 7)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise.

  • Page 93: P90 To P96 (Port 9)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2.10 P90 to P96 (Port 9) These are 7-bit input/output ports. P90 to P93 can drive LEDs directly. They can be specified bit-wise as input or output ports with port mode register 9 (PM9). P90 to P93 are N-ch open-drain pins.

  • Page 94: P130 And P131 (Port 13)

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2.13 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 2-bit input/output ports.

  • Page 95: Vdd

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.2.21 V Positive power supply pin 4.2.22 V Ground potential pin 4.2.23 V ( PD78P078Y only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V in normal operating mode. 4.2.24 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78078Y at delivery.

  • Page 96: Input/Output Circuits And Recommended Connection Of Unused Pins

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) 4.3 Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1.
  • Page 97 CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Circuit Type P50/A8 to P57/A15 P60 to P63 (Mask ROM version) 13-B P60 to P63 ( PD78P078Y) 13-D P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/A0 to P87/A7...

  • Page 98: List Of Pin Input/Output Circuits

    CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) Figure 4-1. List of Pin Input/Output Circuits (1/2) Type 2 Schmitt-Triggered Input with Hysteresis Characteristics Type 5-A pullup enable data P-ch output N-ch disable input enable Type 5-E pullup enable data P-ch output N-ch disable Type 8-A...
  • Page 99 CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES) Figure 4-1. List of Pin Input/Output Circuits (2/2) Type 12-A pullup enable data P-ch output N-ch disable input P-ch enable analog output voltage N-ch Type 13-B Mask Option data N-ch output disable P-ch medium breakdown input buffer Type 13-D...
  • Page 100 [MEMO]...

  • Page 101: Chapter 5 Cpu Architecture

    CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces The PD78078 and 78078Y Subseries allow access to a memory space of 64 Kbytes. Figures 5-1 to 5-3 shows memory maps. Figure 5-1. Memory Map ( PD78076, 78076Y) FFFFH FF00H FEFFH General Registers...

  • Page 102: Memory Map ( Pd78078, 78078Y)

    Figure 5-2. Memory Map ( PD78078, 78078Y) FFFFH FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space F800H F7FFH F400H F3FFH F000H EFFFH Program memory space 0000H Note When internal ROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the internal memory size switching register.

  • Page 103: Memory Map ( Pd78P078, Pd78P078Y)

    CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map ( PD78P078, PD78P078Y) FFFFH Special Function Registers (SFRs) FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-speed RAM FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space F800H F7FFH...

  • Page 104: Internal Program Memory Space

    The internal program memory space stores programs and table data. This is generally accessed by the program counter (PC). The PD78078 and 78078Y Subseries have various size of internal ROMs or PROM as shown below. Part number PD78076, 78076Y PD78078, 78078Y PD78P078, 78P078Y The internal program memory is divided into three areas: vector table area, CALLT instruction table area, and CALLF instruction table area.

  • Page 105: Vector Table

    CHAPTER 5 CPU ARCHITECTURE (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.

  • Page 106: Internal Data Memory Space

    5.1.2 Internal data memory space The PD78078 and 78078Y Subseries units incorporate the following RAMs. (1) Internal high-speed RAM This is a 1024 x 8-bit configuration in the area FB00H to FEFFH 4 banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack memory.

  • Page 107: Data Memory Addressing

    (SFRs) and general registers. The data memory space is the entire 64-Kbyte space (0000H to FFFFH). Figures 5-4 to 5-6 show the data memory addressing modes. For details of addressing, refer to 5.4 Operand Address Addressing. Figure 5-4. Data Memory Addressing ( PD78076, 78076Y) FFFFH Special Function...

  • Page 108: Data Memory Addressing ( Pd78078, 78078Y)

    Figure 5-5. Data Memory Addressing ( PD78078, 78078Y) FFFFH Special Function Registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH...

  • Page 109: Data Memory Addressing ( Pd78P078, 78P078Y)

    CHAPTER 5 CPU ARCHITECTURE Figure 5-6. Data Memory Addressing ( PD78P078, 78P078Y) FFFFH Special Function Registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-speed RAM 1024 x 8 bits FE20H FE1FH FB00H...

  • Page 110: Processor Registers

    5.2 Processor Registers The PD78078 and 78078Y Subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The control registers consist of a program counter (PC), a program status word (PSW), and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
  • Page 111 CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt are disabled. When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledge is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag.

  • Page 112: Stack Pointer Configuration

    (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 5-9. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.

  • Page 113: General Registers

    5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL).

  • Page 114: Special Function Register (Sfr)

    5.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions.

  • Page 115: Special Function Register List

    Table 5-3. Special Function Register List (1/3) Address Special Function Register (SFR) Name FF00H Port0 FF01H Port1 FF02H Port2 FF03H Port3 FF04H Port4 FF05H Port5 FF06H Port6 FF07H Port7 FF08H Port8 FF09H Port9 FF0AH Port10 FF0CH Port12 FF0DH Port13 FF10H Capture/compare register 00 FF11H FF12H...
  • Page 116 Table 5-3. Special Function Register List (2/3) Address Special Function Register (SFR) Name FF30H Real-time output buffer register L FF31H Real-time output buffer register H FF34H Real-time output port mode register FF36H Real-time output port control register FF38H Correction address register 0 FF39H FF3AH Correction address register 1...
  • Page 117 2. The value after reset depends on products. PD78076,78076Y: CCH, PD78078, 78078Y: CFH, PD78P078, 78P078Y: CFH When a mask ROM version is used, do not set to IMS any value other than that determined at reset, unless external device expansion function is used with the PD78078 or 78078Y.

  • Page 118: Instruction Address Addressing

    5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.

  • Page 119: Immediate Addressing

    5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory space. CALLF !addr11 instruction branches to the area from 0800H to 0FFFH.

  • Page 120: Table Indirect Addressing

    5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory space.

  • Page 121: Register Addressing

    5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] CHAPTER 5 CPU ARCHITECTURE...

  • Page 122: Operand Address Addressing

    5.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed.

  • Page 123: Register Addressing

    5.4.2 Register addressing [Function] The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn, RPn) in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

  • Page 124: Direct Addressing

    5.4.3 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] CHAPTER 5 CPU ARCHITECTURE Identifier Description addr16 Label or 16-bit immediate data 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0...

  • Page 125: Short Direct Addressing

    5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space, from FE20H to FF1FH. An internal high-speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

  • Page 126: Special Function Register (Sfr) Addressing

    5.4.5 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.

  • Page 127: Register Indirect Addressing

    5.4.6 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specify code in the instruction code.

  • Page 128: Based Addressing

    5.4.7 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1).

  • Page 129: Based Indexed Addressing

    5.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1).
  • Page 130 [MEMO]...

  • Page 131: Chapter 6 Port Functions

    CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The PD78078 and 78078Y Subseries units incorporate two input ports and eighty-six input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.

  • Page 132: Port Functions ( Pd78078 Subseries)

    Table 6-1. Port Functions ( PD78078 Subseries) (1/2) Pin Name Port 0. 8-bit input/output port. Port 1. 8-bit input/output port. P10 to P17 Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software. Port 2.
  • Page 133 Table 6-1. Port Functions ( PD78078 Subseries) (2/2) Pin Name Port 6. 8-bit input/output port. Input/output mode can be specified bit-wise. Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software. Port 8.

  • Page 134: Port Functions ( Pd78078Y Subseries)

    Table 6-2. Port Functions ( PD78078Y Subseries) (1/2) Pin Name Port 0. 8-bit input/output port. Port 1. P10 to P17 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software. Port 2.
  • Page 135 Table 6-2. Port Functions ( PD78078Y Subseries) (2/2) Pin Name Port 6. 8-bit input/output port. Input/output mode can be specified bit-wise. Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software. Port 8.

  • Page 136: Port Configuration

    6.2 Port Configuration A port consists of the following hardware: Item Control register Port Pull-up resistor Note MM specifies port 4 input/output. 6.2.1 Port 0 Port 0 is an 8-bit input/output port with output latch. P01 to P06 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (PM0).

  • Page 137: Block Diagram Of P00 And P07

    CHAPTER 6 PORT FUNCTIONS Figure 6-2. Block Diagram of P00 and P07 Figure 6-3. Block Diagram of P01 to P06 PUO0 PORT Output Latch (P01 to P06) PM01 to PM06 PUO : Pull-up resistor option register PM : Port mode register : Port 0 read signal WR : Port 0 write signal P00/INTP0/TI00,...

  • Page 138: Port 1

    6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 139: Port 2 ( Pd78078 Subseries)

    6.2.3 Port 2 ( PD78078 Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 140: Block Diagram Of P22 And P27

    Figure 6-6. Block Diagram of P22 and P27 PUO2 PORT Output Latch (P20, P21, P23 to P26) PM20, PM21 PM23 to PM26 Dual Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal CHAPTER 6 PORT FUNCTIONS Selector...

  • Page 141: Port 2 ( Pd78078Y Subseries)

    6.2.4 Port 2 ( PD78078Y Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 142: Block Diagram Of P22 And P27

    Figure 6-8. Block Diagram of P22 and P27 PUO2 PORT Output Latch (P22, P27) PM22, PM27 Dual Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal CHAPTER 6 PORT FUNCTIONS Selector P-ch...

  • Page 143: Port 3

    6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 144: Port 4

    6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on- chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 145: Port 5

    6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 146: Port 6

    6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has pull-up resistor options as shown below. However, the option specification method differs depending on the port pin and the device version.

  • Page 147: Block Diagram Of P60 To P63

    CHAPTER 6 PORT FUNCTIONS Figure 6-13. Block Diagram of P60 to P63 PORT Output Latch (P60 to P63) PM60 to PM63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14. Block Diagram of P64 to P67 PUO6 PORT Output Latch...

  • Page 148: Port 7

    6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be connected in 3-bit units with a pull-up resistor option register L (PUOL).

  • Page 149: Block Diagram Of P71 And P72

    CHAPTER 6 PORT FUNCTIONS Figure 6-16. Block Diagram of P71 and P72 PUO7 PORT Output Latch (P71, P72) PM71, PM72 Dual Function PUO : Pull-up resistor option register PM : Port mode register : Port 7 read signal WR : Port 7 write signal P-ch Selector P71/SO2/TxD,...

  • Page 150: Port 8

    6.2.10 Port 8 Port 8 is an 8-bit input/output port with output latch. P80 to P87 pins can specify the input mode/output mode in 1-bit units with the port mode register 8 (PM8). When pins P80 to P87 are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register H (PUOH).

  • Page 151: Port 9

    6.2.11 Port 9 Port 9 is an 7-bit input/output port with output latch. P90 to P96 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (PM9). This port has pull-up resistor options as shown below. However, the option specification method differs depending on the port pin and the device version.

  • Page 152: Block Diagram Of P90 To P93

    Figure 6-18. Block Diagram of P90 to P93 PORT Output Latch (P90 to P93) PM90 to PM93 PM : Port mode register : Port 9 read signal WR : Port 9 write signal Figure 6-19. Block Diagram of P94 to P96 PUO9 PORT Output Latch...

  • Page 153: Port 10

    6.2.12 Port 10 Port 10 is a 4-bit input/output port with output latch. P100 to P103 pins can specify the input mode/output mode in 1-bit units with the port mode register 10 (PM10). When pins P100 to P103 are used as input ports, an on-chip pull-up resistor can be connected to them in 4-bit units with a pull-up resistor option register H (PUOH).

  • Page 154: Block Diagram Of P102 And P103

    Figure 6-21. Block Diagram of P102 and P103 PUO10 PORT Output Latch (P102, P103) PM102, PM103 PUO : Pull-up resistor option register PM : Port mode register : Port 6 read signal WR : Port 6 write signal CHAPTER 6 PORT FUNCTIONS Selector P-ch P102, P103...

  • Page 155: Block Diagram Of P120 To P127

    6.2.13 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with the port mode register 12 (PM12). When pins P120 to P127 are used as input port pins, an on-chip pull-up resistor can be connected in 8-bit units with a pull-up resistor option register H (PUOH).

  • Page 156: Port 13

    6.2.14 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with the port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor can be connected in 2-bit units with a pull-up resistor option register H (PUOH).

  • Page 157: Port Function Control Registers

    6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM10, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM5 to PM10, PM12, PM13) These registers are used to set port input/output in 1-bit units.

  • Page 158: Port Mode Register And Output Latch Settings When Using Alternate Function

    Table 6-6. Port Mode Register and Output Latch Settings when Using Alternate Function Alternate Function Pin Name Name Input/Output INTP0 Input TI00 Input INTP1 Input TI01 Input P02 to P06 INTP2 to INTP6 Input Note 1 Input P10 to P17 Note 1 ANI0 to ANI7 Input...

  • Page 159: Port Mode Register Format

    CHAPTER 6 PORT FUNCTIONS Figure 6-24. Port Mode Register Format Symbol PM06 PM05 PM04 PM03 PM02 PM01 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80...

  • Page 160: Pull-Up Resistor Option Register Format

    (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL.

  • Page 161: Memory Expansion Mode Register Format

    (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-26. Memory Expansion Mode Register Format Symbol Single-chip/Memory Expansion Mode...

  • Page 162: Key Return Mode Register Format

    (4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-27.

  • Page 163: Port Function Operations

    6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

  • Page 164: Selection Of Mask Option

    6.5 Selection of Mask Option The following mask option is provided in mask ROM version. The PD78P078 and 78P078Y have no mask option. Table 6-7. Comparison between Mask ROM Version and the PD78P078 and 78P078Y Pin Name Mask option for pins P60 to P63 and P90 to P93 CHAPTER 6 PORT FUNCTIONS Mask ROM Version...

  • Page 165: Chapter 7 Clock Generator

    CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).

  • Page 166: Clock Generator Configuration

    7.2 Clock Generator Configuration The clock generator consists of the following hardware. Table 7-1. Clock Generator Configuration Item Control register Oscillator Figure 7-1. Block Diagram of Clock Generator XT1/P07 Subsystem Clock Oscillator Main System Clock Divider Oscillator STOP Oscillation Mode Selection Register CHAPTER 7 CLOCK GENERATOR Configuration...

  • Page 167: Clock Generator Control Register

    7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC selects a CPU clock and the division ratio, determines whether to make the main system clock oscillator operate or stop, and enables or desables the subsystem clock oscillator internal feedback resistor.

  • Page 168: Processor Clock Control Register Format

    Figure 7-3. Processor Clock Control Register Format Symbol <7> <6> <5> <4> CPU CIock (f PCC2 PCC1 PCC0 Other than above Setting prohibited CPU Clock Status Main system clock Subsystem clock Subsystem Clock Feedback Resistor Selection Internal feedback resistor used Internal feedback resistor not used Main System Clock Oscillation Control Oscillation possible...

  • Page 169: Relationship Between Cpu Clock And Minimum Instruction Execution Time

    The fastest instruction of the PD78078 and 78078Y Subseries can be executed in two clocks of the CPU clock. The relationship between the CPU clock (f Table 7-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (f = 5.0 MHz, f = 32.768 kHz : Main system clock oscillation frequency...

  • Page 170: Oscillation Mode Selection Register Format

    (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock.

  • Page 171: System Clock Oscillator

    7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.

  • Page 172: Subsystem Clock Oscillator

    7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin.
  • Page 173 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Oscillator with Bad Connection (2/2) (c) Changing high current is too near a signal conductor (e) Signals are fetched Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.

  • Page 174: Divider

    7.4.3 Divider The divider generates various clocks by dividing the main system clock oscillator output (f 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.

  • Page 175: Clock Generator Operations

    7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS).

  • Page 176: Main System Clock Operations

    7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.

  • Page 177: Subsystem Clock Operations

    Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.

  • Page 178: Changing System Clock And Cpu Clock Settings

    7.6 Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).

  • Page 179: System Clock And Cpu Clock Switching Procedure

    7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching RESET Interrupt Request Signal System Clock CPU Clock Internal Reset Operation (1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, main system clock starts oscillation.
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  • Page 181: Chapter 8 16-Bit Timer/Event Counter

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timers Incorporated into PD78078, 78078Y Subseries This chapter explains the 16-bit timer/event counter. First of all, the timers incorporated into the PD78078, 78078Y Subseries and the related circuits are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency or one-shot pulse output.

  • Page 182: Timer/Event Counter Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operations Operation Interval timer mode External event counter Function Timer output PWM output Pulse width measurement Square-wave output One-shot pulse output Interrupt request Test input Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2.

  • Page 183: 16-Bit Timer/Event Counter Functions

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output TM0 can perform both PWM output and pulse width measurement at the same time.

  • Page 184: Bit Timer/Event Counter Square-Wave Output Ranges

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 2 x TI00 input cycle 2 x 1/f —...

  • Page 185: 16-Bit Timer/Event Counter Configuration

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4. 16-Bit Timer/Event Counter Configuration Item Timer register Register Timer output Control register Note Refer to Figure 22-1 Basic Configuration of Interrupt Function. Configuration 16 bits x 1 (TM0) Capture/compare register: 16 bits x 2 (CR00, CR01)

  • Page 186: Bit Timer/Event Counter Block Diagram

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-1. 16-Bit Timer/Event Counter Block Diagram Internal bus Capture/Compare Control Register 0 CRC02 CRC01 CRC00 TI01 / P01 / 16-Bit Capture/Compare INTP1 Control Register (CR00) INTTM3 16-Bit Timer Register (TM0) TI00 / P00 / Note 1 INTP0 16-Bit Capture/Compare...

  • Page 187: Bit Timer/Event Counter Output Control Circuit Block Diagram

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram PWM Pulse Output Control Circuit CRC02 INTTM01 CRC00 INTTM00 Edge TI00 / Detection P00 / Circuit INTP0 ES11 ES10 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 External Interrupt Mode Register 0 Remark The circuitry enclosed by the dotted line is the output control circuit.

  • Page 188: Intp0/Ti00 Pin Valid Edge And Cr00 Capture Trigger Valid Edge

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0 (CRC0).
  • Page 189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register (CR01) should first be set as a capture register. RESET input sets TM0 to 0000H.

  • Page 190: 16-Bit Timer/Event Counter Control Registers

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4 16-Bit Timer/Event Counter Control Registers The following seven types of registers are used to control the 16-bit timer/event counter. • Timer clock select register 0 (TCL0) • 16-bit timer mode control register (TMC0) • Capture/compare control register 0 (CRC0) •...

  • Page 191: Timer Clock Selection Register 0 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Selection Register 0 Format Symbol <7> TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 (32.768 kHz) Other than above Setting prohibited 16-Bit Timer Register Count Clock Selection TCL06 TCL05 TCL04 TI00 (Valid edge specifiable) Watch timer output (INTTM3)

  • Page 192: Bit Timer Mode Control Register Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.

  • Page 193: Capture/Compare Control Register 0 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation (by setting TMC01 to TMC03 to 0, 0, 0). 2. Set the valid edge of the TI00/INTP0 pin with an external interrupt mode register 0 (INTM0) and select the sampling clock frequency with a sampling clock select register (SCS).

  • Page 194: Bit Timer Output Control Register Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip-flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shop pulse by software.

  • Page 195: Port Mode Register 3 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH.

  • Page 196: External Interrupt Mode Register 0 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8. External Interrupt Mode Register 0 Format Symbol INTM0 ES31 ES30 ES21 ES20 ES11 ES10...

  • Page 197: Sampling Clock Select Register Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select registers (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction.

  • Page 198: 16-Bit Timer/Event Counter Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand is used as the interval.

  • Page 199: Interval Timer Configuration Diagram

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM3 Selector TI00/P00/INTP0 Figure 8-12. Interval Timer Operation Timings Count Clock TM0 Count Value 0000 0001 Count Start CR00 INTTM00 Interval Time Remark Interval time = (N + 1) x t : N = 0001H to FFFFH. OVF0 16-Bit Timer Register (TM0) 0000 0001...

  • Page 200: Pwm Output Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time TCL06 TCL05 TCL4 MCS = 1 2 x TI00 input cycle Setting prohibited 2 x 1/f (400 ns) x 1/f (800 ns) x 1/f (1.6 s) 2 x watch timer output cycle Other than above Setting prohibited...

  • Page 201: Control Register Settings For Pwm Output Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) TMC0 (b) Capture/compare control register 0 (CRC0) CRC0 (c) 16-bit timer output control register (TOC0) OSPT OSPE TOC0 Remark 0/1 : Setting 0 or 1 allows another function to be used simultaneously with PWM output. See the description of the respective control registers for details.

  • Page 202: Example Of D/A Converter Configuration With Pwm Output

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V ) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. capture/compare register 00 (CR00) value : External switching circuit reference voltage Figure 8-14.

  • Page 203: Ppg Output Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/ compare register 00 (CR00), respectively.

  • Page 204: Pulse Width Measurement Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.

  • Page 205: Configuration Diagram For Pulse Width Measurement By Free-Running Counter

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter INTTM3 TI00/P00/INTP00 Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input...

  • Page 206: Control Register Settings For Two Pulse Width Measurements With Free-Running Counter

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Two pulse width measurements with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8- 20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin.
  • Page 207 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input CR00 Captured Value INTP1 OVF0 FFFF...
  • Page 208 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set.

  • Page 209: Timing Of Pulse Width Measurement Operation By Free-Running Counter And Two Capture Registers (With Rising Edge Specified)

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 FFFF...

  • Page 210: Control Register Settings For Pulse Width Measurement By Means Of Restart

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).

  • Page 211: External Event Counter Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.

  • Page 212: External Event Counter Configuration Diagram

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram TI00 Valid Edge Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified) TI00 Pin Input TM0 Count Value 0000 0001 0002 0003 0004 0005 CR00 INTTM0 Caution When reading the external event counter count value, TM0 should be read.

  • Page 213: Square-Wave Output Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation 16-bit timer/event counter operates as a square wave output with any selected frequency at intervals of the count value preset to the 16-bit capture/compare register 00 (CR00). The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1.

  • Page 214: Square-Wave Output Operation Timing

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing TI00 Pin Input TM0 Count 0000 0001 0002 Value CR00 INTTM0 TO0 Pin Output Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 2 x TI00 input cycle —...

  • Page 215: One-Shot Pulse Output Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input). (1) One-shot pulse output using software trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16- bit timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0 by software, a one-shot pulse is output from the TO0/P30 pin.

  • Page 216: Timing Of One-Shot Pulse Output Operation Using Software Trigger

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger Set 0CH to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 CR01 Set Value CR00 Set Value OSPT INTTM01 INTTM00 TO0 Pin Output Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively.

  • Page 217: Control Register Settings For One-Shot Pulse Output Operation Using External Trigger

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16- bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/P30 pin with a TI00/P00 valid edge as an external trigger.
  • Page 218 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34. Timing of One-Shot Pulse Output Operation Using External Trigger (With Rising Edge Specified) Set 08H to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 CR01 Set Value CR00 Set Value TI00 Pin Input INTTM01 INTTM00...

  • Page 219: 16-Bit Timer/Event Counter Operating Precautions

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse.

  • Page 220: Capture Register Data Retention Timing

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge.

  • Page 221: Operation Timing Of Ovf0 Flag

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. CR00 is set to FFFFH. When TM0 is counted up from FFFFH to 0000H. Figure 8-38.
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  • Page 223: Chapter 9 8-Bit Timer/Event Counters 1 And 2

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/ event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode).

  • Page 224: Bit Timer/Event Counters 1 And 2 Interval Times

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time MCS = 1 MCS = 0 2 x 1/f x 1/f (400 ns)

  • Page 225: Bit Timer/Event Counters 1 And 2 Square-Wave Output Ranges

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0...

  • Page 226: 16-Bit Timer/Event Counter Mode

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Interval Time MCS = 1 MCS = 0...

  • Page 227: Square-Wave Output Ranges When 8-Bit Timer/Event Counters 1 And 2 Are Used As 16-Bit Timer/Event Counters

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Pulse Width MCS = 1...

  • Page 228: 8-Bit Timer/Event Counters 1 And 2 Configurations

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5. 8-Bit Timer/Event Counters 1 and 2 Configurations Item Timer register Register Timer output Control register...

  • Page 229: Block Diagram Of 8-Bit Timer/Event Counter Output Control Circuit 1

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Level F/F LVR1 LVS1 TOC11 INTTM1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Level F/F LVR2 LVS2...
  • Page 230 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively).

  • Page 231: 8-Bit Timer/Event Counters 1 And 2 Control Registers

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers The following four types of registers are used to control the 8-bit timer/event counter. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) •...

  • Page 232: Timer Clock Select Register 1 Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-4. Timer Clock Select Register 1 Format Symbol TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 8-Bit Timer Register 1 Count Clock Selection TCL13 TCL12 TCL11 TCL10 TI1 falling edge TI1 rising edge Other than above Setting prohibited...

  • Page 233: Bit Timer Mode Control Register 1 Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register 1 (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H.

  • Page 234: Bit Timer Output Control Register Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8- bit timer registers 1 and 2.

  • Page 235: Port Mode Register 3 Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0.

  • Page 236: 8-Bit Timer/Event Counters 1 And 2 Operations

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20).

  • Page 237: Bit Timer/Event Counter 1 Interval Time

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 TI1 input cycle TI1 input cycle 2 x 1/f (400 ns) x 1/f (800 ns) x 1/f (1.6 s) x 1/f...

  • Page 238: Bit Timer/Event Counter 2 Interval Time

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time Minimum Interval Time TCL17 TCL16 TCL15 TCL14 MCS = 1 TI2 input cycle TI2 input cycle 2 x 1/f (400 ns) x 1/f (800 ns) x 1/f (1.6 s) x 1/f...

  • Page 239: External Event Counter Operation Timings (With Rising Edge Specified)

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1) is input.

  • Page 240: Bit Timer/Event Counters 1 And 2 Square-Wave Output Ranges

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output Operation 8-bit timer/event counters 1 and 2 operate as a square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1.

  • Page 241: Timing Of Square Wave Output Operation

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-10. Timing of Square Wave Output Operation Count Clock TM1 Count Value N–1 N–1 Count Start CR10 Note Note The initial value of the TO1 output can be set by bits 2 and 3 (LVS1 and LVR1) of the 8-bit timer output control register (TOC1).

  • Page 242: 16-Bit Timer/Event Counter Mode

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is selected by using bits 0 through 3 (TCL10 through TCL13) of the timer clock select register (TCL1), and the overflow signal of the 8-bit timer/event counter 1 (TM1) is used as the count clock for the 8-bit timer/event counter 2 (TM2).

  • Page 243: Are Used As 16-Bit Timer/Event Counter

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 TI1 input cycle TI1 input cycle 2 x 1/f (400 ns) x 1/f...

  • Page 244: External Event Counter Operation Timings (With Rising Edge Specified)

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2-channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input.

  • Page 245: Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters Tm1 And Tm2) Are Used As 16-Bit Timer/Event Counter

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation The 8-bit timer/event counters 1 and 2 operate as square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers (CR10 and CR20). To set the count value, set the values of the higher 8 bits to CR20 and set the values of the lower 8 bits to CR10.

  • Page 246: 8-Bit Timer/Event Counters 1 And 2 Precautions

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.5 8-Bit Timer/Event Counters 1 and 2 Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start.

  • Page 247: Timing After Compare Register Change During Timer Count Operation

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0.
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  • Page 249: Chapter 10 8-Bit Timer/Event Counters 5 And 6

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.1 8-Bit Timer/Event Counters 5 and 6 Functions The 8-bit timer event counters 5 and 6 (TM5, TM6) have the following functions. • Interval timer • External event counter • Square-wave output •...

  • Page 250: Bit Timer/Event Counters 5 And 6 Interval Times

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 10-1. 8-Bit Timer/Event Counters 5 and 6 Interval Times Minimum Interval Width MCS = 1 MCS = 0 —...

  • Page 251: Bit Timer/Event Counters 5 And 6 Square-Wave Output Ranges

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 10-2. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0...

  • Page 252: 8-Bit Timer/Event Counters 5 And 6 Configurations

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.2 8-Bit Timer/Event Counters 5 and 6 Configurations The 8-bit timer/event counters 5 and 6 consist of the following hardware. Table 10-3. 8-Bit Timer/Event Counters 5 and 6 Configurations Item Timer register 8 bits x 2 (TM5, TM6) Register Compare register: 8 bits x 2 (CR50, CR60)

  • Page 253: Block Diagram Of 8-Bit Timer/Event Counters 5 And 6 Output Control Circuit

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 10-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit RESET LVRn LVSn TMCn1 TMCn6 INTTMn PWM Output Circuit Timer Output F/F2 TCEn INTTMn OVFn Remarks 1. The section in the broken line is an output control circuit. 2.

  • Page 254: 8-Bit Timer/Event Counters 5 And 6 Control Registers

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.3 8-Bit Timer/Event Counters 5 and 6 Control Registers The following three types of registers are used to control the 8-bit timer/event counters 5 and 6. • Timer clock select register 5 and 6 (TCL5, TCL6) •...

  • Page 255: Timer Clock Select Register 6 Format

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) Timer clock select register 6 (TCL6) This register sets count clocks of 8-bit timer register 6. TCL6 is set with an 8-bit memory manipulation instruction. RESET input sets TCL6 to 00H. Figure 10-4.

  • Page 256: Bit Timer Output Control Register Format

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) 8-bit timer mode control register 5 (TMC5) This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register 5 and controls operation of 8-bit timer/event counter 5 output control circuit. It sets R-S flip-flop (timer output F/F 1,2) setting/resetting, the active level in PWM mode, inversion enabling/ disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/disabling.

  • Page 257: Bit Timer Output Control Register 6 Format

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (4) 8-bit timer mode control register 6 (TMC6) This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register 6 and controls operation of 8-bit timer/event counter 6 output control circuit. It sets R-S flip-flop (timer output F/F 1,2) setting/resetting, active level in PWM mode, inversion enabling/ disabling in modes other than PWM mode and 8-bit timer/event counter 6 timer output enabling/disabling.

  • Page 258: Port Mode Register 10 Format

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (5) Port mode register 10 (PM10) This register sets port 10 input/output in 1-bit units. When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101 and output latches of P100 and P101 to 0. PM10 is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 259: 8-Bit Timer/Event Counters 5 And 6 Operations

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4 8-Bit Timer/Event Counters 5 and 6 Operations 10.4.1 Interval timer operations Setting the 8-bit timer mode control registers (TMC5 and TMC6) as shown in Figure 10-8 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value preset in 8-bit compare registers (CR50 and CR60) as the interval.

  • Page 260: Bit Timer/Event Counters 5 And 6 Interval Times

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 10-4. 8-Bit Timer/Event Counters 5 and 6 Interval Times Minimum Interval Time TCLn3 TCLn2 TCLn1 TCLn0 MCS = 1 TIn input cycle TIn input cycle (Setting prohibited) (200 ns) 2 x 1/f (400 ns) x 1/f (800 ns)

  • Page 261: External Event Counter Operation

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5/P100/TO5 and TI6/ P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6). TM5 and TM6 are incremented each time the valid edge specified with timer clock select registers 5 and 6 (TCL5 and TCL6) is input.

  • Page 262: Square-Wave Output

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.3 Square-wave output A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (CR50 and CR60). The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reversed at intervals of the count value preset to CR50 or CR60 by setting bit 1 (TMC51) and bit 0 (TOE5) of the 8-bit timer output control register 5 (TMC5), or bit 1 (TMC61) and bit 0 (TOE1) of the 8-bit timer mode control register 6 (TMC6) to 1.

  • Page 263: Bit Timer/Event Counters 5 And 6 Square-Wave Output Ranges

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 10-5. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Time MCS = 1 MCS = 0 MCS = 1 — (200 ns) 2 x 1/f (200 ns) (400 ns) (51.2 s) 2 x 1/f x 1/f...

  • Page 264: Pwm Output Operations

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.4 PWM output operations Setting the 8-bit timer mode control registers (TMC5 and TMC6) as shown in Figure 10-14 allows operation as PWM output. Pulses with the duty rate determined by the values preset in 8-bit compare registers (CR50 and CR60) output from the TO5/P100/TI5 or TO6/P101/TI6 pin.

  • Page 265: Pwm Output Operation Timing (Active High Setting)

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 10-15. PWM Output Operation Timing (Active High Setting) CRn0 Changing Count Clock TMn Count Value CRn0 TCEn INTTMn OVFn Inactive Level Remark n = 5, 6 Figure 10-16. PWM Output Operation Timings (CRn0 = 00H, Active High Setting) CRn0 Changing Count Clock TMn Count Value...

  • Page 266: Pwm Output Operation Timings (Crn0 Changing, Active High Setting)

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 10-17. PWM Output Operation Timings (CRn0 = FFH, Active High Setting) Count Clock TMn Count Value CRn0 TCEn INTTMn OVFn Inactive Level Remark n = 5, 6 Figure 10-18. PWM Output Operation Timings (CRn0 Changing, Active High Setting) CRn0 Changing Count Clock...

  • Page 267: 8-Bit Timer/Event Counters 5 And 6 Precautions

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.5 8-Bit Timer/Event Counters 5 and 6 Precautions (1) Timer start errors An error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts.

  • Page 268: Timings After Compare Register Change During Timer Count Operation

    CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR50 and CR60) are changed are smaller than those of 8- bit timer registers (TM5 and TM6), TM5 and TM6 continue counting, overflow and then restarts counting from 0.

  • Page 269: Chapter 11 Watch Timer

    11.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768-kHz subsystem clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals. When the 4.19-MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals.

  • Page 270: Watch Timer Configuration

    11.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 11-2. Watch Timer Configuration Item Counter Control register CHAPTER 11 WATCH TIMER Configuration 5 bits x 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2)

  • Page 271: Watch Timer Control Registers

    11.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer. • Timer clock select register 2 (TCL2) • Watch timer mode control register (TMC2) (1) Timer clock select register 2 (TCL2) This register sets the watch timer count clock. TCL2 is set with an 8-bit memory manipulation instruction.

  • Page 272: Timer Clock Select Register 2 Format

    Figure 11-2. Timer Clock Select Register 2 Format Symbol TCL2 TCL27 TCL26 TCL25 TCL24 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Watch Timer Count Clock Selection TCL24 MCS = 1 (32.768 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Caution When rewriting TCL2 to other data, stop the timer operation beforehand.

  • Page 273: Watch Timer Mode Control Register Format

    (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/disables prescaler and 5-bit counter operations. manipulation instruction. RESET input sets TMC2 to 00H. Figure 11-3. Watch Timer Mode Control Register Format Symbol TMC2 TMC26...

  • Page 274: Watch Timer Operations

    11.4 Watch Timer Operations 11.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1.

  • Page 275: Chapter 12 Watchdog Timer

    CHAPTER 12 WATCHDOG TIMER 12.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (the watchdog timer and the interval timer cannot be used simultaneously). (1) Watchdog timer mode An inadvertent program loop (runaway) is detected.

  • Page 276: Interval Times

    (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Interval Time x 1/f x 1/f x 1/f x 1/f x 1/f x 1/f x 1/f x 1/f Remarks 1. f : Main system clock frequency (f 2.

  • Page 277: Watchdog Timer Configuration

    12.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Item Control register Prescaler Timer Clock Select Register 2 CHAPTER 12 WATCHDOG TIMER Table 12-3. Watchdog Timer Configuration Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 12-1.

  • Page 278: Watchdog Timer Control Registers

    12.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory manipulation instruction.

  • Page 279: Timer Clock Select Register 2 Format

    CHAPTER 12 WATCHDOG TIMER Figure 12-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL24 TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Watch Timer Count Clock Selection TCL24 MCS = 1 (39.1 kHz) (32.768 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited...

  • Page 280: Watchdog Timer Mode Register Format

    (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 12-3. Watchdog Timer Mode Register Format <7>...

  • Page 281: Watchdog Timer Operations

    12.4 Watchdog Timer Operations 12.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).

  • Page 282: Interval Timer Operation

    12.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0, respectively. The count clock (interval time) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).

  • Page 283: Chapter 13 Clock Output Control Circuit

    CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/P35 pin.

  • Page 284: Clock Output Control Circuit Configuration

    CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 13-1. Clock Output Control Circuit Configuration Item Control register Figure 13-2. Clock Output Control Circuit Block Diagram CLOE TCL03 TCL02 TCL01 TCL00 Timer Clock Select Register 0 Configuration...

  • Page 285: Clock Output Function Control Registers

    CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock.

  • Page 286: Timer Clock Select Register 0 Format

    CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT Figure 13-3. Timer Clock Select Register 0 Format <7> Symbol TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL03 TCL02 TCL01 TCL00 Other than above 16-Bit Timer Register Count Clock Selection TCL06 TCL05 TCL04 TI00 (Valid edge specifiable) Watch Timer Output (INTTM3) Other than above Setting prohibited...

  • Page 287: Port Mode Register 3 Format

    CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.
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  • Page 289: Chapter 14 Buzzer Output Control Circuit

    CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT 14.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2-kHz, 2.4-kHz, 4.9-kHz, or 9.8-kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency.

  • Page 290: Buzzer Output Function Control Registers

    CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT 14.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.

  • Page 291: Timer Clock Select Register 2 Format

    CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT Figure 14-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL24 TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Watch Timer Count Clock Selection TCL24 MCS = 1 (39.1 kHz) (32.768 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable...

  • Page 292: Port Mode Register 3 Format

    CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.

  • Page 293: Chapter 15 A/D Converter

    CHAPTER 15 A/D CONVERTER 15.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/ D conversion result register (ADCR).

  • Page 294: A/D Converter Block Diagram

    Figure 15-1. A/D Converter Block Diagram Internal Bus A/D Converter Input Select Register ADIS3 ADIS2 ADIS1 ADIS0 ANI0/P10 ANI1/P11 Note 1 Note 2 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Edge INTP3/P03 Detector Note 3 ES40, ES41 Trigger Enable FR0 ADM3 ADM2 ADM1 A/D Converter Mode Register Notes 1.
  • Page 295 (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When the result of comparison is held to the least significant bit (LSB) (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR).

  • Page 296: A/D Converter Control Registers

    Caution A series resistor string of approximately 10 k pin. Therefore, if the output impedance of the reference voltage source is high, AV is connected in parallel with the series resistor string between AV a result, the reference voltage error will increase. (8) AV This is a GND potential pin of the A/D converter.

  • Page 297: A/D Converter Mode Register Format

    CHAPTER 15 A/D CONVERTER Figure 15-2. A/D Converter Mode Register Format <7> <6> Symbol ADM3 ADM3 ADM2 ADM1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D Conversion Time Selection = 5.0-MHz Operation MCS = 1 80/f (Setting prohibited 40/f...

  • Page 298: A/D Converter Input Select Register Format

    (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H.

  • Page 299: External Interrupt Mode Register 1 Format

    (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 15-4. External Interrupt Mode Register 1 Format Symbol ES71 ES70...

  • Page 300: A/D Converter Operations

    15.4 A/D Converter Operations 15.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).

  • Page 301: A/D Converter Basic Operation

    Figure 15-5. A/D Converter Basic Operation Sampling Time Sampling Converter Operation Undefined ADCR INTAD A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the beginning.

  • Page 302: Input Voltage And Conversion Results

    15.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in ADCR) is shown by the following expression. ADCR = INT ( x 256 + 0.5) REF0 REF0...

  • Page 303: A/D Converter Operating Mode

    15.4.3 A/D converter operating mode One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and A/D conversion is executed. The following two ways are available to start A/D conversion. •...

  • Page 304: A/D Conversion By Software Start

    (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.

  • Page 305: A/D Converter Cautions

    15.5 A/D Converter Cautions (1) Current consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV be cut in order to minimize the overall system power dissipation.

  • Page 306: Analog Input Pin Disposition

    (2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above or below AV is input (even if within the absolute maximum rating range), the conversion value for REF0 that channel will be indeterminate.

  • Page 307: A/D Conversion End Interrupt Request Generation Timing

    (5) AV pin input impedance REF0 A series resistor string of approximately 10 k Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AV reference voltage error.
  • Page 308 [MEMO]...

  • Page 309: Chapter 16 D/A Converter

    CHAPTER 16 D/A CONVERTER 16.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start the A/D conversion by setting the DACE0 and DACE1 of the D/A converter mode register (DAM).

  • Page 310: D/A Converter Configuration

    16.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 16-1. D/A Converter Configuration Item Register Control register Figure 16-1. D/A Converter Block Diagram DACS1 Write INTTM2 DACS0 Write INTTM1 REF1 DAM5 DAM4 DACE1 DACE0 D/A Converter Mode Register Internal Bus CHAPTER 16 D/A CONVERTER Configuration...
  • Page 311 (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the value used to determine analog voltage values output to the ANO0 and ANO1 pins, re-spectively. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input sets these registers to 00H.

  • Page 312: D/A Converter Control Registers

    16.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 16-2.

  • Page 313: D/A Converter Operations

    16.4 D/A Converter Operations (1) Select the channel 0 operating mode and channel 1 operating mode with DAM4 and DAM5, respectively, of the D/A converter mode register (DAM). (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to the D/A conversion value setting registers 0 and 1 (DACS0 and DACS1), respectively.

  • Page 314: D/A Converter Cautions

    16.5 D/A Converter Cautions (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins.

  • Page 315: Chapter 17 Serial Interface Channel 0 ( Pd78078 Subseries)

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) The PD78078 Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.

  • Page 316: Serial Interface Channel 0 Functions

    This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). SBI mode complies with the NEC serial bus format. In the SBI mode, transfer data is transmitted/received as one of the three data types: “address”, “command”, or “data”.

  • Page 317: Serial Bus Interface (Sbi) System Configuration Example

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level.

  • Page 318: Serial Interface Channel 0 Configuration

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Register Control register Note Refer to Figure 6-5 Block Diagram of P20, P21, P23 to P26 and Figure 6-6 Block Diagram of P22 and P27.
  • Page 319 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.
  • Page 320 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.

  • Page 321: Serial Interface Channel 0 Control Registers

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...

  • Page 322: Timer Clock Select Register 3 Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) Figure 17-3. Timer Clock Select Register 3 Format Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 Other than above Setting prohibited Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34...
  • Page 323 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.

  • Page 324: Serial Operating Mode Register 0 Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) Figure 17-4. Serial Operating Mode Register 0 Format Symbol <7> <6> <5> CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM...

  • Page 325: Serial Bus Interface Control Register Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 17-5.
  • Page 326 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) Figure 17-5. Serial Bus Interface Control Register Format (2/2) ACKE Acknowledge Signal Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer After completion of transfer ACKD Acknowledge Detection Clear Conditions (ACKD = 0)

  • Page 327: Interrupt Timing Specify Register Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.

  • Page 328: Serial Interface Channel 0 Operations

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode •...

  • Page 329: 3-Wire Serial I/O Mode Operation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
  • Page 330 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.

  • Page 331: Wire Serial I/O Mode Timings

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).

  • Page 332: Circuit Of Switching In Transfer Bit Order

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 333: Sbi Mode Operation

    17.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single-master device and employs the clocked serial I/O format with the addition of a bus configuration function.
  • Page 334 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available.

  • Page 335: Sbi Transfer Timings

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data, “address”, “command”, and “data”. Figure 17-11 shows the address, command, and data transfer timings.

  • Page 336: Bus Release Signal

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device.

  • Page 337: Addresses

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 17-14. Addresses SCK0 SB0 (SB1) Bus Release...

  • Page 338: Commands

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 17-16. Commands SCK0 SB0 (SB1) Command Command Signal Figure 17-17. Data SCK0 SB0 (SB1) Data...

  • Page 339: Acknowledge Signal

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 17-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] SCK0 SB0 (SB1) [When output in synchronization with 9th clock SCK0] SCK0...
  • Page 340 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC) and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Used for bus release signal output.
  • Page 342 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) ACKD Acknowledge Detection Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution. • When CSIE0 = 0 • When RESET input is applied Note BSYE Synchronizing Busy Signal Output Control...
  • Page 343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> SINT SIC SVAM Notes 1. Bit 6 (CLD) is a read-only bit. 2.

  • Page 344: Relt, Cmdt, Reld, And Cmdd Operations (Master)

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (4) Various signals Figures 17-20 to 17-25 show various signals and flag operations in the serial bus interface control register (SBIC). Table 17-3 lists various signals in SBI. Figure 17-20. RELT, CMDT, RELD, and CMDD Operations (Master) SIO0 SCK0 SB0 (SB1)

  • Page 345: Ackt Operation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) Figure 17-22. ACKT Operation SCK0 SB0 (SB1) ACKT Caution Do not set ACKT before termination of transfer. ACK signal is output for a period of one clock just after setting When set during this period...

  • Page 346: Acke Operations

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (a) When ACKE = 1 upon completion of transfer SCK0 SB0 (SB1) ACKE (b) When set after completion of transfer SCK0 SB0 (SB1) ACKE (c) When ACKE = 0 upon completion of transfer SCK0 SB0 (SB1) ACKE...

  • Page 347: Ackd Operations

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) Figure 17-24. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 SIO0 SCK0 SB0 (SB1) ACKD (b) When ACK signal is output after 9th clock of SCK0 SIO0 SCK0 SB0 (SB1)

  • Page 348: Various Signals In Sbi Mode

    Output Signal Name Definition Device Bus release SB0 (SB1) rising edge signal Master when SCK0 = 1 (REL) Command SB0 (SB1) falling edge signal Master when SCK0 = 1 (CMD) Low-level signal to be Acknowledge output to SB0 (SB1) during Master/ signal one-clock period of SCK0...
  • Page 349 Output Signal Name Definition Device Synchronous clock to output address/command/data, ACK signal, synchronous BUSY Serial clock Master signal, etc. Address/ (SCK0) command/data are transferred with the first eight synchronous clocks. 8-bit data to be transferred Address in synchronization with Master (A7 to A0) SCK0 after output of REL and CMD signals...

  • Page 350: Pin Configuration

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ... Serial clock input/output pin <1> Master ... CMOS and push-pull output <2>...
  • Page 351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (6) Address match detection method In the SBI mode, a particular slave device can be selected by transmitting slave address from the master device. Address match detection can be automatically executed by hardware. With slave address register, CSIIF0 is set only when the wake-up function specify bit (WUP) = 1 and the address transmitted from the master device matches the value set to SVA.

  • Page 352: Address Transmission From Master Device To Slave Device (Wup = 1)

    Figure 17-27. Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter) CMDT RELT CMDT Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing CMDD CMDD CMDD Hardware Operation Clear RELD...

  • Page 353: Command Transmission From Master Device To Slave Device

    Figure 17-28. Command Transmission from Master Device to Slave Device Master Device Processing (Transmitter) CMDT Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing CMDD Hardware Operation Write to SIO0 Serial Transmission Command Serial Reception Interrupt Servicing...

  • Page 354: Data Transmission From Master Device To Slave Device

    Figure 17-29. Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing Hardware Operation Write to SIO0 Serial Transmission Data Serial Reception Interrupt Servicing (Preparation for the Next Serial Transfer) INTCSI0...

  • Page 355: Data Transmission From Slave Device To Master Device

    Figure 17-30. Data Transmission from Slave Device to Master Device Master Device Processing (Receiver) Program Processing SCK0 Hardware Operation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY Slave Device processing (Transmitter) Write Program Processing to SIO0 BUSY Hardware Operation Clear FFH Write to SIO0...
  • Page 356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...

  • Page 357: 2-Wire Serial I/O Mode Operation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set 1 to the output latch of P25 and P26 <2>...
  • Page 358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.
  • Page 360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> SINT SVAM Notes 1. Bit 6 (CLD) is a read-only bit. 2.

  • Page 361: Relt And Cmdt Operations

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
  • Page 362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...

  • Page 363: Sck0/P27 Pin Output Manipulation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES) 17.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables setting any value to SCK0 by software (SI0/SB0 and SO0/SB1 pin to be controlled with the RELT and CMDT bits of the serial bus interface control register (SBIC)).
  • Page 364 [MEMO]...

  • Page 365: Chapter 18 Serial Interface Channel 0 ( Pd78078Y Subseries)

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) The PD78078Y Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.

  • Page 366: Serial Interface Channel 0 Functions

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I C (Inter IC) bus mode Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/I of the serial interface channel 0 is enabled.
  • Page 367 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (4) I C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received.

  • Page 368: Serial Interface Channel 0 Configuration

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 18-2. Serial Interface Channel 0 Configuration Item Register Control register Note Refer to Figure 6-7 Block Diagram of P20, P21, P23 to P26 and Figure 6-8 Block Diagram of P22 and P27.

  • Page 369: Serial Interface Channel 0 Block Diagram

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-2. Serial Interface Channel 0 Block Diagram Serial Operating Mode Register 0 CSIM CSIE0 COI WUP BSYE Control Circuit SI0/SB0/ SDA0/P25 PM25 Output Latch Output Control SO0/SB1/ SDA1/P26 PM26 Output Control P26 Output Latch SCK0/...
  • Page 370 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.

  • Page 371: Serial Interface Channel 0 Interrupt Request Signal Generation

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates interrupt request signals according to the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation mode register 0 (CSIM0) bit 5 (WUP), as shown in Table 18-3.

  • Page 372: Serial Interface Channel 0 Control Registers

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...

  • Page 373: Timer Clock Select Register 3 Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Figure 18-3.
  • Page 374 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.

  • Page 375: Serial Operating Mode Register 0 Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-4. Serial Operating Mode Register 0 Format Symbol <7> <6> <5> CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 Input clock to SCK0/SCL pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM...

  • Page 376: Serial Bus Interface Control Register Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 18-5.
  • Page 377 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-5. Serial Bus Interface Control Register Format (2/2) ACKE Acknowledge Signal Output Control Disables acknowledge signal automatic output. (However, output with ACKT is enabled) Used for reception when 8-clock wait mode is selected or for transmission. Enables acknowledge signal automatic output.

  • Page 378: Interrupt Timing Specify Register Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
  • Page 379 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-6. Interrupt Timing Specify Register Format (2/2) SVAM SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 INTCSI0 Interrupt Cause Selection CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer Note 2 SCK0/SCL Pin Level...

  • Page 380: Serial Interface Channel 0 Operations

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode •...

  • Page 381: 3-Wire Serial I/O Mode Operation

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
  • Page 382 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.

  • Page 383: Wire Serial I/O Mode Timings

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).

  • Page 384: Circuit Of Switching In Transfer Bit Order

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 385: 2-Wire Serial I/O Mode Operation

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
  • Page 386 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 387 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.

  • Page 388: Wire Serial I/O Mode Timings

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).

  • Page 389: Relt And Cmdt Operations

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (3) Other signals Figure 18-12 shows RELT and CMDT operations. Figure 18-12. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.

  • Page 390: C Bus Mode Operation

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.4.4 I C bus mode operation The I C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data bus (SDA0 or SDA1) line.

  • Page 391: I 2 C Bus Serial Data Transfer Timing

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (1) I C bus mode functions In the I C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.

  • Page 392: Start Condition

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer.

  • Page 393: Stop Condition

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer.

  • Page 394: Wait Signal

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers.
  • Page 395 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (3) Register setting The I C bus mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 396 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT Use for stop condition output.
  • Page 397 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> <3> SINT SVAM CLC WREL WAT1 WAT0 WAT1 WAT0 Interrupt control by wait...
  • Page 398 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (4) Various signals A list of signals in the I C bus mode is given in Table 18-4. Table 18-4. Signals in I Signal name Description Start condition Definition : Function : Signaled by : Signaled when : Affected flag(s) : CMDD (is set.)

  • Page 399: Pin Configuration

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1>...
  • Page 400 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (6) Address match detection method In the I C mode, the master can select a specific slave device by sending slave address data. Address match detection is performed automatically by the slave device hardware. A slave device address has a slave register (SVA), and compares its contents and the slave address sent from the master device.
  • Page 401 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-22. Example of Communication from Master to Slave (with 9-Clock Wait Selected for Both Master and Slave) (1/3) Processing in master device SIO0 <- address SIO0 write ACKD CMDD RELD BSYE ACKE CMDT...
  • Page 402 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-22. Example of Communication from Master to Slave (with 9-Clock Wait Selected for Both Master and Slave) (2/3) Processing in master device SIO0 <- data SIO0 write ACKD CMDD RELD BSYE ACKE CMDT...
  • Page 403 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-22. Example of Communication from Master to Slave (with 9-Clock Wait Selected for Both Master and Slave) (3/3) Processing in master device SIO0 <- data SIO0 write ACKD CMDD RELD BSYE ACKE CMDT...
  • Page 404 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both Master and Slave) (1/3) Processing in master device SIO0 <- address SIO0 write ACKD CMDD RELD BSYE ACKE CMDT...
  • Page 405 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both Master and Slave) (2/3) Processing in master device SIO0 <- FFH SIO0 write ACKD CMDD RELD BSYE ACKE CMDT...
  • Page 406 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both Master and Slave) (3/3) Processing in master device SIO0 <- FFH SIO0 write ACKD CMDD RELD BSYE ACKE CMDT...
  • Page 407 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (9) Start of transfer A serial transfer is started by setting transfer data in the serial I/O shift register 0 (SIO0) if the following two conditions have been satisfied: • The serial interface channel 0 operation control bit (CSIE0) = 1. •...

  • Page 408: Cautions On Use Of I C Bus Mode

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.4.5 Cautions on use of I C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal.

  • Page 409: Slave Wait Release (Transmission)

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (2) Slave wait release (slave transmission) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line.

  • Page 410: Slave Wait Release (Reception)

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (3) Slave wait release (slave reception) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction. When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write to SIO0, the slave may not receive the first bit of the data sent from the master.

  • Page 411: Restrictions In I C Bus Mode

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.4.6 Restrictions in I C bus mode The following restrictions apply to the PD78078Y Subseries. • Restrictions when used as slave device in I Applicable models PD78076Y, 78078Y, 78P078Y, and IE-78078-R-EM Description When the wake-up function is executed (by setting the WUP flag (bit 5 of the serial operation mode register 0 (CSIM0)) in the serial transfer status...
  • Page 412 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) • Example of program releasing serial transfer status SET1 P2.5 ; <1> SET1 PM2.5 ; <2> SET1 PM2.7 ; <3> CLR1 CSIE0 ; <4> SET1 CSIE0 ; <5> SET1 RELT ; <6> CLR1 PM2.7 ;...

  • Page 413: Sck0/Scl/P27 Pin Output Manipulation

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) 18.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin enables static output by manipulating software in addition to normal serial clock output. The value of serial clocks can be set by software (SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)).

  • Page 414: Sck0/Scl/P27 Pin Configuration

    CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries) (2) In I C bus mode The SCK0/SCL/P27 pin output level is manipulated by the CLC bit of interrupt timing specify register (SINT). <1> Set serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation is enabled).

  • Page 415: Chapter 19 Serial Interface Channel 1

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.

  • Page 416: Serial Interface Channel 1 Configuration

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 19-1. Serial Interface Channel 1 Configuration Item Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Control register Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1)
  • Page 417 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.

  • Page 418: Serial Interface Channel 1 Control Registers

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) •...

  • Page 419: Serial Operation Mode Register 1 Format

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop, and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.

  • Page 420: Automatic Data Transmit/Receive Control Register Format

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, and error check enable/disable, and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 421: Automatic Data Transmit/Receive Interval Specify Register Format

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 19-5.
  • Page 422 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
  • Page 423 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 Data Transfer Interval Control No control of interval by ADTI Control of interval by ADTI (ADTI0 to ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Notes 1.
  • Page 424 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).

  • Page 425: Serial Interface Channel 1 Operations

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 19.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.

  • Page 426: 3-Wire Serial I/O Mode Operation

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1).

  • Page 427: Wire Serial I/O Mode Timings

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock SCK1.

  • Page 428: Circuit Of Switching In Transfer Bit Order

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-7. Circuit of Switching in Transfer Bit Order Internal Bus LSB-first MSB-first Shift Register 1 (SIO1) SCK1 Start bit switching is realized by switching the bit order write to SIO1. The SIO1 shift order remains unchanged.

  • Page 429: 3-Wire Serial I/O Mode Operation With Automatic Transmit/Receive Function

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
  • Page 430 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Symbol <7> <6> <5> <4> <3> ADTC ARLD ERCE ERR TRF STRB Notes 1.
  • Page 431 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0...
  • Page 432 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f is 2/f Minimum = (n + 1)
  • Page 433 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 Data Transfer Interval Control No control of interval by ADTI Control of interval by ADTI (ADTI0 to ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Notes 1. The interval is dependent only on CPU processing. 2.
  • Page 434 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f is 2/f Minimum = (n + 1)
  • Page 435 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address.

  • Page 436: Basic Transmission/Reception Mode Operation Timings

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.

  • Page 437: Basic Transmission/Reception Mode Flowchart

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-9. Basic Transmission/Reception Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
  • Page 438 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 19-10 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
  • Page 439 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-10. Buffer RAM Operation in 6-byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception FADFH FAC5H Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6)

  • Page 440: Basic Transmission Mode Operation Timings

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.

  • Page 441: Basic Transmission Mode Flowchart

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-12. Basic Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
  • Page 442 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 0, RE = 0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 19-13 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.

  • Page 443: Buffer Ram Operation In 6-Byte Transmission (In Basic Transmit Mode)

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-13. Buffer RAM Operation in 6-byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point FADFH Transmit data 1 (T1) FAC5H Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6)

  • Page 444: Repeat Transmission Mode Operation Timing

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1).

  • Page 445: Repeat Transmission Mode Flowchart

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-15. Repeat Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
  • Page 446 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 19-16 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.

  • Page 447: Buffer Ram Operation In 6-Byte Transmission (In Repeat Transmit Mode)

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-16. Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes FADFH FAC5H Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H...

  • Page 448: Automatic Transmission/Reception Suspension And Restart

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0, it is suspended upon completion of 8-bit data transfer.

  • Page 449: System Configuration When The Busy Control Option Is Used

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving. (a) Busy control option Busy control is a function which causes the master device’s serial transmission to wait when the slave device outputs a busy signal to the master device, and maintain the wait state while that busy signal...

  • Page 450: Operation Timings When Using Busy Control Option (Busy0 = 0)

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-19. Operation Timings when Using Busy Control Option (BUSY0 = 0) SCK1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY CSIIF1 Caution When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1 : Interrupt request flag : Bit 3 of the automatic data transmit/receive control register (ADTC) If the busy signal becomes inactive, the wait is canceled.

  • Page 451: Busy Signal And Wait Cancel (Busy0 = 0)

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-20. Busy Signal and Wait Cancel (BUSY0 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY In the case where the busy (Active High) signal becomes inactive directly when sampled (b) Busy &...

  • Page 452: Operation Timings When Using Busy & Strobe Control Option (Busy0 = 0)

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) SCK1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY CSIIF1 Caution When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1: Interrupt request flag : Bit 3 of the automatic data transmit/receive control register (ADTC) D7 D6 D5 D4 D3 D2 D1 D0...
  • Page 453 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Bit slippage detection function through the busy signal During an automatic transmit/receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the strobe control option is not used, this bit slippage will have an effect on sending of the next byte.

  • Page 454: Automatic Data Transmit/Receive Interval

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in the automatic transmit/receive interval specification register (ADTI) and the CPU processing...

  • Page 455: Operation Timing With Automatic Data Transmit/Receive Function Performed By Internal Clock

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the automatic transmit/receive function is operated by the internal clock, interval timing by CPU processing is as follows.

  • Page 456: Interval Timing Through Cpu Processing (When The External Clock Is Operating)

    CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is cleared to 0, external clock operation is set. When the automatic transmit/receive function is used by the external clock, it must be selected so that the interval may be longer than the values shown as follows.

  • Page 457: Chapter 20 Serial Interface Channel 2

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.

  • Page 458: Serial Interface Channel 2 Configuration

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 20-1. Serial Interface Channel 2 Configuration Item Register Control register Note Refer to Figure 6-15 Block Diagram of P70 and Figure 6-16 Block Diagram of P71 and P72.

  • Page 459: Baud Rate Generator Block Diagram

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-2. Baud Rate Generator Block Diagram CSIE2 Terminal Clock Receive Clock Start Bit Detection Start Bit Sampling Clock 5-Bit Counter Match MDL0 to MDL3 Decoder Match 5-Bit Counter TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register Internal Bus...
  • Page 460 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation.

  • Page 461: Serial Interface Channel 2 Control Registers

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status Register (ASIS) •...

  • Page 462: Asynchronous Serial Interface Mode Register Format

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.

  • Page 463: Serial Interface Channel 2 Operating Mode Settings

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Table 20-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72 TXE RXE SCK CSIE2 CSIM22 CSCK Other than above (2) 3-wire Serial I/O Mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72...

  • Page 464: Asynchronous Serial Interface Status Register Format

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 1-bit or 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS are undefined.

  • Page 465: Baud Rate Generator Control Register Format

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 20-6. Baud Rate Generator Control Register Format (1/2) Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0...
  • Page 466 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-6. Baud Rate Generator Control Register Format (2/2) TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation.

  • Page 467: Relationship Between Main System Clock And Baud Rate

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock.
  • Page 468 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = 2 x (k + 16)

  • Page 469: Serial Interface Channel 2 Operation

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 20.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
  • Page 470 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol <7> <6> ASIM Address After Reset ISRM SCK FF70H Receive Operation Control Receive operation stopped Receive operation enabled...

  • Page 471: Asynchronous Serial Interface (Uart) Mode

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
  • Page 472 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol <7> <6> ASIM Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port.
  • Page 473 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with an 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. Symbol ASIS Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read.
  • Page 474 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0 Other than above Address...
  • Page 475 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1.

  • Page 476: Relationship Between Main System Clock And Baud Rate

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock.
  • Page 477 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = where, : Frequency of clock input to ASCK pin...

  • Page 478: Asynchronous Serial Interface Transmit/Receive Data Format

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is shown in Figure 20-7. Figure 20-7. Asynchronous Serial Interface Transmit/Receive Data Format Start One data frame consists of the following bits. • Start bit ... 1 bit •...
  • Page 479 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.

  • Page 480: Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated.

  • Page 481: Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. When the RxD pin input becomes low, the 5-bit counter of baud rate generaor (see Figure 20-2) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output.

  • Page 482: Receive Error Timing

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. If the data reception result error flag is set in the asynchronous serial interface status register (ASIS), a receive error interrupt request (INTSER) is generated.

  • Page 483: State Of Receive Buffer Register (Rxb) When Receive Operation Is Stopped And Whether Interrupt Request (Intsr) Is Generated Or Not

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When transmit operation is stopped by clearing (0) bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1, before executing the next transmission.

  • Page 484: 3-Wire Serial I/O Mode

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
  • Page 485 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. Symbol <7>...
  • Page 486 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 : 5-bit counter source clock : Value set in MDL0 to MDL3 (0 Address...
  • Page 487 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1.
  • Page 488 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC Setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 through TPS3.

  • Page 489: Wire Serial I/O Mode Timing

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock (SCK2).

  • Page 490: Circuit Of Switching In Transfer Bit Order

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 20-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 491: Restrictions On Using Uart Mode

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.4 Restrictions on using UART mode In the UART mode, a receive completion interrupt request (INTSR) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (INTSER). Thereby, the phenomenon shown below may occur.

  • Page 492: Period That Reading Receive Buffer Register Is Prohibited

    CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-15. Period that Reading Receive Buffer Register is Prohibited RxD (input) START INTSR INTSER (when framing or overrun error is generated) INTSER (when parity error is generated) T1 : The amount of time for one unit of data sent in the baud rate selected with the baud rate generator control register (BRGC) (1/baud rate) T2 : The amount of time for 2 clocks of 5-bit counter source clock (f BRGC...
  • Page 493 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 [Example] Main processing INTSER is generated 7 clocks (MIN.) of CPU clock (time from interrupt request to servicing) UART receive error interrupt request (INTSER) servicing Instructions for 2205 clocks (MIN.) of CPU clock are required.
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  • Page 495: Chapter 21 Real-Time Output Port

    CHAPTER 21 REAL-TIME OUTPUT PORT 21.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally. This is called the real-time output function.

  • Page 496: Real-Time Output Buffer Register Configuration

    CHAPTER 21 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the special function register (SFR) area as shown in Figure 21-2. When specifying 4 bits x 2 channels as the operating mode, data are set individually in RTBL and RTBH. When specifying 8 bits x 1 channel as the operating mode, data are set to both RTBL and RTBH by writing 8-bit data to either RTBL or RTBH.

  • Page 497: Real-Time Output Port Control Registers

    CHAPTER 21 REAL-TIME OUTPUT PORT 21.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output mode of port 12 pins (P120 to P127) which also function as real-time output pins (RTP0 to RTP7).

  • Page 498: Real-Time Output Port Control Register Format

    CHAPTER 21 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 21-3 shows the relationship between the real-time output port operating mode and output trigger. RTPC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

  • Page 499: Chapter 22 Interrupt Functions

    CHAPTER 22 INTERRUPT FUNCTIONS 22.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.

  • Page 500: Interrupt Sources And Configuration

    22.2 Interrupt Sources and Configuration There are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources (see Table 22-1). Table 22-1. Interrupt Source List (1/2) Interrupt Default Type Priority Note 1 Name Non- – INTWDT maskable INTWDT INTP0 INTP1 INTP2...
  • Page 501 CHAPTER 22 INTERRUPT FUNCTIONS Table 22-1. Interrupt Source List (2/2) Interrupt Default Note 1 Type Priority Name Reference time interval signal from INTTM3 watch timer Generation of 16-bit timer register, INTTM00 capture/compare register (CR00) match signal Generation of 16-bit timer register, INTTM01 capture/compare register (CR01) match signal...

  • Page 502: Basic Configuration Of Interrupt Function

    Figure 22-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Interrupt Request (B) Internal maskable interrupt Interrupt Request (C) External maskable interrupt (INTP0) Sampling Clock External Interrupt Mode Select Register Register (INTM0) (SCS) Sampling Edge Interrupt Clock Detector Request CHAPTER 22 INTERRUPT FUNCTIONS Internal Bus...
  • Page 503 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) External Interrupt Mode Register (INTM0, INTM1) Interrupt Edge Request Detector (E) Software interrupt Interrupt Priority Control Request Circuit Interrupt request flag Interrupt enable flag ISP : Inservice priority flag MK :...

  • Page 504: Interrupt Function Control Registers

    22.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...

  • Page 505: Interrupt Request Flag Register Format

    CHAPTER 22 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.

  • Page 506: Interrupt Mask Flag Register Format

    (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.

  • Page 507: Priority Specify Flag Register Format

    CHAPTER 22 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.

  • Page 508: External Interrupt Mode Register 0 Format

    (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP6. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 22-5. External Interrupt Mode Register 0 Format Symbol INTM0 ES31...

  • Page 509: External Interrupt Mode Register 1 Format

    CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-6. External Interrupt Mode Register 1 Format Symbol INTM1 ES71 ES70 ES61 ES60 ES51 After Address Reset ES50 ES41 ES40 FFEDH ES41 ES40 Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 ES50 Falling edge Rising edge...

  • Page 510: Sampling Clock Select Register Format

    (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction.

  • Page 511: Noise Eliminator Input/Output Timing (During Rising Edge Detection)

    CHAPTER 22 INTERRUPT FUNCTIONS When the setting INTP0 input level is active twice in succession, the noise eliminator sets interrupt request flag (PIF0) to 1. Figure 22-8 shows the noise eliminator input/output timing. Figure 22-8. Noise Eliminator Input/Output Timing (during Rising Edge Detection) (a) When input is less than the sampling cycle (t Sampling Clock INTP0...

  • Page 512: Program Status Word Format

    (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped.

  • Page 513: Interrupt Servicing Operations

    22.4 Interrupt Servicing Operations 22.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, PSW and PC, in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched.

  • Page 514: Flowchart From Non-Maskable Interrupt Generation To Acknowledge

    Figure 22-10. Flowchart from Non-Maskable Interrupt Generation to Acknowledge (with watchdog timer mode selected)? Overflow in WDT? (with non-maskable interrupt selected)? Interrupt request generation WDT interrupt servicing? register unaccessed? WDTM : Watchdog timer mode register : Watchdog timer Figure 22-11. Non-Maskable Interrupt Request Acknowledge Timing CPU Instruction Instruction TMIF4...

  • Page 515: Non-Maskable Interrupt Request Acknowledge Operation

    CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-12. Non-Maskable Interrupt Request Acknowledge Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1> NMI Request <2> 1 Instruction Execution If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1>...

  • Page 516: Maskable Interrupt Request Acknowledge Operation

    22.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).

  • Page 517: Interrupt Request Acknowledge Processing Algorithm

    CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-13. Interrupt Request Acknowledge Processing Algorithm Interrupt request reserve Any high- priority interrupt among simultaneously generated xxPR = 0 interrupt requests? Interrupt request reserve IE = 1? Interrupt request reserve Vectored interrupt servicing xxIF : Interrupt request flag xxMK : Interrupt mask flag xxPR : Priority specify flag : Flag to control maskable interrupt request acknowledge...

  • Page 518: Software Interrupt Request Acknowledge Operation

    Figure 22-14. Interrupt Request Acknowledge Timing (Minimum Time) CPU Processing Instruction xxIF (xxPR = 1) xxIF (xxPR = 0) Remark 1 clock: Figure 22-15. Interrupt Request Acknowledge Timing (Maximum Time) CPU Processing Instruction xxIF (xxPR = 1) xxIF (xxPR = 0) Remark 1 clock: 22.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution.

  • Page 519: Multiple Interrupt Servicing

    22.4.4 Multiple interrupt servicing A multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt. A multiple interrupt is generated only in the interrupt request acknowledge enable state (IE = 1) (except non- maskable interrupt). As soon as an interrupt request is acknowledged, it enters the acknowledge disable state (IE = 0).

  • Page 520: Multiple Interrupt Example

    Figure 22-16. Multiple Interrupt Example (1/2) Example 1. Two multiple interrupts generated Main Processing (PR = 0) INTxx (PR = 1) During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a multiple interrupt is generated. acknowledge, and the interrupt request acknowledge enable state is set. Example 2.
  • Page 521 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-16. Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupts are not enabled Main Processing IE = 0 INTxx (PR = 0) 1 Instruction Execution Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated.

  • Page 522: Interrupt Request Reserve

    22.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interupt request is generated during the execution. The following shows such instructions (interrupt request reserve instruction). •...

  • Page 523: Test Functions

    22.5 Test Functions In this function, when the watch timer overflows and when a rising edge of port 4 is detected, the corresponding test input flag is set (1), and a standby release signal is generated. Unlike the interrupt function, vectored processing is not performed. There are two test input factors as shown in Table 22-5.

  • Page 524: Format Of Interrupt Request Flag Register 1L

    (1) Interrupt request flag register 1L (IF1L) It indicates whether a clock timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 22-19.

  • Page 525: Test Input Signal Acknowledge Operation

    (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 22-21.
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  • Page 527: Chapter 23 External Device Expansion Function

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. The external device expansion function can be used in the following two modes: •...

  • Page 528: Pin Functions In Separate Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION (2) Separate bus mode External devices are connected using independent address and data buses. This connection requires no latches externally, resulting in reduction of external parts and area on the mounting board. In this mode, ports 4 through 6 and port 8 are used for control of address/data, reafd/write strobe, wait as shown below.

  • Page 529: Memory Map When Using External Device Expansion Function

    Memory maps when using the external device expansion function are as follows. Figure 23-1. Memory Map when Using External Device Expansion Function (1/2) (a) Memory map of PD78076, 78076Y, and of PD78P078, 78P078Y when internal PROM capacity is 48 Kbytes...
  • Page 530 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-1. Memory Map when Using External Device Expansion Function (2/2) (b) Memory map of PD78078, 78078Y, 78P078, 78P078Y when internal ROM capacity (PROM) is 56 Kbytes FFFFH FF00H FEFFH Internal High-Speed RAM FB00H FAFFH Reserved FAE0H...

  • Page 531: External Device Expansion Function Control Register

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and internal memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and also sets the input/output of port 4.

  • Page 532: Internal Memory Size Switching Register Format

    ROM3 Notes 1. The values after reset depend on the product. (See Table 23-5) Table 23-5. Values when the Internal Memory Size Switching Register is Reset PD78076, 78076Y PD78078, 78078Y PD78P078, 78P078Y 2. When using the external device expansion function in the PD78078, 78078Y, 78P078, and 78P078Y set the internal ROM size to 56 Kbytes.

  • Page 533: External Bus Type Select Register Format

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION (3) External bus type select register (EBTS) This register sets the operation mode of the external device expansion function. When the multiplexed bus mode is selected, the P80/A0 through P87/A7 pins can be used as an I/O port. It is set by an 8-bit memory manipulation instruction.

  • Page 534: External Device Expansion Function Timing

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.3 External Device Expansion Function Timing 23.3.1 Timings in multiplexed bus mode Timing control signal output pins in the multiplexed bus mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory.

  • Page 535: Instruction Fetch From External Memory In Multiplexed Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-5. Instruction Fetch from External Memory in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting ASTB AD0 to AD7 Lower Address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower Address...

  • Page 536: External Memory Read Timing In Multiplexed Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-6. External Memory Read Timing in Multiplexed Bus Mode ASTB AD0 to AD7 A8 to A15 ASTB AD0 to AD7 A8 to A15 Internal Wait Signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting ASTB AD0 to AD7 A8 to A15...

  • Page 537: External Memory Write Timing In Multiplexed Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-7. External Memory Write Timing in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting ASTB AD0 to AD7 Lower Address A8 to A15 ASTB Lower Address AD0 to AD7 A8 to A15 Internal Wait Signal (1-clock wait)

  • Page 538: External Memory Read Modify Write Timing In Multiplexed Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-8. External Memory Read Modify Write Timing in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z AD0 to AD7 Lower Address Read Data Write Data A8 to A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB...

  • Page 539: Timings In Separate Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.3.2 Timings in separate bus mode Timing control signal output pins in the separate bus mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory.

  • Page 540: Instruction Fetch From External Memory In Separate Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-9. Instruction Fetch from External Memory in Separate Bus Mode Note ASTB AD0 to AD7 A0 to A7 A8 to A15 Note ASTB AD0 to AD7 A0 to A7 A8 to A15 Internal Wait Signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting Note...

  • Page 541: External Memory Read Timing In Separate Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-10. External Memory Read Timing in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting Note ASTB AD0 to AD7 A0 to A7 A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting Note ASTB AD0 to AD7...

  • Page 542: External Memory Write Timing In Separate Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-11. External Memory Write Timing in Separate Bus Mode Note ASTB AD0 to AD7 Lower Address A0 to A7 A8 to A15 Note ASTB Lower Address AD0 to AD7 A0 to A7 A8 to A15 Internal Wait Signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting...

  • Page 543: External Memory Read Modify Write Timing In Separate Bus Mode

    CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-12. External Memory Read Modify Write Timing in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting Note ASTB AD0 to AD7 Lower Address A0 to A7 A8 to A15 Note ASTB Lower Address...
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  • Page 545: Chapter 24 Standby Function

    CHAPTER 24 STANDBY FUNCTION 24.1 Standby Function and Configuration 24.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.

  • Page 546: Standby Function Control Register

    24.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.

  • Page 547: Standby Function Operations

    24.2 Standby Function Operations 24.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 24-1.

  • Page 548: Halt Mode Released By Interrupt Request Generation

    (2) HALT mode release The HALT mode can be released with the following four types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is generated to release the HALT mode. If interrupt request acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction is executed. Figure 24-2.

  • Page 549: Halt Mode Released By Reset Input

    CHAPTER 24 STANDBY FUNCTION (d) Release by RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 24-3. HALT Mode Released by RESET Input HALT Instruction RESET Signal Operating Mode HALT Mode...

  • Page 550: Stop Mode

    24.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V resistor to minimize leakage current at the crystal oscillator.

  • Page 551: Stop Mode Released By Interrupt Request Generation

    CHAPTER 24 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released with the following three types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode. If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.

  • Page 552: Stop Mode Released By Reset Input

    (c) Release by RESET input The STOP mode is released and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 24-5. STOP Mode Released by RESET Input STOP Instruction RESET Signal Operating Mode Oscillation Clock Remarks 1. f : Main system clock oscillation frequency 2.

  • Page 553: Chapter 25 Reset Function

    CHAPTER 25 RESET FUNCTION 25.1 Reset Function The following two operations are available to generate the reset signal. External reset input with RESET pin Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.

  • Page 554: Timing Of Reset By Reset Input

    Figure 25-2. Timing of Reset by RESET Input Normal Operation RESET Internal Reset Signal Port Pin Figure 25-3. Timing of Reset due to Watchdog Timer Overflow Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin Figure 25-4. Timing of Reset by RESET Input in STOP Mode STOP Instruction Execution Normal Operation RESET...

  • Page 555: Hardware Status After Reset

    All other hardware statuses remains unchanged after reset. 2. In the standby mode, the status before the reset is held even after the reset. 3. The values after reset depend on the product. PD78076, 78076Y : CCH PD78P078, 78P078Y : CFH CHAPTER 25 RESET FUNCTION...
  • Page 556 Table 25-1. Hardware Status after Reset (2/3) Hardware 8-bit timer/event counters Timer register (TM5, TM6) 5 and 6 Compare register (CR50, CR60) Clock select register (TCL5, TCL6) Mode control register (TMC5, TMC6) Watch timer Mode control register (TMC2) Clock select register (TCL2) Watchdog timer Mode register (WDTM) Serial interface...
  • Page 557 Table 25-1. Hardware Status after Reset (3/3) Hardware Interrupt Request flag register (IF0L, IF0H, IF1L) Mask flag register (MK0L, MK0H, MK1L) Priority specify flag register (PR0L, PR0H, PR1L) External interrupt mode register (INTM0, INTM1) Key return mode register (KRM) Sampling clock select register (SCS) CHAPTER 25 RESET FUNCTION Status after Reset...
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  • Page 559: Chapter 26 Rom Correction

    CHAPTER 26 ROM CORRECTION 26.1 ROM Correction Functions The PD78078, 78078Y Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction.

  • Page 560: Correction Address Registers 0 And 1 Format

    (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1.

  • Page 561: Rom Correction Control Registers

    26.3 ROM Correction Control Registers The ROM correction is controlled with the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. The correction control register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1).

  • Page 562: Rom Correction Application

    26.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to CORAD0 or CORAD1 generates the correction branch.

  • Page 563: Initialization Routine

    CHAPTER 26 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 26-6 to correct the program. Figure 26-6. Initialization Routine ROM correction Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Note Whether the ROM correction is used or not should be judged by the port input level.

  • Page 564: Rom Correction Operation

    CHAPTER 26 ROM CORRECTION Figure 26-7. ROM Correction Operation Start of internal ROM program Does fetch address match with correction address? ROM correction Set correction status flag Correction branch (branch to address F7FDH) Execution of correction program...

  • Page 565: Rom Correction Example

    26.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 26-8. ROM Correction Example Internal ROM 0000H 0080H Program start 1000H ADD A, #1 MOV B, A 1002H (1) Branches to address F7FDH when the preset value 1000H in the correction address register matches the...

  • Page 566: Program Execution Flow

    26.6 Program Execution Flow Figures 26-9 and 26-10 show the program transition diagrams when the ROM correction is used. Figure 26-9. Program Transition Diagram (when One Place is Corrected) FFFFH F7FFH F7FDH JUMP xxxxH 0000H (1) Branches to address F7FDH when fetch address matches correction address (2) Branches to correction program (3) Returns to internal ROM program Remark Area filled with diagonal lines : Internal expansion RAM...

  • Page 567: Program Transition Diagram (When Two Places Are Corrected)

    CHAPTER 26 ROM CORRECTION Figure 26-10. Program Transition Diagram (when Two Places are Corrected) FFFFH F7FFH BR !JUMP F7FDH Correction program 2 yyyyH Correction program 1 xxxxH Destination judge program JUMP Internal ROM Correction place 2 Internal ROM Correction place 1 Internal ROM 0000H (1) Branches to address F7FDH when fetch address matches correction address...

  • Page 568: Cautions On Rom Correction

    26.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag (COREN0, COREN1) is 0 (when the correction branch is in disabled state).

  • Page 569: Chapter 27 Pd78P078, 78P078Y

    ROM version, be sure to conduct sufficient evaluations for the consumer samples (not engineering samples) of the mask ROM version. PD78P078, 78P078Y PD78P078, 78P078Y Mask ROM Versions One-time PROM/EPROM Mask ROM 60 Kbytes PD78076, 78076Y: 48 Kbytes PD78078, 78078Y: 60 Kbytes Note 1 Note 2 None Available Available None...

  • Page 570: Internal Memory Size Switching Register

    FFF0H ROM2 ROM1 ROM0 ROM3 ROM2 ROM1 Other than above RAM2 RAM1 RAM0 Other than above IMS Setting PD78076, 78076Y PD78078, 78078Y After Reset ROM0 Internal ROM Capacity Selection 48 Kbytes Note 56 Kbytes 60 Kbytes Setting prohibited Internal High-Speed RAM Capacity Selection...

  • Page 571: Internal Extension Ram Size Switching Register

    The IXS is set by an 8-bit memory manipulation instruction. RESET signal input sets IXS to 0AH. Caution When the PD78076, 78078, 78076Y, or 78078Y is used, be sure to set the value specified in Table 27-3 to IXS. Other settings are prohibited.

  • Page 572: Prom Programming

    27.3 PROM Programming The PD78P078 and 78P078Y each incorporate a 60-Kbyte PROM as program memory. To write a program into the PROM make the device enter the PROM programming mode by setting the levels of the V pins as specified. For the connection of unused pins, refer to 1.5 (2) PROM programming mode and 2.5 Pin Configuration (Top Vew).
  • Page 573 CHAPTER 27 (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.

  • Page 574: Prom Write Procedure

    27.3.2 PROM write procedure Figure 27-3. Page Program Mode Flowchart Address = Address + 1 Pass CHAPTER 27 PD78P078, 78P078Y Start Address = G = 6.5 V, V = 12.5 V G = Start address X = 0 N = Last address of program Latch Address = Address + 1 Latch...

  • Page 575: Page Program Mode Timing

    CHAPTER 27 Figure 27-4. Page Program Mode Timing Page Data Latch A2 to A16 A0, A1 D0 to D7 Data Input + 1.5 PD78P078, 78P078Y Page Program Program Verify Hi-Z Data Output...

  • Page 576: Byte Program Mode Flowchart

    Figure 27-5. Byte Program Mode Flowchart Address = Address + 1 Pass CHAPTER 27 PD78P078, 78P078Y Start Address = G G = Start address N = Last address of program = 6.5 V, V = 12.5 V X = 0 X = X + 1 0.1 ms program pulse Fail...

  • Page 577: Byte Program Mode Timing

    CHAPTER 27 Figure 27-6. Byte Program Mode Timing Program A0 to A16 Data Input D0 to D7 + 1.5 Cautions 1. Apply V before applying V 2. V must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied to V may have an adverse affect on reliability.

  • Page 578: Prom Reading Procedure

    27.3.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V programming mode and 2.5 Pin Configuration (Top View). (2) Supply +5 V to the V and V (3) Input address of data to be read to pins A0 through A16.

  • Page 579: Erasure Procedure ( Pd78P078Kl-T And 78P078Ykl-T Only)

    27.6 Screening of One-Time PROM Versions One-time PROM versions cannot be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore, after users have written data to the PROM, screening should be implemented: that is, store devices under the following conditions.
  • Page 580 [MEMO]...

  • Page 581: Chapter 28 Instruction Set

    CHAPTER 28 INSTRUCTION SET This chapter describes each instruction set of the PD78078 and 78078Y Subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 Series USER’S MANUAL — Instructions (U12326E).”...

  • Page 582: Legends Used In Operation List

    28.1 Legends Used in Operation List 28.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.

  • Page 583: Description Of "Operation" Column

    28.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter...

  • Page 584: Operation List

    28.2 Operation List Instruction Mnemonic Operands Group 8-bit data r, #byte transfer saddr, #byte sfr, #byte Note 3 A, r Note 3 r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A...
  • Page 585 Instruction Mnemonic Operands Group 16-bit data MOVW rp, #word transfer saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX Note 3 AX, rp Note 3 rp, AX AX, !addr16 !addr16, AX Note 3 XCHW AX, rp 8-bit A, #byte operation saddr, #byte...
  • Page 586 Instruction Mnemonic Operands Group 8-bit A, #byte operation saddr, #byte Note 3 A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] SUBC A, #byte saddr, #byte Note 3 A, r r, A A, saddr...
  • Page 587 Instruction Mnemonic Operands Group 8-bit A, #byte operation saddr, #byte Note 3 A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte Note 3 A, r r, A A, saddr...
  • Page 588 Instruction Mnemonic Operands Group 16-bit ADDW AX, #word operation SUBW AX, #word CMPW AX, #word Multiply MULU divide DIVUW Increment decrement saddr saddr INCW DECW Rotate A, 1 A, 1 RORC A, 1 ROLC A, 1 ROR4 [HL] ROL4 [HL] ADJBA adjust ADJBS...
  • Page 589 Instruction Mnemonic Operands Group Bit mani- AND1 CY, saddr.bit pulation CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW. bit CY, [HL].bit SET1 saddr.bit sfr.bit...
  • Page 590 Instruction Mnemonic Operands Group Call / CALL !addr16 return CALLF !addr11 CALLT [addr5] RETI RETB Stack PUSH manipulate MOVW SP, #word SP, AX AX, SP Uncondi- !addr16 tional $addr16 branch Conditional BC $addr16 branch $addr16 $addr16 $addr16 Notes 1. For instructions that access the internal high-speed RAM area or perform no data access 2.
  • Page 591 Instruction Mnemonic Operands Group Conditional BT saddr.bit, $addr16 branch sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 BTCLR saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 DBNZ B, $addr16 C, $addr16 saddr.

  • Page 592: Instructions Listed By Addressing Type

    28.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ CHAPTER 28 INSTRUCTION SET...
  • Page 593 Second Operand #byte Note First Operand MOV MOV MOV MOV MOV MOV MOV MOV ADDC SUBC ADDC SUBC MOV MOV ADDC SUBC B, C MOV MOV saddr MOV MOV ADDC SUBC !addr16 MOV MOV [DE] [HL] [HL + byte] [HL + B] [HL + C] Note Except when “r = A”...
  • Page 594 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word 1st Operand ADDW SUBW CMPW MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand...
  • Page 595 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction Compound instruction (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP CHAPTER 28 INSTRUCTION SET !addr16 !addr11 [addr5]...
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  • Page 597: Appendix A Differences Between Pd78078, 78075B Subseries, And Pd78070A

    Part Number Item Anti-EMI noise measure Not provided Product equipped with I C bus Available Supply voltage Internal ROM size PD78076 PD78078, 78P078 Internal expansion RAM size 1024 bytes I/O port Total CMOS input CMOS I/O N-ch open-drain I/O Pins with...
  • Page 598 [MEMO]...

  • Page 599: Appendix B Development Tools

    APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the PD78078 and 78078Y Subseries. Figure B-1 shows the configuration example of the tools.

  • Page 600: B-1 Development Tool Configuration

    Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Language processing software • Assembler package • C compiler package • C library source file • Device file PROM programming tool • PG-1500 controller PROM programming environment PROM programmer Programmer adapter...
  • Page 601 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A Language processing software • Assembler package • C compiler package • C library source file • Device file PROM programming tool PROM programming environment PROM programmer Programmer...

  • Page 602: Language Processing Software

    B.1 Language Processing Software RA78K/0 Assembler Package CC78K/0 C Compiler Package DF78078 Note Device File CC78K/0-L C Library Source File Note The DF78078 can commonly be used for all the products of the RA78K/0, CC78K/0, SM78K0, ID78K0-NS, and ID78K0. APPENDIX B DEVELOPMENT TOOLS A program that converts a program written in mnemonic into object codes that microcomputers can process.
  • Page 603 APPENDIX B DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx RA78K0 Sxxxx CC78K0 Sxxxx DF78078 Sxxxx CC78K0-L xxxx Host Machine AA13 PC-9800 series AB13 IBM PC/AT™ and BB13 compatibles 3P16 HP9000 series 700™...

  • Page 604: Prom Writing Tools

    B.2 PROM Writing Tools B.2.1 Hardware PG-1500 PROM Programmer PA-78P078GC PA-78P078GF PA-78P078KL-T PROM Programmer Adapter B.2.2 Software PG-1500 Controller Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx PG1500 xxxx 5A13 PC-9800 series 5B13 IBM PC/AT and compatibles...

  • Page 605: Debugging Tools

    B.3 Debugging Tools B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS IE-78K0-NS Note In-circuit Emulator IE-70000-MC-PS-B Power Supply Adapter Note IE-70000-98-IF-C Interface Adapter IE-70000-CD-IF Note PC Card Interface IE-70000-PC-IF-C Note Interface Adapter IE-78078-NS-EM1 Note Emulation Board NP-100GC Emulation Probe TGC-100SDW Conversion Adapter (refer to Figure B-2)
  • Page 606 B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A IE-78001-R-A Note In-circuit Emulator IE-70000-98-IF-B or IE-70000-98- Note IF-C Interface Adapter IE-70000-PC-IF-B or IE-70000-PC- IF-C Note Interface adapter IE-78000-R-SV3 Interface Adapter IE-78078-NS-EM1 Note Emulation Board IE-78K0-R-EX1 Note Emulation Probe Conversion Board IE-78078-R-EM Emulation board EP-78064GC-R...

  • Page 607: Software

    B.3.2 Software (1/2) SM78K0 System Simulator Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx SM78K0 xxxx AA13 PC-9800 series AB13 IBM PC/AT and BB13 compatible Note Does not support WindowsNT. APPENDIX B DEVELOPMENT TOOLS Capable of debugging in C source level or assembler level while simulating the operation of the target system on the host machine.
  • Page 608 B.3.2 Software (2/2) Note ID78K0-NS Integrated debugger (supporting in-circuit emulator IE-78K0-NS) ID78K0 Integrated Debugger (supporting in-circuit emulator IE-78001-R-A) Note Under development Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx ID78K0-NS xxxx AA13 PC-9800 series AB13 IBM PC/AT and...

  • Page 609: Os For Ibm Pc

    Table B-2. System Upgrading from Former-type In-circuit Emulator for 78K/0 Series to IE-78001-R-A In-circuit Unit Owned IE-78000-R IE-78000-R-A Note To system up-grade the enclosure, the unit must be brought to NEC. APPENDIX B DEVELOPMENT TOOLS Table B-1. OS for IBM PC Version Ver. 5.02 to Ver. 6.3 J6.1/V...

  • Page 610: B-2 Tgc-100Sdw Drawing (For Reference Only)

    Drawing for Conversion Adapter (TGC-100SDW) Figure B-2. TGC-100SDW Drawing (For Reference Only) TGC-100SDW (TQPACK100SD + TQSOCKET100SDW) Package dimension (unit: mm) F E D note: Product by TOKYO ELETECH CORPORATION. APPENDIX B DEVELOPMENT TOOLS I J K ITEM MILLIMETERS INCHES 21.55 0.848 0.5x24=12 0.020x0.945=0.472...

  • Page 611: B-3 Ev-9200Gf-100 Drawing (For Reference Only)

    Socket Drawing and Recommended Footprints (EV-9200GF-100) Figure B-3. EV-9200GF-100 Drawing (For Reference Only) EV-9200GF-100 No.1 pin index APPENDIX B DEVELOPMENT TOOLS ITEM MILLIMETERS 24.6 18.6 4-C 2 12.0 22.6 25.3 16.6 19.3 0.35 EV-9200GF-100-G0 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89...

  • Page 612: B-4 Ev-9200Gf-100 Recommended Footprints (For Reference Only)

    Figure B-4. EV-9200GF-100 Recommended Footprints (For Reference Only) Based on EV-9200GF-100 (2) Pad drawing (in mm) ITEM MILLIMETERS 0.65 0.02 x 29 = 18.85 0.05 0.65 0.02 x 19 = 12.35 0.05 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts.

  • Page 613: Appendix C Embedded Software

    APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the embedded software is available. Real-time OS (1/2) RX78K/0 A real-time OS conforming to ITRON specifications. Real-time OS Added with the tool (configurator) to create the RX78K/0 nucleus and multiple information table. Used in combination with separately available Assembler Package (RA78K/0) and Device File (DF78078).
  • Page 614 APPENDIX C Real-time OS (2/2) MX78K0 A ITRON specification subset OS. Added with MX78K0 nucleus. Performs task management, event management, and time management. In task management, controls the execution order of tasks and performs processing to change the task to the one executed next.

  • Page 615: Appendix D Register Index

    D.1 Register Name Index A/D conversion result register (ADCR) ... 295 A/D converter input select register (ADIS) ... 298 A/D converter mode register (ADM) ... 296 Asynchronous serial interface mode register (ASIM) ... 462 Asynchronous serial interface status register (ASIS) ... 464 Automatic data transmit/receive address pointer (ADTP) ...
  • Page 616 8-bit timer mode control register 1 (TMC1) ... 233 8-bit timer mode control register 5 (TMC5) ... 256 8-bit timer mode control register 6 (TMC6) ... 257 8-bit timer output control register (TOC1) ... 234 8-bit timer register 1 (TM1) ... 230 8-bit timer register 2 (TM2) ...
  • Page 617 Port 0 (P0) ... 136 Port 1 (P1) ... 138 Port 2 (P2) ... 139, 141 Port 3 (P3) ... 143 Port 4 (P4) ... 144 Port 5 (P5) ... 145 Port 6 (P6) ... 146 Port 7 (P7) ... 148 Port 8 (P8) ...
  • Page 618 Sampling clock select register (SCS) ... 197, 510 Serial bus interface control register (SBIC) ... 325, 376 Serial I/O shift register 0 (SIO0) ... 319, 370 Serial I/O shift register 1 (SIO1) ... 417 Serial operating mode register 0 (CSIM0) ... 323, 374 Serial operating mode register 1 (CSIM1) ...

  • Page 619: Register Symbol Index

    D.2 Register Symbol Index ADCR: A/D conversion result register ... 295 ADIS: A/D converter input select register ... 298 ADM: A/D converter mode register ... 296 ADTC: Automatic data transmit/receive control register ... 420 ADTI: Automatic data transmit/receive interval specify register ... 421 ADTP: Automatic data transmit/receive address pointer ...
  • Page 620 IMS: Internal memory size switching register ... 532, 570 INTM0: External interrupt mode register 0 ... 196, 508 INTM1: External interrupt mode register 1 ... 299, 508 IXS: Internal extension RAM size switching register ... 571 KRM: Key return mode register ... 162, 525 MK0H: Interrupt mask flag register 0H ...
  • Page 621 PM10: Port mode register 10 ... 157, 258 PM12: Port mode register 12 ... 157, 497 PM13: Port mode register 13 ... 157 PR0H: Priority specify flag register 0H ... 507 PR0L: Priority specify flag register 0L ... 507 PR1L: Priority specify flag register 1L ... 507 PUOH: Pull-up resistor option register H ...
  • Page 622 TMC6: 8-bit timer mode control register 6 ... 257 TMS: 16-bit timer register ... 230 TOC0: 16-bit timer output control register ... 194 TOC1: 8-bit timer output control register ... 234 TXS: Transmit shift register ... 460 WDTM: Watchdog timer mode register ... 280 APPENDIX D REGISTER INDEX...

  • Page 623: Appendix Erevision History

    The revision history is shown below. The chapters appearing in the chapter column indicate those of the corresponding edition. Version Major revisions from previous version Second PD78076, 78078, 78P078: Under development Developed PD78074, 78075, 78074Y, 78075Y, 78076Y, 78078Y, 78P078Y have been added as new members of this subseries.
  • Page 624 Version Major revisions from previous version Second Table 24-1. HALT Mode Operating Status has been modified. Table 24-3. STOP Mode Operating Status has been modified. CHAPTER 26 ROM CORRECTION has been added. The development statuses for the following products have been changed from “Under Development”...
  • Page 625 Edition Major revisions from previous edition Fourth The following products have been changed from “under development” to “already developed”. PD78078Y Subseries: PD78076Y, 78078Y, 78P078Y The following package has been added to the Subseries. 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) Block diagrams of ports have been changed.
  • Page 626 [MEMO]...
  • Page 627 NEC Electronics Taiwan Ltd. Fax: 02-719-5951 Excellent Good Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.

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