Page 1 User’s Manual µ PD754144, 754244 4-Bit Single-Chip Microcontrollers µ PD754144 µ PD754244 Document No. U10676EJ3V0UM00 (3rd edition) Date Published November 2002 N CP(K) 1997 Printed in Japan...
Page 2 [MEMO] User’s Manual U10676EJ3V0UM...
Page 3 This product cannot be used for an IC card (SMART CARD). EEPROM is a trademark of NEC Electronics Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Correction of instruction code of “BR BCDE” in 11.3 Opcode of Each Instruction p.296 Deletion of flash-related products in configuration diagram in APPENDIX A DEVELOPMENT TOOLS Deletion of APPENDIX A LIST OF FUNCTIONS OF µ PD754144, 754244, AND 75F4264 p.297 in 2nd edition The mark Major Revisions in This Edition Description shows major revised points.
Page 7 It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. • To users who use this manual as a manual for µ PD754144 (RC oscillation, f → Unless otherwise specified, the µ PD754244 (crystal/ceramic oscillation, f •...
Page 8 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to devices µ PD754144, 754244 Data Sheet µ PD754144, 754244 User’s Manual 75XL Series Selection Guide Documents related to development tools (software) (user’s manuals) RA75X Assembler Package Documents related to development tools (hardware) (user’s manuals)
Page 9: Table Of Contents
INT0 ... 2.2.5 KR4 to KR7 ... 2.2.6 KRREN ... 2.2.7 TH00 and TH01 ... 2.2.8 CL1 and CL2 ( µ PD754144 only) ... 2.2.9 X1 and X2 ( µ PD754244 only) ... 2.2.10 2.2.11 RESET ... 2.2.12 IC ...
Page 10 Accumulator ... Stack Pointer (SP) and Stack Bank Select Register (SBS) ... Program Status Word (PSW) ... Bank Select Register (BS) ... CHAPTER 5 EEPROM ... EEPROM Configuration ... EEPROM Features ... EEPROM Write Control Register (EWC) ... Interrupt Related to EEPROM Control ... EEPROM Manipulation Method ...
Page 11 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS ... 186 Configuration of Interrupt Controller ... 186 Types of Interrupt Sources and Vector Table ... 188 Hardware Controlling Interrupt Function ... 190 Interrupt Sequence ... 197 Nesting Control of Interrupts ... 198 Servicing of Interrupts Sharing Vector Address ... 200 Machine Cycles Until Interrupt Servicing ...
Page 12 11.4.10 Branch instructions ... 11.4.11 Subroutine/stack control instructions ... 11.4.12 Interrupt control instructions ... 11.4.13 Input/output instructions ... 11.4.14 CPU control instruction ... 11.4.15 Special instructions ... APPENDIX A DEVELOPMENT TOOLS ... 293 APPENDIX B ORDERING MASK ROM ... 297 APPENDIX C INSTRUCTION INDEX ...
Page 13 Figure No. Selecting MBE = 0 Mode and MBE = 1 Mode ... Data Memory Configuration and Addressing Range for Each Addressing Mode ... Updating Address of Static RAM ... Example of Using Register Banks ... Configuration of General-Purpose Registers (4-Bit Processing) ... Configuration of General-Purpose Registers (8-Bit Processing) ...
Page 14 Figure No. 6-18 Example of Incorrect Resonator Connection ... 6-19 CPU Clock Switching Example ... 6-20 Block Diagram of Basic Interval Timer/Watchdog Timer ... 6-21 Format of Basic Interval Timer Mode Register ... 6-22 Format of Watchdog Timer Enable Flag (WDTM) ... 6-23 Block Diagram of Timer Counter (Channel 0) ...
Page 15 Figure No. Interrupt Nesting by Changing Interrupt Status Flag ... 7-10 Block Diagram of KR4 to KR7 ... 7-11 Format of INT2 Edge Detection Mode Register (IM2) ... Releasing Standby Mode ... Wait Time After Releasing STOP Mode ... STOP Mode Release by Key Return Reset or RESET Input ... Configuration of Reset Circuit ...
Page 16 Table No. Pin Functions of Digital I/O Ports ... Functions of Non-Port Pins ... Recommended Connection of Unused Pins ... Addressing Modes ... Register Bank Selected by RBE and RBS ... Example of Using Different Register Banks for Normal Routine and Interrupt Routine ... Addressing Modes Applicable to Peripheral Hardware Unit Manipulation ...
Page 17: Chapter 1 General
The µ PD754144 and 754244 are 4-bit single-chip microcontrollers in the NEC 75XL Series, the successor to the 75X Series that boasts a wealth of variations. The µ PD754144 and 754244 have extended CPU functions compared to the µ PD75048, a 75X Series product with on-chip EEPROM, enabling high-speed and low voltage (1.8 V) operation.
Page 18: Functional Outline
Package • 20-pin plastic SOP (7.62 mm (300)) • 20-pin plastic SSOP (7.62 mm (300)) CHAPTER 1 GENERAL µ PD754144 = 1.0 MHz) Pull-up resistors can be incorporated by mask option On-chip pull-up resistors can be specified by software 3 channels (can be used as 16-bit timer counter) = –40 to +85°C...
Page 19: Ordering Information
20-pin plastic SOP (7.62 mm (300)) 20-pin plastic SSOP (7.62 mm (300)) 20-pin plastic SOP (7.62 mm (300)) 20-pin plastic SSOP (7.62 mm (300)) µ PD754144 4, 8, 16, 64 µ s (at f = 1.0 MHz) RC oscillator (resistors and capacitors are externally provided) Fixed to 56 µ...
Page 20: Block Diagram
Standby divider generator control CL1 CL2 X1 X2 In the case of In the case of µ µ PD754144 PD754244 User’s Manual U10676EJ3V0UM Port 3 P30 to P33 Port 6 P60 to P63 Port 7 P70 to P73 Port 8 Bit seq.
Page 21: Pin Configuration (Top View)
1.5 Pin Configuration (Top View) • Pin configuration of µ PD754144 • 20-pin plastic SOP (7.62 mm (300)) µ PD754144GS-×××-BA5 • 20-pin plastic SSOP (7.62 mm (300)) µ PD754144GS-×××-GJG RESET P60/AV P61/INT0 P62/PTH00 P63/PTH01 IC: Internally Connected (Directly connect to V CHAPTER 1 GENERAL User’s Manual U10676EJ3V0UM...
Page 22 • Pin configuration of µ PD754244 • 20-pin plastic SOP (7.62 mm (300)) µ PD754244GS-×××-BA5 • 20-pin plastic SSOP (7.62 mm (300)) µ PD754244GS-×××-GJG RESET P60/AV P61/INT0 P62/PTH00 P63/PTH01 IC: Internally Connected (Directly connect to V CHAPTER 1 GENERAL User’s Manual U10676EJ3V0UM KRREN P30/PTO0 P31/PTO1...
Page 23 Pin Name P30 to P33: Port 3 P60 to P63: Port 6 P70 to P73: Port 7 P80: Port 8 KR4 to KR7: Key return 4 to 7 INT0: External vectored interrupt 0 PTH00, PTH01: Programmable threshold port analog input 0, 1 PTO0 to PTO2: Programmable timer output 0 to 2 KRREN: Key return reset enable...
Page 24: Chapter 2 Pin Functions
2.1 Pin Functions of µ PD754244 Table 2-1. Pin Functions of Digital I/O Ports Alternate Pin Name Function PTO0 PTO1 PTO2 – INT0 PTH00 PTH01 Input – Notes 1. Circled characters indicate Schmitt-triggered input. Do not specify connection of an on-chip pull-up resistor when using a programmable threshold port. CHAPTER 2 PIN FUNCTIONS Function Programmable 4-bit I/O port (Port 3).
Page 25: Functions Of Non-Port Pins
Reset signal is generated at falling edge of KRn when KRREN = high in STOP mode. Reference voltage input pin. Provided in µ PD754144 only. These pins connect R and C for system clock oscillation. No external clock can be input to these pins.
Page 26: Description Of Pin Functions
2.2 Description of Pin Functions 2.2.1 P30 to P33 (Port 3) ... I/O pins shared with PTO0 to PTO2 P60 to P63 (Port 6) ... I/O pins shared with AV P80 (Port 8) ... I/O pin These are 4-bit I/O ports with output latches (ports 3 and 6) and a 1-bit I/O port with an output latch (port 8). Ports 3 and 6 also have the following functions, in addition to the I/O port function.
Page 27: Int0
2.2.4 INT0 ... input pin shared with port 6 This pin inputs the vectored interrupt signal detected by the edge. A noise eliminator is selectable for INT0. The edge to be detected can be specified by using the edge detection mode register (IM0). (1) INT0 (bits 0 and 1 of IM0) (a) Active at rising edge (b) Active at falling edge...
Page 28: Ref
This is a reference voltage input pin. An analog reference voltage for the programmable threshold port is input. 2.2.9 CL1 and CL2 ( µ PD754144 only) These pins are used to connect the RC oscillator resistor (R) and capacitor (C) of the system clock oscillator.
Page 29: Vss
2.2.12 IC The IC (Internally Connected) pin sets the test mode in which the µ PD754244 is tested before shipment. Usually, you should directly connect the IC pin to the V If a voltage difference is generated between the IC and V external noise is superimposed on the IC pin, your program may not be correctly executed.
Page 30: Vdd
2.3 Pin I/O Circuits The following diagrams show the I/O circuits of the pins of the µ PD754244. Note that in these diagrams the I/ O circuits have been slightly simplified. Type A P-ch N-ch CMOS specification input buffer. Type B Schmitt-triggered input with hysteresis characteristics.
Page 31: Av Ref
2.4 Processing of Unused Pins Table 2-3. Recommended Connection of Unused Pins P30/PTO0 P31/PTO1 P32/PTO2 P60/AV P61/INT0 P62/PTH00 P63/PTH01 P70/KR4 P71/KR5 P72/KR6 P73/KR7 KRREN CHAPTER 2 PIN FUNCTIONS Recommended Connection Input: Independently connect to V or V Output: Leave open. Connect to V Input: Independently connect to V...
Page 32: Chapter 3 Features Of Architecture And Memory Map
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP The 75XL architecture employed for the µ PD754244 has the following features. • Internal RAM: 4K words × 4 bits MAX. (12-bit address) • Expandability peripheral hardware To realize these superb features, the following techniques have been employed. (1) Bank configuration of data memory (2) Bank configuration of general-purpose registers (3) Memory mapped I/O...
Page 33: Selecting Mbe = 0 Mode And Mbe = 1 Mode
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-1. Selecting MBE = 0 Mode and MBE = 1 Mode SET 1 MBE CLR 1 MBE Internal hardware and static RAM manipulation SET 1 MBE repeated. Remark Solid line: MBE = 1, dotted line: MBE = 0 Because MBE is automatically saved or restored during subroutine processing, it can be changed even while subroutine processing is being executed.
Page 34: Addressing Mode Of Data Memory
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.1.2 Addressing mode of data memory The 75XL architecture employed for the µ PD754244 provides the seven types of addressing modes shown in Table 3-1. This means that the data memory space can be efficiently addressed by the bit length of the data to be processed and that programming can be carried out efficiently.
Page 35: Data Memory Configuration And Addressing Range For Each Addressing Mode
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-2. Data Memory Configuration and Addressing Range for Each Addressing Mode Addressing mode mem. bit Memory bank enable flag MBE = 0 MBE = 1 MBE = 0 MBE = 1 000H General- purpose...
Page 36: Addressing Modes
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Addressing Mode Representation 4-bit direct addressing 8-bit direct addressing 4-bit register indirect addressing @HL+ @HL– 8-bit register indirect addressing Bit manipulation fmem.bit addressing pmem.@L @H+mem.bit Stack addressing — Table 3-1. Addressing Modes Specified Address •...
Page 37 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (2) 4-bit direct addressing (mem) This addressing mode is used to directly address the entire memory space in 4-bit units by using the operand of an instruction. Like the 1-bit direct addressing mode, the area that can be addressed is fixed to the data area of addresses 000H to 07FH and the peripheral hardware area of F80H to FFFH in the mode of MBE = 0.
Page 38 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Examples 1. To compare data 50H to 57H with data 60H to 67H DATA1 EQU DATA2 EQU SET1 D, #DATA1 SHR 4 HL, #DATA2 AND 0FFH LOOP : MOV A, @DL A, @HL DECS L LOOP 2.
Page 39: Updating Address Of Static Ram
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-3. Updating Address of Static RAM DECS D 4-bit DECS L transfer INCS D DECS H Auto @HL 4-bit decrement manipulation DECS L 8-bit DECS HL manipuIation INCS H DECS E INCS L DECS DE Direct addressing...
Page 40 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (5) 8-bit register indirect addressing (@HL) This addressing mode is used to indirectly address the entire data memory space in 8-bit units by using a data pointer (HL register pair). In this addressing mode, data is processed in 8-bit units, that is, the 4-bit data at an address specified by the data pointer with bit 0 (bit 0 of the L register) cleared to 0 and the 4-bit data at the address higher are used in pairs and processed with the data of the 8-bit accumulator (XA register).
Page 41 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (6) Bit manipulation addressing This addressing mode is used to manipulate the entire memory space in bit units (such as Boolean processing and bit transfer). While the 1-bit direct addressing mode can only be used with the instructions that set, reset, or test a bit, this addressing mode can be used in various ways such as Boolean processing by the AND1, OR1, and XOR1 instructions, and test and reset by the SKTCLR instruction.
Page 42 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (b) Specific address bit register indirect addressing (pmem, @L) This addressing mode is to indirectly specify and successively manipulate the bits of the peripheral hardware units such as I/O ports. The data memory addresses to which this addressing mode can be applied are FC0H to FFFH.
Page 43 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (c) Special 1-bit direct addressing (@H+mem.bit) This addressing mode enables bit manipulation in the entire memory space. The higher 4 bits of the data memory address of the memory bank specified by MBE and MBS are indirectly specified by the H register, and the lower 4 bits and the bit address are directly specified by the operand.
Page 44 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (7) Stack addressing This addressing mode is used to save or restore data when interrupt servicing or subroutine processing is executed. The address of data memory bank 0 pointed to by the stack pointer (8 bits) is specified in this addressing mode. In addition to being used during interrupt servicing or subroutine processing, this addressing is also used to save or restore register contents by using the PUSH or POP instruction.
Page 45: Bank Configuration Of General-Purpose Registers
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.2 Bank Configuration of General-Purpose Registers The µ PD754244 is provided with four register banks with each bank consisting of eight general-purpose registers: X, A, B, C, D, E, H, and L. The general-purpose register area consisting of these registers is mapped to the addresses 00H to 1FH of memory bank 0 (refer to Figure 3-5 Configuration of General-Purpose Registers (4-Bit Process- ing)).
Page 46: Example Of Using Register Banks
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-4. Example of Using Register Banks <Main program> SET1 RBE SEL RB2 RB = 2 RB = 0 If RBS is to be changed in the course of subroutine processing or interrupt servicing, it must be saved or restored by using the PUSH or POP instruction.
Page 47 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (1) To use as 4-bit registers When the general-purpose register area is used as a 4-bit register area, a total of eight general-purpose registers, X, A, B, C, D, E, H, and L, specified by RBE and RBS can be used as shown in Figure 3-5. Of these registers, A plays a central role in transferring, operating, and comparing 4-bit data as a 4-bit accumulator.
Page 48: Configuration Of General-Purpose Registers (4-Bit Processing)
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-5. Configuration of General-Purpose Registers (4-Bit Processing) Register bank 0 (RBE RBS = 0) Register bank 1 (RBE RBS = 1) Register bank 2 (RBE RBS = 2) Register bank 3 (RBE RBS = 3) User’s Manual U10676EJ3V0UM...
Page 49: Configuration Of General-Purpose Registers (8-Bit Processing)
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-6. Configuration of General-Purpose Registers (8-Bit Processing) When RBE RBS = 0 When RBE RBS = 2 User’s Manual U10676EJ3V0UM When RBE RBS = 1 When RBE RBS = 3...
Page 50: Memory-Mapped I/O
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.3 Memory-Mapped I/O The µ PD754244 employs memory-mapped I/O that maps peripheral hardware units such as I/O ports and timers to addresses F80H to FFFH on the data memory space, as shown in Figure 3-2. Therefore, no special instructions to control the peripheral hardware units are provided, and all the hardware units are controlled by using memory manipulation instructions.
Page 51 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7 shows the I/O map of the µ PD754244. The meanings of the symbols shown in this figure are as follows. • Symbol ... Name indicating the address of an internal hardware unit Can be written in operands of instructions •...
Page 52: Μ Pd754244 I/O Map
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address F80H Stack pointer (SP) Register bank selection register (RBS) F82H Bank selection register (BS) F83H Memory bank selection register (MBS) F84H Stack bank selection register (SBS) F85H Basic interval timer mode register (BTM) F86H Basic interval timer (BT) F88H...
Page 53 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µ PD754244 I/O Map (2/8) Hardware name (symbol) Address F90H Timer counter 2 mode register (TM2) TOE2 REMC NRZB F92H Timer counter 2 control register (TC2) – – F94H Timer counter 2 count register (T2) F96H Timer counter 2 modulo register (TMOD2) F98H...
Page 54 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address FA0H Timer counter 0 mode register (TM0) Note 1 FA2H TOE0 – – FA3H Unmounted FA4H Timer counter 0 count register (T0) FA6H Timer counter 0 modulo register (TMOD0) FA8H Timer counter 1 mode register (TM1) Note 2...
Page 55 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address IST1 IST0 FB0H Program status word (PSW) Note 1 Note 1 Note 1 FB2H Interrupt priority selection register (IPS) FB3H Processor clock control register (PCC) FB4H INT0 edge detection mode register (IM0) FB5H Unmounted FB6H...
Page 56 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address FC0H Bit sequential buffer 0 (BSB0) FC1H Bit sequential buffer 1 (BSB1) FC2H Bit sequential buffer 2 (BSB2) FC3H Bit sequential buffer 3 (BSB3) FC4H Unmounted FC5H Reset detection flag register (RDF) FC6H –...
Page 57 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address FD0H Unmounted FD3H FD4H Programmable threshold port (PTH0) FD5H Unmounted Note Note Note PTHM3 PTHM2 PTHM1 PTHM0 FD6H Programmable threshold port mode register (PTHM) Note Note PTHM7 PTHM6 –...
Page 58 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address FE0H Unmounted FE7H PM33 PM32 PM31 FE8H Port mode register group A (PMGA) Note Note Note PM63 PM62 PM61 PM60 FEAH Unmounted FEDH – – – FEEH Port mode register group C (PMGC) –...
Page 59 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address FF0H Unmounted FF2H FF3H Port 3 (PORT3) FF4H Unmounted FF5H FF6H Port 6 (PORT6) Port 7 (PORT7) FF7H Note 1 Port 8 (PORT8) FF8H – – – FF9H Unmounted FFFH Notes 1.
Page 60: Chapter 4 Internal Cpu Function
This mode can be used with the CPU in the 75XL Series having a ROM capacity of up to 16 KB. • MkII mode: In this mode, the µ PD754144 is not compatible with the 75X Series. This mode can be used with all the CPUs in the 75XL Series, including the models having a ROM capacity of 16 KB or higher.
Page 61: Setting Stack Bank Select Register (Sbs)
4.1.2 Setting stack bank select register (SBS) The MkI mode or MkII mode is selected by using the stack bank select register (SBS). Figure 4-1 shows the format of this register. The stack bank select register is set by using a 4-bit memory manipulation instruction. To use the MkI mode, be sure to initialize the stack bank select register to 1000B at the beginning of the program.
Page 62: Program Counter (Pc)
4.2 Program Counter (PC) ··· 12 bits This is a binary counter that holds an address of the program memory. Figure 4-2. Configuration of Program Counter PC11 PC10 The value of the program counter (PC) is usually automatically incremented by the number of bytes of an instruction each time that instruction has been executed.
Page 63: Program Memory (Rom)
4.3 Program Memory (ROM) ··· 4096 × 8 bits The program memory stores a program, interrupt vector table, the reference table of the GETI instruction, and table data. The program memory is addressed by the program counter. The table data can be referenced by using a table reference instruction (MOVT).
Page 64: Program Memory Map
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0020H GET instruction reference table 007FH 0080H 07FFH 0800H 0FFFH Note Can be used in the MkII mode only. Remark In addition to the above, a branch can be made to an address with the lower 8-bits only of the PC changed by means of a BR PCDE or BR PCXA instruction.
Page 65: Data Memory (Ram)
4.4 Data Memory (RAM) ... 128 words × 4 bits The data memory consists of data areas and a peripheral hardware area as shown in Figure 4-4. The data memory consists the following banks with each bank made up of 256 words × 4 bits. •...
Page 66: Specifying Bank Of Data Memory
4.4.2 Specifying bank of data memory A memory bank is specified by a 4-bit memory bank select register (MBS) when bank specification is enabled by setting a memory bank enable flag (MBE) to 1 (MBS = 0, 4, or 15). When bank specification is disabled (MBS = 0), bank 0 or 15 is automatically specified depending on the addressing mode selected at that time.
Page 67: Data Memory Map
CHAPTER 4 INTERNAL CPU FUNCTION Figure 4-4. Data Memory Map Data area Stack area static RAM (128 × 4) Data area EEPROM (16 × 8) Peripheral hardware area User’s Manual U10676EJ3V0UM Data memory 000H General-purpose (32 × 4) register area 01FH 020H 128 ×...
Page 68 The contents of the data memory are undefined at reset. Therefore, they must be initialized at the beginning of program execution (RAM clear). Otherwise, unexpected bugs may occur. Example To clear RAM at addresses 000H to 07FH SET1 XA, #00H HL, #04H RAMC0 : @HL, A...
Page 69: General-Purpose Registers
4.5 General-Purpose Registers ... 8 × 4 bits × 4 banks General-purpose registers are mapped to the specific addresses of the data memory. Four banks of registers, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A), are available. The register bank (RB) that becomes valid when an instruction is executed is determined by the following expression.
Page 70: Accumulator
4.6 Accumulator With the µ PD754244, the A register or XA register pair functions as an accumulator. The A register plays a central role in 4-bit data processing, while the XA register pair is used for 8-bit data processing. When a bit manipulation instruction is used, the carry flag (CY) is used as a bit accumulator. 4.7 Stack Pointer (SP) and Stack Bank Select Register (SBS) The µ...
Page 71: Stack Pointer And Stack Bank Selection Register Configuration
When 00H is set to SP as the initial value, memory bank 0 specified by SBS is used as the stack area, starting from the highest address (07FH). The stack area can be used only in memory bank 0. If stack operation is performed from address 000H onwards, the stack pointer will point to unmounted area 0FFH.
Page 72: Data Saved To Stack Memory (Mki Mode)
Figure 4-9. Data Saved to Stack Memory (MkI Mode) PUSH instruction Stack SP – 2 Register pair, low SP – 1 Register pair, high Figure 4-10. Data Restored from Stack Memory (MkI Mode) POP instruction Stack Register pair, low SP + 1 Register pair, high SP + 2 CHAPTER 4 INTERNAL CPU FUNCTION...
Page 73: Data Saved To Stack Memory (Mkii Mode)
CHAPTER 4 INTERNAL CPU FUNCTION Figure 4-11. Data Saved to Stack Memory (MkII Mode) PUSH instruction Stack SP – 2 Register pair, low SP – 1 Register pair, high Figure 4-12. Data Restored from Stack Memory (MkII Mode) POP instruction Stack Register pair, low SP + 1...
Page 74: Program Status Word (Psw)
4.8 Program Status Word (PSW) ... 8 Bits The program status word (PSW) consists of flags closely related to the operations of the processor. PSW is mapped to addresses FB0H and FB1H of the data memory space, and the 4 bits of address FB0H can be manipulated by using a memory manipulation instruction.
Page 75: Carry Flag Manipulation Instruction
CHAPTER 4 INTERNAL CPU FUNCTION Table 4-4. Carry Flag Manipulation Instruction Instruction (Mnemonic) Carry flag manipulation SET1 instruction CLR1 NOT1 Bit transfer instruction MOV1 mem*.bit, CY MOV1 CY, mem*.bit Bit Boolean instruction AND1 CY, mem*.bit CY, mem*.bit XOR1 CY, mem*.bit Interrupt service In interrupt execution - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -...
Page 76: Contents Of Interrupt Status Flags
(3) Interrupt status flags (IST1 and IST0) The interrupt status flags record the status of the processing under execution (for details, refer to Table 7-3 IST, IST0, and Interrupt Servicing). Table 4-5. Contents of Interrupt Status Flags IST1 IST0 Status of Processing Being Executed Status 0 Status 1 Status 2...
Page 77 CHAPTER 4 INTERNAL CPU FUNCTION (5) Register bank enable flag (RBE) This flag specifies whether the register bank of the general-purpose registers is expanded or not. RBE can be set or reset at any time by using a bit manipulation instruction, regardless of the setting of the memory bank.
Page 78: Bank Select Register (Bs)
4.9 Bank Select Register (BS) The bank select register (BS) consists of a register bank select register (RBS) and a memory bank select register (MBS) which specify the register bank and the memory bank to be used, respectively. RBS and MBS are set by the SEL RBn and SEL MBn instructions, respectively. BS can be saved to or restored from the stack area in 8-bit units by the PUSH BS or POP BS instruction.
Page 79: Rbe, Rbs, And Register Bank Selected
CHAPTER 4 INTERNAL CPU FUNCTION (2) Register bank select register (RBS) The register bank select register specifies a register bank to be used as general-purpose registers. It can select bank 0 to 3. RBS is set by the SEL RBn instruction (n = 0-3). When the RESET signal is asserted, RBS is initialized to “0”.
Page 80: Chapter 5 Eeprom
• Write time ··· Set EWTC4 to EWTC6 so that the write time is as follows. With µ PD754144 ··· 18 × 2 With µ PD754244 ··· 4.0 ms MIN., 10.0 ms MAX. Clear the EEPROM write enable/disable control bit (EWE) to 0 after writing.
Page 81: Eeprom Write Control Register (Ewc)
5.3 EEPROM Write Control Register (EWC) The EEPROM write control register (EWC) is an 8-bit register used to control manipulation of EEPROM. Figure 5-1 shows its configuration. Figure 5-1. Format of EEPROM Write Control Register Address FCEH CHAPTER 5 EEPROM EWTC6 EWTC5 EWTC4...
Page 82: Interrupt Related To Eeprom Control
Cautions 1. The write time depends on the system clock oscillation frequency. 2. Set EWTC4-EWTC6 so that the write time is as follows. With µ PD754144 ··· 18 × 2 With µ PD754244 ··· 4.0 ms MIN., 10.0 ms MAX.
Page 83: Eeprom Manipulation Method
5.5 EEPROM Manipulation Method 5.5.1 EEPROM manipulation instructions Instructions that can be used to manipulate the EEPROM are shown below, divided into read instructions and write instructions. (1) Read manipulation instructions Instruction Group Mnemonic Transfer instruction Compare instruction Remark Operation instruction such as ADDS, AND, etc., cannot be used. (2) Write manipulation instructions Instruction Group Mnemonic...
Page 84: Read Manipulation
5.5.2 Read manipulation The following procedure is used to read EEPROM. EWST, ERE and EWE can be set simultaneously by an 8-bit memory manipulation instruction to EWC. <1> Check that the write status flag (EWST) is 0 (write enabled = writing is currently not being performed). <2>...
Page 85: Write Manipulation
5.5.3 Write manipulation Use the following procedure to write to EEPROM. Any instruction other than one related to EEPROM writing can be executed even during an EEPROM write operation. EWST, EWTC and EWE can be set simultaneously by an 8-bit memory manipulation instruction to EWC. <1>...
Page 86 Set EWTC4 to EWTC6 so that data can be written to the EEPROM once within the following time. • With µ PD754144 ... 18 × 2 • With µ PD754244 ... 4.0 ms MIN., 10.0 ms MAX.
Page 87: Cautions On Eeprom Writing
There are restrictions on the write instruction. Refer to 5.5.1 EEPROM manipulation instructions for details. Set EWTC4 to EWTC6 so that the write time is as follows. With µ PD754144 ... 18 × 2 With µ PD754244 ... 4.0 ms MIN., 10.0 ms MAX. Clear EWE to 0 after writing.
Page 88: Chapter 6 Peripheral Hardware Function
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Ports The µ PD754244 uses memory mapped I/O, and all the I/O ports are mapped to the data memory space. Figure 6-1. Data Memory Address of Digital Ports Address Table 6-2 lists the instructions that manipulate the I/O ports. Ports 3 and 6 can be manipulated in 4-I/O and 1-bit units.
Page 89: Types, Features, And Configurations Of Digital I/O Ports
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.1 Types, features, and configurations of digital I/O ports Table 6-1 shows the types of digital I/O ports. Figures 6-2 to 6-9 show the configuration of each port. Table 6-1. Types and Features of Digital Ports Port Function PORT3...
Page 90: P3N Configuration (N = 0 To 2)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-2. P3n Configuration (n = 0 to 2) Input buffer Output latch PM3n PTOn Input buffer Output latch PM33 POGA bit 3 Input buffer Output buffer Figure 6-3. P33 Configuration POGA bit 3 Input buffer Output buffer User’s Manual U10676EJ3V0UM Pull-up resistor...
Page 91: P60 Configuration
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-4. P60 Configuration Input buffer with Input buffer hysteresis characteristics Output buffer Output latch PM60 Figure 6-5. P61 Configuration INT0 Input buffer with Internal bus hysteresis characteristics Output buffer Output latch PM61 User’s Manual U10676EJ3V0UM POGA bit 6 Pull-up resistor P-ch...
Page 92: P62 Configuration
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Input buffer Output latch PM62 Input buffer Output latch PM63 Figure 6-6. P62 Configuration POGA bit 6 Input buffer with hysteresis characteristics Output buffer PTH00 Figure 6-7. P63 Configuration POGA bit 6 Input buffer with hysteresis characteristics Output buffer PTH01...
Page 93: P7N Configuration (N = 0 To 3)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-8. P7n Configuration (n = 0 to 3) Key return reset One-shot pulse generator Interrupt control Falling edge detector Input buffer with hysteresis characteristics Input buffer Figure 6-9. P80 Configuration Input buffer Output buffer Output latch Port mode register group C bit 0 User’s Manual U10676EJ3V0UM...
Page 94: Setting I/O Mode
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.2 Setting I/O mode The input or output mode of each I/O port is set by the corresponding port mode register as shown in Figure 6- 10. Ports 3 and 6 can be set to the input or output mode in 1-bit units by using port mode register group A (PMGA). Port 8 is set to the input or output mode by using port mode register group C (PMGC).
Page 95: Format Of Each Port Mode Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-10. Format of Each Port Mode Register Port mode register group A Address FE8H PM63 PM62 PM61 Port mode register group C Address FEEH – – – Specification Input mode (output buffer off) Output mode (output buffer on) Symbol PM60 PM33 PM32...
Page 96: Digital I/O Port Manipulation Instruction
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.3 Digital I/O port manipulation instruction Because all the I/O ports of the µ PD754244 are mapped to the data memory space, they can be manipulated by using data memory manipulation instructions. Table 6-2 shows these data memory manipulation instructions, which are considered to be especially useful for manipulating the I/O pins and their range of applications.
Page 97: I/O Pin Manipulation Instructions
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-2. I/O Pin Manipulation Instructions PORT Instruction Note 1 A, PORTn Note 1 XA, PORTn Note 1 PORTn, A Note 1 PORTn, XA Note 1 A, PORTn Note 1 XA, PORTn Note 1 PORTn, A Note 1 PORTn, XA Note 1...
Page 98: Operation Of Digital I/O Port
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.4 Operation of digital I/O port The operations of each port and port pin when a data memory manipulation instruction is executed to manipulate a digital I/O port differ depending on whether the port is set to the input or output mode (refer to Table 6-3). This is because, as can be seen from the configuration of the I/O port, the data of each pin is loaded to the internal bus in the input mode, and the data of the output latch is loaded to the internal bus in the output mode.
Page 99: Operation When I/O Port Is Manipulated
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-3. Operation When I/O Port Is Manipulated Instruction Executed <1> Tests pin data <1> MOV1 CY, <1> Transfers pin data to CY AND1 CY, <1> Performs operation between pin data and CY CY, <1> XOR1 CY, <1>...
Page 100: Connecting Pull-Up Resistor
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.5 Connecting pull-up resistor Each port pin of the µ PD754244 can be connected to a pull-up resistor. Some pins can be connected to a pull- up resistor via software and others can be connected by a mask option. Table 6-4 shows how to specify the connection of the pull-up resistor to each port pin.
Page 101: I/O Timing Of Digital I/O Port
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.6 I/O timing of digital I/O port Figure 6-12 shows the timing at which data is output to the output latch and the timing at which the pin data or the data of the output latch is loaded to the internal bus. Figure 6-13 shows the ON timing when an on-chip pull-up resistor connection is specified via software.
Page 102: On Timing Of Internal Pull-Up Resistor Connected Via Software
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-13. ON Timing of Internal Pull-up Resistor Connected via Software Instruction execution Pull-up resistor specification register 2 machine cycles Internal pull-up resistor setting instruction User’s Manual U10676EJ3V0UM Φ Φ...
Page 103: Clock Generator
Φ = CPU clock PCC: Processor Clock Control Register One clock cycle (t ) of the CPU clock is equal to one machine cycle of the instruction. (a) µ PD754144 (RC oscillation) 1/1 to 1/4096 Divider 1/2 1/4 1/16 HALT F/F User’s Manual U10676EJ3V0UM...
Page 104 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-14. Block Diagram of Clock Generator (2/2) (b) µ PD754244 Crystal/Ceramic Oscillation System clock oscillator Oscillation stops PCC0 PCC1 PCC2 HALT Note PCC3 STOP Note PCC2, STOP F/F PCC3 clear Note Instruction execution Remarks 1. : System clock frequency Φ...
Page 105: Function And Operation Of Clock Generator
Notes 1. µ PD754144: 64 µ s at f µ PD754244: 15.3 µ s at f 2. µ PD754144: 4, 8, 16, 64 µ s at f µ PD754244: 0.95, 1.91, 3.81, 15.3 µ s at f 0.67, 1.33, 6.67, 10.7 µ s at f Note 2 by PCC.
Page 106 3. To set STOP mode (be sure to write a NOP instruction after STOP and HALT instructions) STOP PCC is cleared to “0” when the RESET signal is asserted. Notes 1. µ PD754144: 4 µ s (f µ PD754244: 0.67 µ s (f 2. µ PD754144: 8 µ s (f µ...
Page 107: Format Of Processor Clock Control Register
CPU operating mode control bits PCC3 PCC2 Normal operating mode HALT mode STOP mode Setting prohibited CPU clock selection bits ( µ PD754144: When f PCC1 PCC0 CPU clock frequency Φ = f Φ = f Φ = f Φ = f ( µ...
Page 108: Rc Oscillation External Circuit
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) System clock oscillator (a) µ PD754144 (RC oscillation) The system clock oscillator oscillates by means of a resistor (R) and capacitor (C) connected to the CL1 and CL2 pins. An external clock cannot be input for RC oscillation.
Page 109: Example Of Incorrect Resonator Connection
Figure 6-18 shows incorrect examples of connecting the resonator. Figure 6-18. Example of Incorrect Resonator Connection (1/3) (a) Wiring length too long µ • PD754144 µ PD754144 User’s Manual U10676EJ3V0UM by a resistor of 50 kΩ (typ.) µ • PD754244...
Page 110 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-18. Example of Incorrect Resonator Connection (2/3) (b) Crossed signal line µ • PD754144 µ PD754144 (c) High alternating current close to signal line µ • PD754144 µ PD754144 High current PORTn (n = 3, 6-8)
Page 111 PORTn (n = 3, 6-8) (e) Signal fetched µ • PD754144 µ PD754144 (3) Divider circuit The divider circuit divides the output of the system clock oscillator to create various clock signals. µ PD754144 High current User’s Manual U10676EJ3V0UM µ...
Page 112: Setting Cpu Clock
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.2.3 Setting CPU clock (1) Time required to switch CPU clock The CPU clock can be switched by using the lower 2 bits of PCC. The processor does not operate with the selected clock, however, immediately after data has been written to the registers; it operates with the pre- change clock for the duration of a certain number of machine cycles.
Page 113: Cpu Clock Switching Example
µ PD754244: The wait time can be selected by a mask option. Can be selected from 2 and from 2 2. µ PD754144: 64 µ s at f µ PD754244: 15.3 µ s at 4.19 MHz and 10.7 µ s at 6.0 MHz 3. µ PD754144: 2 µ...
Page 114: Basic Interval Timer/Watchdog Timer
Note 2 SET1 1. In the case of the µ PD754144 (RC oscillation), it is not possible to select the wait time after the release Notes of standby mode or after a reset. The µ PD754144 has almost no oscillation stabilization wait time and returns to normal operating mode after counting 2 In the case of µ...
Page 115: Basic Interval Timer Mode Register (Btm)
Note It is 1.95 ms when the µ PD754244 is operating at f In the case of µ PD754144, it is fixed to 2 When bit 3 of this register is set to “1”, the contents of BT are cleared, and at the same time, the basic interval timer/watchdog timer interrupt request flag (IRQBT) is cleared (the basic interval timer/watchdog timer is started).
Page 116: Format Of Basic Interval Timer Mode Register
Other Basic interval timer/watchdog timer start control bit Note In the µ PD754244 only, wait time is selectable when standby mode is released. In the µ PD754144, wait time is always fixed to 2 = 1.0 MHz Specifies input clock (244 Hz) (1.95 kHz)
Page 117: Watchdog Timer Enable Flag (Wdtm)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3.3 Watchdog timer enable flag (WDTM) WDTM is a flag that enables assertion of the reset signal when an overflow occurs. This flag is set by a bit manipulation instruction. Once this flag has been set, it cannot be cleared by an instruction. Example To set watchdog timer function MB15 ;...
Page 118: Operation As Basic Interval Timer
BTM, A IEBT Note It is 1.95 ms when the µ PD754244 is operating at f In the case of the µ PD754144, it is 8.19 ms at f ; Sets time and starts ; Enables interrupt ; Enables BT interrupt = 4.19 MHz.
Page 119: Operation As Watchdog Timer
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3.5 Operation as watchdog timer The basic interval timer/watchdog timer operates as a watchdog timer that asserts the internal reset signal when an overflow occurs in the basic interval timer (BT), if WDTM is set to “1”. However, if the overflow occurs during the oscillation wait time that elapses after the STOP instruction has been released, the reset signal is not asserted.
Page 120 SET1 MB15 SET1 BTM.3 Note It is 7.81 ms when the µ PD754244 is operating at f In the case of the µ PD754144, it is 32.8 ms at f SET1 MB15 A, #1101B BTM, A ; Sets time and starts SET1 .
Page 121: Other Functions
MB15 A, #1101B BTM, A STOP 1. The µ PD754244 only. In the µ PD754144, the wait time is fixed to 2 Notes 2. It is 7.81 ms when the µ PD754244 is operating at f (2) Reading count value The count value of the basic interval timer (BT) can be read by using an 8-bit manipulation instruction.
Page 122: Timer Counter
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4 Timer Counter The µ PD754244 incorporates a three-channel timer counter. The timer counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register.
Page 123 Note SET1 – TM06 TM05 TM04 TM03 TM02 From clock generator Timer operation starts Internal bus TMOD0 Modulo register (8) inci- dence TOUT Comparator (8) Reset Count register (8) Clear TOE0 PORT3.0 Bit 0 of PMGA T0 enable Port 3 flag output latch I/O mode...
Page 124 Note SET1 – TM16 TM15 TM14 TM13 TM12 TM11 TM10 Timer counter (channel 2) output From clock generator 16-bit timer counter mode Internal bus TMOD1 Modulo register (8) Decoder inci- dence Comparator (8) Count register (8) Clear Timer operation starts Selector Timer counter (channel 2) match signal (in 16-bit timer counter mode)
Page 125 Note SET1 High-level period setting – TM26 TM25 TM24 TM23 TM22 TM21 TM20 Decoder From clock generator 16-bit timer counter mode Timer operation starts Internal bus TMOD2H TMOD2 – – – Modulo register (8) TOE2 modulo register (8) MPX (8) Match TOUT Comparator (8)
Page 126 SET1 TMn.3 Note CP = 4.10 kHz when the µ PD754244 is operating at fx = 4.19 MHz. CP = 977 kHz when the µ PD754144 is operating at f Remark n = 0 to 2 ; or CLR1 MBE ;...
Page 127: Format Of Timer Counter Mode Register (Channel 0)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-26. Format of Timer Counter Mode Register (Channel 0) Address FA0H – TM06 TM05 Count pulse (CP) select bit µ PD754144: f TM06 TM05 Other µ PD754244: f TM06 TM05 Other µ PD754244: f...
Page 128: Format Of Timer Counter Mode Register (Channel 1)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (1/2) Address FA8H – TM16 TM15 Count pulse (CP) select bit µ PD754144: f TM16 TM15 Other µ PD754244: f TM16 TM15 Other µ PD754244: f...
Page 129 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (2/2) Timer start command bit Clears counter and IRQT1 flag when "1" is written. Starts count operation TM13 if bit 2 is set to "1". Operation mode TM12 Stops (count value retained)
Page 130: Format Of Timer Counter Mode Register (Channel 2)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (1/2) Address F90H – TM26 TM25 Count pulse (CP) select bit µ PD754144: f TM26 TM25 Other µ PD754244: f TM26 TM25 Other µ PD754244: f...
Page 131 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (2/2) Timer start command bit Clears counter and IRQT2 flag when "1" is written. Starts count operation TM23 if bit 2 is set to "1". Operation mode TM22 Stops (count value retained)
Page 132: Format Of Timer Counter Output Enable Flag
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) Timer counter output enable flags (TOE0, TOE1) Timer counter output enable flags TOE0 and TOE1 enable or disable output to the PTO0 and PTO1 pins in the timer out F/F (TOUT F/F) status. The timer out F/F is inverted by a match signal from the comparator. When bit 3 (timer start command bit) of timer counter mode register TM0 or TM1 is set to “1”, the timer out F/F is cleared to “0”.
Page 133: Format Of Timer Counter Control Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Timer counter control register (TC2) The timer counter control register (TC2) is an 8-bit register that controls the timer counter (channel 2). Figure 6-30 shows the format of this register. This register controls timer output enable carrier generator mode used in combination with the timer counter (channel 1).
Page 134: Operation In 8-Bit Timer Counter Mode
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.2 Operation in 8-bit timer counter mode In this mode, the timer counter is used as an 8-bit timer counter. In this case, the timer counter operates as an 8-bit programmable interval timer or counter. (1) Register setting In the 8-bit timer counter mode, the following four registers are used: •...
Page 135: Setting Of Timer Counter Mode Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-31. Setting of Timer Counter Mode Register (1/3) (a) Timer counter (channel 0) Address FA0H – TM06 TM05 TM04 Count pulse (CP) select bit TM06 TM05 TM04 Other Timer start command bit Clears counter and IRQT0 flag when "1" is written. Starts count operation TM03 if bit 2 is set to "1".
Page 136 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-31. Setting of Timer Counter Mode Register (2/3) Address FA8H – TM16 TM15 Count pulse (CP) select bit TM16 TM15 Other Timer start command bit Clears counter and IRQT1 flag when "1" is written. Starts count operation TM13 if bit 2 is set to "1".
Page 137 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-31. Setting of Timer Counter Mode Register (3/3) (c) Timer counter (channel 2) Address F90H – TM26 TM25 TM24 Count pulse (CP) select bit TM26 TM25 TM24 Other Timer start command bit Clears counter and IRQT2 flag when "1" is written. Starts count operation TM23 if bit 2 is set to "1".
Page 138: Setting Of Timer Counter Control Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the 8-bit timer counter mode, set TC2 as shown in Figure 6-32 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TC2 is manipulated by an 8- or 4-bit, or bit manipulation instruction. The value of TC2 is cleared to 00H when the internal reset signal is asserted.
Page 139: Resolution And Longest Set Time (8-Bit Timer Counter Mode)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION [Timer set time] (cycle) is calculated by dividing [contents of modulo register + 1] by [count pulse (CP) frequency] selected by the mode register. T (sec) = = (n+1) (resolution) n +1 where, T (sec): Timer set time (seconds) (Hz): CP frequency (Hz) Contents of modulo register (n ≠...
Page 140 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-7. Resolution and Longest Set Time (8-Bit Timer Counter Mode) (2/3) (TM10 = 0, TM11 = 0, TM20 = 0, TM21 = 0) 8-bit timer counter (channel 2) Mode Register TM26 TM25 (b) µ PD754244: at 4.19 MHz 8-bit timer counter (channel 0) Mode Register TM06...
Page 141 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-7. Resolution and Longest Set Time (8-Bit Timer Counter Mode) (3/3) (TM10 = 0, TM11 = 0, TM20 = 0, TM21 = 0) (c) µ PD754144: at 1.0 MHz 8-bit timer counter (channel 0) Mode Register...
Page 142 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Timer counter operation (8-bit) The timer counter operates as follows. Figure 6-34 shows the configuration when the timer counter operates. <1> The count pulse (CP) is selected by the timer counter mode register (TMn) and is input to the timer counter count register (Tn).
Page 143: Configuration When Timer Counter Operates
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-34. Configuration When Timer Counter Operates Timer counter modulo register (TMODn) Timer counter count register (Tn) Count pulse (CP) Timer counter modulo register (TMODn) Timer counter count register (Tn) Reset TOUT F/F Timer start command Remark m: Set value of timer counter modulo register n : 0 to 2 INTTn...
Page 144 Note This example applies to the operation of the µ PD754244 at f of the µ PD754244 and f = 1.0 MHz operation of the µ PD754144, the longest set time and the interval time are different even if the settings are the same.
Page 145: Operation In Pwm Pulse Generator Mode (Pwm Mode)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.3 Operation in PWM pulse generator mode (PWM mode) In this mode, the timer counter (channel 2) is used as a PWM pulse generator. The timer counter operates as an 8-bit PWM pulse generator. When the timer counter (channel 2) is used as a PWM pulse generator, the timer counters (channel 0 and 1) can be used as 8-bit timer counter.
Page 146: Setting Of Timer Counter Mode Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-36. Setting of Timer Counter Mode Register Address F90H – TM26 TM25 Count pulse (CP) select bit TM26 TM25 Other Timer start command bit Clears counter and IRQT2 flag when "1" is written. Starts count operation TM23 if bit 2 is set to "1".
Page 147: Setting Of Timer Counter Control Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the PWM mode, set TC2 as shown in Figure 6-37 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TC2 is manipulated by an 8-, 4-, or bit manipulation instruction. TC2 is cleared to 00H when the internal reset signal is asserted.
Page 148 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) PWM pulse generator operation The timer counter (channel 2) in PWM pulse generator mode has two registers, a high-level period setting timer counter modulo register (TMOD2H) and a low-level period setting timer counter modulo register (TMOD2).
Page 149: Pwm Pulse Generator Operating Configuration
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-38. PWM Pulse Generator Operating Configuration Timer counter (channel 2) High level period setting timer counter modulo register (TMOD2H) Internal Timer counter count clock register (T2) Note This is the IRQT2 set signal. It is only set when TMOD2 matches T2. Figure 6-39.
Page 150 Note This example applies to the operation of the µ PD754244 at f of the µ PD754244 and f = 1.0 MHz operation of the µ PD754144, the cycles are different even if the settings are the same. 36 = 24H 73 = 49H ;...
Page 151: Operation In 16-Bit Timer Counter Mode
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.4 Operation in 16-bit timer counter mode In this mode, two timer counter channels, 1 and 2, are used in combination to implement 16-bit programmable interval timer or event timer operation. (1) Register setting In the 16-bit timer counter mode, the following seven registers are used. •...
Page 152: Setting Of Timer Counter Mode Registers
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-40. Setting of Timer Counter Mode Registers Address FA8H – TM16 TM15 F90H – TM26 TM25 Count pulse (CP) select bit TMn6 TMn5 Other Timer start command bit Clears counter and IRQTn flag when "1" is written. Starts count operation TM23 if bit 2 is set to "1".
Page 153: Setting Of Timer Counter Control Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the 16-bit timer counter mode, set TC2 as shown in Figure 6-41 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TC2 is manipulated by an 8-, 4-, or bit manipulation instruction. TC2 is cleared to 00H when the internal reset signal is asserted.
Page 154: Resolution And Longest Set Time (16-Bit Timer Counter Mode)
Table 6-8. Resolution and Longest Set Time (16-Bit Timer Counter Mode) (1/2) (TM10 = 0, TM11 = 1, TM20 = 0, TM21 = 1) Mode Register TM26 Mode Register TM26 (a) µ PD754144: at 1.0 MHz 16-Bit Timer Counter TM25 TM24 Resolution 2 µ s 1 µ...
Page 155 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-8. Resolution and Longest Set Time (16-Bit Timer Counter Mode) (2/2) (TM10 = 0, TM11 = 1, TM20 = 0, TM21 = 1) (c) µ PD754244: at 4.19 MHz Mode Register TM26 TM25 TM24 User’s Manual U10676EJ3V0UM 16-Bit Timer Counter Resolution...
Page 156 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Timer counter operation (at 16-bit) The timer counter operates as follows. Figure 6-42 shows the configuration when the timer counter operates. <1> The count pulse (CP) is selected by timer counter mode registers TM1 and TM2 and is input to timer counter count register T2.
Page 157: Configuration When Timer Counter Operates
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-42. Configuration When Timer Counter Operates Other internal clock is ignored T2 overflow Internal clock Timer counter modulo register (TMOD1) Match Comparator Clear Timer counter count register (T1) Timer counter modulo register (TMOD2) Match Comparator Timer counter count register (T2)
Page 158: Timing Of Count Operation
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-43. Timing of Count Operation Count pulse (CP) Timer counter modulo register (TMOD2) Timer counter count register (T2) Timer counter modulo register (TMOD1) Timer counter count register (T1) TOUT F/F Timer start command Remark m: Set value of timer counter module register (TMOD1) n: Set value of timer counter modulo register (TMOD2) m–1 User’s Manual U10676EJ3V0UM...
Page 159 Sets mode and starts timer Disables timer (channel 1) interrupt Enables interrupts Enables timer (channel 2) interrupt = 1.0 MHz operation of the µ PD754144, the longest set time User’s Manual U10676EJ3V0UM Note = 4.19 MHz. With f = 6.0 MHz...
Page 160: Operation In Carrier Generator Mode (Cg Mode)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.5 Operation in carrier generator mode (CG mode) In the PWM mode, timer counter channels 1 and 2 operate in combination to implement an 8-bit carrier generator operation. When using CG mode, use it in combination with channel 1 and channel 2 of the timer counter. Timer counter channel 1 generates a remote controller signal.
Page 161: Setting Of Timer Counter Mode Register (N = 1, 2)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-44. Setting of Timer Counter Mode Register (n = 1, 2) Address FA8H – TM16 TM15 TM14 F90H – TM26 TM25 TM24 Count pulse (CP) select bit TMn6 TMn5 TMn4 Other Timer start command bit Clears counter and IRQTn flag when "1"...
Page 162: Setting Of Timer Counter Output Enable Flag
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the CG mode, set the timer counter output enable flag (TOE1) and TC2 as shown in Figure 6-45 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TOE1 is manipulated by a bit manipulation instruction.
Page 163 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) Carrier generator operation The carrier generator operation is performed as follows. Figure 6-47 shows the configuration of the timer counter in the carrier generator mode. (a) Timer counter (channel 1) operation The timer counter (channel 1) in carrier generator mode determines the time required to output the carrier clock generated by the timer counter (channel 2) to the PTO2 pin, and the time to stop the output.
Page 164 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION <4> The operations <2> and <3> are repeated. <5> The no return zero data is reloaded from NRZB to NRZ when timer counter channel 1 generates an interrupt. <6> A carrier clock or high level is output when NRZ is set to 1 by the remote controller output flag (REMC).
Page 165: Configuration In Carrier Generator Mode
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-47. Configuration in Carrier Generator Mode Timer counter modulo register (TMOD1) Other internal clock is ignored Carrier clock High-level period setting timer counter modulo register (TMOD2H) Internal clock INTT1 (IRQT1 set signal) Match Comparator Timer counter Clear count register (T1)
Page 166: Carrier Generator Operation Timing
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-48. Carrier Generator Operation Timing <1> Timer (channel 2) operation and carrier clock (Modulo register H (TMOD2H) = i, Modulo register (TMOD2) = k) Count pulse (CP) Timer counter count register (T2) Carrier clock <2>...
Page 167 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Remark If a timer (channel 1) interrupt is generated when the PTO2 pin is low and the carrier clock is high (NRZ = 0, carrier clock = high level), the carrier is output to the PTO2 pin from the pulse after the carrier clock.
Page 168 TMOD2H, XA XA, #49H TMOD2, XA XA, #00111111B TM2, XA = 1.0 MHz operation of the µ PD754144, the cycles and signal output 36 = 24H 73 = 49H or CLR1 MBE Sets modulo (high-level period) Sets modulo (low-level period) Sets mode and starts timer User’s Manual U10676EJ3V0UM...
Page 169 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION <2> To output a leader code with a 9 ms period to output a carrier clock and a 4.5 ms period to output a low level (Refer to the figure below.) • Set the higher 4 bits of the timer counter mode register (TM1) to 0110B and select 15.6 ms as the longest set time.
Page 170 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION <3> To output a custom code with a 0.56 ms period to output a carrier clock when data is “1”, a 1.69 ms to output a low level, a 0.56 ms to output a carrier clock when data is “0”, and a 0.56 ms period to output a low level (refer to the figure below).
Page 171 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION <Program example> In the following example, it is assumed that the output latch of the PTO2 pin is cleared to “0” and that the output mode has been set. It is also assumed that the carrier clock is generated with the status of the program in the preceding example (2).
Page 172 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION SEND_1_F CALL !SEND_D_1 SEND_1_F SEND_END : ; <subroutine> GET_DATA: BSB0.@L A, #0 A, #1 H, A SEND_D_0 : LOOP_1ST : SKTCLR IRQT1 LOOP_1ST SEND_D_1 : CLR1 NRZB LOOP_2ND : SKTCLR IRQT1 CLR1 LOOP_3RD : SKTCLR IRQT1 ;...
Page 173: Notes On Using Timer Counter
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.6 Notes on using timer counter (1) Error when timer starts After the timer has been started (bit 3 of TMn has been set to “1”), the time required for generation of the match signal, which is calculated by the expression (contents of modulo register + 1) × resolution, deviates by up to one clock of the count pulse (CP).
Page 174 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) Note on starting timer Usually, count register Tn and interrupt request flag IRQTn are cleared when the timer is started (bit 3 of TMn is set to “1”). However, if the timer is in an operation mode, and if IRQTn is set as soon as the timer is started, IRQTn may not be cleared.
Page 175 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Notes on changing count pulse When it is specified to change the count pulse (CP) by rewriting the contents of the timer counter mode register (TMn), the specification becomes valid immediately after execution of the instruction that commands the specification.
Page 176 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (4) Operation after changing modulo register The contents of the timer counter modulo register (TMODn) and high-level period setting timer counter modulo register (TMOD2H) are changed as soon as an 8-bit data memory manipulation instruction has been executed. Count pulse (CP) Timer counter modulo register...
Page 177 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (5) Note on application of carrier generator (on starting) When the carrier clock is generated, after the timer has been started (by setting bit 3 of TM2 to “1”), the high- level period of the initial carrier clock may deviate by up to one clock of the count pulse (CP) (up to two clocks of CP if the frequency of CP is higher than one machine cycle) from the value calculated by the expression (contents of modulo register + 1) ×...
Page 178 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (6) Notes on application of carrier generator (reload) To output a carrier to the PTO2 pin, the time required for the initial carrier to be generated deviates by up to one carrier clock after reloading (the contents of the no return zero buffer flag (NRZB) are transferred to the no return zero flag (NRZ) by occurrence of the interrupt of timer counter channel 1, and the contents of NRZ are updated to “1”).
Page 179 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (7) Notes on application of carrier generator (restarting) If forced reloading is performed by directly rewriting the contents of the no return zero flag (NRZ) and then the timer is restarted (by setting bit 3 of TM2 to “1”) when the carrier clock is high (TOUT F/F holds “1”), the carrier may not be output to the PTO2 pin as shown below.
Page 180: Programmable Threshold Port (Analog Input Port)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.5 Programmable Threshold Port (Analog Input Port) The µ PD754244 provides analog input pins (PTH00, PTH01) whose threshold voltage (reference voltage) is selectable within sixteen steps. The following operations can be performed with these analog input pins. (1) Comparator operation (2) 4-bit resolution A/D converter operation (controlled by software) Caution When using a programmable threshold port, do not specify connection of an internal pull-up...
Page 181: Block Diagram Of Programmable Threshold Port
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-49. Block Diagram of Programmable Threshold Port PTH00 PTH01 PTH0 – Programmable threshold port input latch (2) – Operate/stop Standby mode signal PTHM7 PTHM6 PTHM5 PTHM4 PTHM3 PTHM2 PTHM1 PTHM0 PTHM User’s Manual U10676EJ3V0UM Input buffer Input buffer...
Page 182: Programmable Threshold Port Mode (Pthm) Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.5.2 Programmable threshold port mode (PTHM) register PTHM is an 8-bit register that controls the programmable threshold port operation, and it is set by an 8-bit memory manipulation instruction. The threshold voltage can be selected by specifying the lower four bits of PTHM within 16 steps as follows. 15.5 ×...
Page 183: Programmable Threshold Port Application
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.5.3 Programmable threshold port application (1) An analog input voltage input to the PTH00 pin is A/D converted with 4-bit resolution. Figure 6-51. Application Example of Programmable Threshold Port PTH00 input voltage Reference voltage (V Conversion start Comparison result...
Page 184: Bit Sequential Buffer
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.6 Bit Sequential Buffer ... 16 Bits The bit sequential buffer (BSB) is a special data memory used for bit manipulation. It can manipulate bits by sequentially changing the address and bit specification. Therefore, this buffer is useful for processing data with a long bit length in bit units.
Page 185 CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Example For serial output of the 16-bit data of BUFF1, 2 from bit 0 of port 3 CLR1 XA, BUFF1 BSB0, XA XA, BUFF2 BSB2, XA L, #0 LOOP0: BSB0, @L LOOP1 SET1 PORT3.0 LOOP2 LOOP1: CLR1 PORT3.0...
Page 186: Chapter 7 Interrupt And Test Functions
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS The µ PD754244 has six vectored interrupt sources and one test input that can be used for various applications. The interrupt controller of the µ PD754244 has unique features and can service interrupts at extremely high speed. (1) Interrupt function (a) Hardware-controlled vectored interrupt functions that can control acknowledgment of an interrupt by using an interrupt enable flag (IE×××) and interrupt master enable flag (IME)
Page 187 INTBT IRQBT Edge IRQ0 INT0/P61 Note1 detector INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 INTEE IRQEE KR4/P70 Falling edge IRQ2 Note2 detector KR7/P73 Key return reset circuit Internal bus Interrupt enable flag (IE×××) IST1 IST0 Decoder VRQn Vector table address Priority controller generator Standby release signal...
Page 188: Types Of Interrupt Sources And Vector Table
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.2 Types of Interrupt Sources and Vector Table The µ PD754244 has the following six interrupt sources and nesting of interrupts can be controlled by software. Table 7-1. Types of Interrupt Sources Interrupt Source INBT (reference time interval signal from ba- sic interval timer/watchdog timer)
Page 189: Interrupt Vector Table
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Address 0002H 0004H 0006H 0008H 000AH 000CH 000EH The priority column in Table 7-1 indicates the priority according to which interrupts are executed if two or more interrupts occur at the same time, or if two or more interrupt requests are held pending. Write the start address of interrupt servicing to the vector table , and the set values of MBE and RBE during interrupt servicing.
Page 190: Hardware Controlling Interrupt Function
(refer to 7.6 Servicing of Interrupts Sharing Vector Address). The µ PD754144 also has six interrupt enable flags (IE×××) corresponding to the respective interrupt request flags. INT0 interrupt enable flag (IE0)
Page 191: Signals Setting Interrupt Request Flags
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Table 7-2. Signals Setting Interrupt Request Flags Interrupt Request Flag IRQBT Set by reference time interval signal from basic interval timer watchdog timer IRQ0 Set by detection of edge of INT0/P61 pin input signal. Edge to be detected is selected by INT0 edge detection mode register (IM0) IRQT0 Set by match signal from timer counter 0...
Page 192: Interrupt Priority Select Register
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-3. Interrupt Priority Select Register Address FB2H IPS3 IPS2 IPS1 Note If this value is set in the IPS register then the state is the same as if it had been set to IPS = X000B (Does not give high priority to any interrupt.) Symbol IPS0...
Page 193 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (3) Hardware of INT0 (a) Figure 7-4 shows the configuration of INT0, which is an external interrupt input that can be detected at the rising or falling edge depending on the specification. INT0 also has a noise elimination function which uses a sampling clock (refer to Figure 7-5 I/O Timing of Noise Eliminator).
Page 194: Configuration Of Int0
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Noise eliminator INT0/P61 Selector Φ Note Even if f /64 is selected, the HALT mode cannot be released by INT0. Figure 7-5. I/O Timing of Noise Eliminator <1> Narrow than sampling cycle INT0 Shaped output <2>...
Page 195: Format Of Int0 Edge Detection Mode Register (Im0)
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-6. Format of INT0 Edge Detection Mode Register (IM0) Address FB4H IM03 IM02 IM01 IM00 Note This value differs depending on the system clock frequency (f Caution When the contents of the edge detection mode register are changed, the interrupt request flag may be set.
Page 196: Ist1 And Ist0 And Interrupt Servicing Status
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (4) Interrupt status flag The interrupt status flags (IST0 and IST1) indicate the status of the processing currently being executed by the CPU and are included in PSW. The interrupt priority controller controls nesting of interrupts according to the contents of these flags as shown in Table 7-3.
Page 197: Interrupt Sequence
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.4 Interrupt Sequence When an interrupt occurs, it is processed according to the procedure illustrated below. Figure 7-7. Interrupt Servicing Sequence Interrupt (INT×××) occurs Sets IRQ××× IE××× set? Corresponding VRQn occurs IME=1 VRQn interrupt with high priority? Note 1 IST1, 0 = 00 or...
Page 198: Nesting Control Of Interrupts
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.5 Nesting Control of Interrupts The µ PD754244 can nest interrupts by the following two methods. (1) Nesting with interrupt having high priority specified This method is the standard nesting method of the µ PD754244. One interrupt source is selected and nested. An interrupt with a higher priority specified by the interrupt priority select register (IPS) can occur when the status of the processing under execution is 0 or 1, and the other interrupts (interrupts with a lower priority) can occur when the status is 0 (refer to Figure 7-8 and Table 7-3).
Page 199: Interrupt Nesting By Changing Interrupt Status Flag
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (2) Nesting by changing interrupt status flags Nesting can be implemented if the interrupt status flags are changed by program. In other words, nesting is enabled when IST1 and IST0 are cleared to “0, 0” by an interrupt servicing program, and status 0 is set. This method is used to nest two or more interrupts, or to implement nesting level 3 or higher.
Page 200: Servicing Of Interrupts Sharing Vector Address
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.6 Servicing of Interrupts Sharing Vector Address Because interrupt sources INTT1 and INTT2 share vector tables, you should select one or both of the interrupt sources in the following way. (1) To use one interrupt Of the two interrupt sources sharing a vector table, set the interrupt enable flag of the necessary interrupt source to “1”, and clear the interrupt enable flag of the other interrupt source to “0”.
Page 201 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Examples 1. To use both INTT1 and INTT2 as having higher priority, and give priority to INTT2 SKTCLR RETI VSUBBT: CLR1 RETI 2. To use both INTT1 and INTT2 as having lower priority, and give priority to INTT2 SKTCLR RETI VSUBBT: CLR1...
Page 202: Machine Cycles Until Interrupt Servicing
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.7 Machine Cycles Until Interrupt Servicing The number of machine cycles required from when an interrupt request flag (IRQxxx) has been set until the interrupt routine is executed is as follows. (1) If IRQxxx is set while interrupt control instruction is being executed If IRQxxx is set while an interrupt control instruction is being executed, the next instruction is executed.
Page 203 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (2) If IRQxxx is set while instruction other than (1) is executed (a) If IRQxxx is set at the last machine cycle of the instruction under execution In this case, the one instruction following the instruction under execution is executed, three machine cycles of interrupt servicing is performed, and then the interrupt routine is executed.
Page 204: Effective Usage Of Interrupts
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.8 Effective Usage of Interrupts Use the interrupt function effectively as follows. (1) Use different register banks for the normal routine and interrupt routine. The normal routine uses register banks 2 and 3 with RBE = 1 and RBS = 2. For the interrupt service routine for one nested interrupt, use register bank 0 with RBE = 0, so that you do not have to save or restore the registers.
Page 205 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (1) Enabling or disabling interrupt <Main program> <1> Reset <2> EI IE0 EI IET1 <3> <4> DI IE0 <5> <1> All the interrupts are disabled by the RESET signal. <2> An interrupt enable flag is set by the EI IE××× instruction. At this stage, the interrupts are still disabled. <3>...
Page 206 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (2) Example of using INTBT and INT0 (falling edge active): not nested (all interrupts have higher priority) <Main program> Reset <1> <2> A, #1 IM0, A CLR1 IRQ0 <3> IEBT IET0 <4> <1> All the interrupts are disabled by the RESET signal and status 0 is set. RBE = 1 is specified by the reset vector table.
Page 207 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTT2 have lower priority) Reset IEBT IET0 IET2 A, #9 <1> IPS, A INTT0 <2> <1> INTBT is specified as having a higher priority by setting of IPS, and interrupts are enabled at the same time.
Page 208 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (4) Executing pending interrupt - interrupt input while interrupts are disabled - <2> <4> <1> The request flag is held pending even if INT0 is set while the interrupts are disabled. <2> INT0 servicing program is started when the interrupts are enabled by the EI instruction. <3>...
Page 209 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (5) Executing pending interrupt - two interrupts with lower priority occur simultaneously - Reset IET0 <1> <1> If INT0 and INTT0 with a lower priority occur at the same time (while the same instruction is being executed), INT0 with a higher priority is executed first (INTT0 is held pending).
Page 210 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) - IEBT IET0 IET2 MOV A, #9 MOV IPS, A <1> If INTBT with a higher priority and INTT0 with a lower priority occur at the same time, the servicing of the interrupt with the higher priority is started.
Page 211 CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (7) Enabling nesting of two interrupts - INTT0 and INT0 are nested doubly and INTBT and INTT2 are nested singly - <Main program> Reset IET0 IEBT IET2 INTBT <1> <1> When an INTBT that does not enable nesting occurs, the INTBT servicing routine is started. The status is 1.
Page 212: Test Function
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.10 Test Function 7.10.1 Types of test sources The µ PD754244 has a test source, INT2. INT2 is an edge-detection testable input. INT2 (detects falling edge of input to KR4 to KR7 pins) 7.10.2 Hardware controlling test function (1) Test request and test enable flags The test request flag (IRQ2) is set to “1”...
Page 213: Block Diagram Of Kr4 To Kr7
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-10. Block Diagram of KR4 to KR7 KR7/P73 KR6/P72 KR5/P71 KR4/P70 Input buffer Nothing is assigned (in reset mode) Key return reset circuit Falling edge detector Internal bus User’s Manual U10676EJ3V0UM INT2 (IRQ2 setting signal)
Page 214: Format Of Int2 Edge Detection Mode Register (Im2)
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-11. Format of INT2 Edge Detection Mode Register (IM2) Address FB6H IM21 IM20 Cautions1. If the contents of the edge detection mode register are changed, the test request flag may be set. Disable the test input before changing the contents of the mode register. Then, clear the test request flag by the CLR1 instruction and enable the test input.
Page 215: Chapter 8 Standby Function
The following page describes the points to be noted in using the standby mode. Cautions 1. You can operate the µ PD754144 efficiently with a low current consumption at a low voltage by selecting the standby mode and CPU clock. In any case, however, the time described in 6.2.3 Setting CPU clock is required until the operation is started with the new clock when...
Page 216: Settings And Operating Statuses Of Standby Mode
8.1 Settings and Operating Statuses of Standby Mode Table 8-1. Operating Statuses in Standby Mode Instruction to be set Operating status Clock generator Basic interval timer/ watchdog timer Timer counter External interrupt Release signal Note Operation is possible only when the noise eliminator is not selected (when IM02 = 1) by bit 2 of the edge detection mode register (IM0).
Page 217: Block Diagram Of Interrupt Controller
STOP instruction has been executed, and the time set by the BTM register elapses. Then, the normal operation mode is restored. Also, in the µ PD754144, HALT mode is entered immediately after the STOP instruction has been executed, and after a wait of 2 restored.
Page 218: Releasing Standby Mode
(21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz) (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz) µ PD754144: The wait time is fixed to 56/f 2. µ PD754244: The time is set by BTM. µ PD754144: This time is fixed to 2 Remark The broken lines indicate acknowledgment of the interrupt request that releases the standby mode.
Page 219 (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz) (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz) µ PD754144: The wait time is fixed to 56/f Remark The broken lines indicate acknowledgment of the interrupt request that releases the standby mode.
Page 220: Wait Time After Releasing Stop Mode
STOP mode has been released. Therefore, you should select the appropriate wait time depending on the given conditions, and set BTM before setting the STOP mode. µ PD754144: The wait time is fixed to 2 Table 8-2. Selecting Wait Time by BTM...
Page 221: Stop Mode Release By Key Return Reset Or Reset Input
Figure 8-3. STOP Mode Release by Key Return Reset or RESET Input Key return reset or RESET input The differences between release by a key return reset and release by RESET input are as follows. Key return flag (KRF) Watchdog flag (WDF) CHAPTER 8 STANDBY FUNCTION IE×××←0 STOP...
Page 222: Operation After Release Of Standby Mode
This example applies to the operation of the µ PD754244 at f µ PD754244 and f = 1.0 operation of the µ PD754144, the CPU clock and the wait time are different even if the settings are the same. <1> Detect the cause that sets the standby mode such as an interrupt input or power failure by port input.
Page 223 (1) Application example of STOP mode (when using the µ PD754244 at f <When using the STOP mode under the following conditions> • The STOP mode is set at the falling edge of INT0 and released at the rising edge. •...
Page 224 <Program example> (INT0 servicing program, MBE = 0) VSUB0: PORT6.1 PDOWN SET1 BTM.3 WAIT: IRQBT WAIT PORT6.1 PDOWN MOV A, #0011B MOV PCC, A MOV XA.#××H MOV PMGm, XA IEBT IET0 RETI PDOWN: MOV A, #0 MOV PCC, A MOV XA, #00H MOV PMGA, XA IEBT IET0...
Page 225 (2) Application example of HALT mode (when using the µ PD754244 at f <To perform intermittent operation under the following conditions> • The standby mode is set at the falling edge of INT0 and released at the rising edge. • In the standby mode, an intermittent operation is performed at intervals of 175 ms (INTBT). •...
Page 226 <Program example> BTAND4: SKTCLR IRQ0 VSUBBT PORT6.1 PDOWN SET1 BTM.3 WAIT: IRQBT WAIT PORT6.1 PDOWN A, #0011B PCC, A IEn] RETI PDOWN: A, #0 PCC, A IEn] SETHLT: HALT RETI VSUBBT: CLR1 IRQBT SETHLT CHAPTER 8 STANDBY FUNCTION ; INT0 = 1? ;...
Page 227: Chapter 9 Reset Function
9.1 Configuration and Operation of Reset Function Three types of reset signals are used: the external reset signal (RESET), a reset signal from the basic interval timer/watchdog timer, and a key return reset. When any one of these reset signals is input, the internal reset signal is asserted.
Page 228: Reset Operation By Reset Signal
Note µ PD754244: The following two times can be selected by the mask option. (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz) (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz) µ PD754144: The wait time is fixed to 56/f CHAPTER 9 RESET FUNCTION Note...
Page 229: Status Of Each Hardware Unit After Reset
Table 9-1. Status of Each Hardware Unit After Reset (1/3) Hardware Program counter (PC) Carry flag (CY) Skip flags (SK0-SK2) Interrupt status flags (IST0, IST1) Bank enable flags (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) Data memory (EEPROM) EEPROM write control register (EWC) General-purpose registers (X, A, H, L, D, E, B, C)
Page 230 Table 9-1. Status of Each Hardware Unit After Reset (2/3) Hardware Timer Counter (T2) counter (T2) Modulo register (TMOD2) High-level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB Programmable threshold port mode register (PTHM) Clock generation Processor clock control circuit...
Page 231: Watchdog Flag (Wdf), Key Return Flag (Krf)
9.2 Watchdog Flag (WDF), Key Return Flag (KRF) WDF and KRF are mapped to bit 2 and 3 of address FC6H respectively. The contents of WDF and KRF are undefined initially, but they are initialized to “0” by external RESET signal generation.
Page 232: Krf Operation In Generating Each Signal
Figure 9-4. KRF Operation in Generating Each Signal Reset signal generation by KRn input STOP instruction execution External RESET STOP HALT mode mode Operation mode Operation mode Internal reset operation CHAPTER 9 RESET FUNCTION External RESET STOP instruction signal generation execution Operation HALT...
Page 233: Chapter 10 Mask Options
(2) 2 (5.46 ms: at f = 6.0 MHz, 7.81 ms: at f The µ PD754144 has no mask option and the wait time is fixed to 56/f CHAPTER 10 MASK OPTIONS Table 10-1. Selection of Mask Options µ PD754144...
Page 234: Chapter 11 Instruction Set
(6) Table reference instructions ideal for successive reference (7) 1-byte relative branch instruction (8) Easy-to-understand, well-organized NEC standard mnemonics For the addressing modes applicable to data memory manipulation and the register banks valid for instruction execution, refer to 3.2 Bank Configuration of General-Purpose Registers.
Page 235: Bit Manipulation Instruction
11.1.2 Bit manipulation instruction The µ PD754244 has reinforced bit test, bit transfer, and bit Boolean (AND, OR, and XOR) instructions, in addition to the ordinary bit manipulation (set and clear) instructions. The bit to be manipulated is specified in the bit manipulation addressing mode. Three types of bit manipulation addressing modes can be used.
Page 236: Base Number Adjustment Instruction
11.1.4 Base number adjustment instruction Some applications require that the result of addition or subtraction of 4-bit data (which is carried out in binary) be converted into a decimal number or into a number with a base of 6, such as time. Therefore, the µ...
Page 237: Skip Instruction And Number Of Machine Cycles Required For Skipping
11.1.5 Skip instruction and number of machine cycles required for skipping The instruction set of the µ PD754244 configures a program where instructions may be or may not be skipped if a given condition is satisfied. If a skip condition is satisfied when a skip instruction is executed, the instruction next to the skip instruction is skipped and the instruction after next is executed.
Page 238 Representation X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' rp'1 BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL–, DE, DL rpa1 DE, DL...
Page 239 (2) Conventions for explanation of operation A register; 4-bit accumulator B register C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) XA’: Expansion register pair (XA’) BC’: Expansion register pair (BC’) DE’:...
Page 240 (3) Symbols in addressing area field MB = MBE MBS (MBS = 0, 4, 15) MB = 0 MBE = 0: MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1: MB = MBS (MBS = 0, 4, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH...
Page 241 (4) Explanation of machine cycle field S indicates the number of machine cycles required for an instruction with skip to execute the skip operation. The value of S varies as follows. • When skip is executed ... S = 0 •...
Page 242 Instructions Mnemonic Operand Transfer A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @HL...
Page 243 Instructions Mnemonic Operand Bytes Table MOVT XA, @PCDE reference XA, @PCXA XA, @BCDE XA, @BCXA Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL...
Page 244 Instructions Mnemonic Operand RORC Accumulator manipulation Increment/ INCS decrement DECS Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag SET1 manipula- CLR1 tion NOT1 Memory bit SET1 mem.bit manipula- fmem.bit tion pmem. @L @H+mem.bit CLR1 mem.bit...
Page 245 Instructions Mnemonic Operand Bytes AND1 CY, fmem.bit Memory bit CY, pmem.@L manipula- tion CY, @H + mem.bit CY, fmem.bit CY, pmem.@L CY, @H + mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H + mem.bit Note1 Branch addr addr1 !addr $addr $addr1 PCDE PCXA...
Page 246 Instructions Mnemonic Operand Note CALLA !addr1 Subrou- tine/stack control Note CALL !addr Note CALLF !faddr Note Note RETS Note RETI Note The shaded portion is supported only in the MkII mode. All others are supported only in the MkI mode. CHAPTER 11 INSTRUCTION SET Machine Bytes...
Page 247 Instructions Mnemonic Operand Bytes PUSH Subrou- tine/stack control Interrupt control IE××× IE××× Note1 A, PORT Note1 PORT CPU control HALT STOP Special Note2, 3 GETI taddr Notes 1. To execute an IN/OUT instruction, it is necessary that MBE = 0 or MBE = 1, MBS = 15. 2.
Page 248: Opcode Of Each Instruction
11.3 Opcode of Each Instruction (1) Description of symbol of opcode addressing @HL+ @HL– IE××× IEBT IET0 IEEE IET1 IET2 Immediate data for n4 or n8 : Immediate data for mem : Immediate data for bit : Immediate data for n or IE××× : Immediate data for taddr ×...
Page 249 (2) Opcode for bit manipulation addressing *1 in the operand field indicates the following three types. • fmem.bit • pmem.@L • @H+mem.bit The second byte *2 of the opcode corresponding to the above addressing is as follows. 2nd Byte of Opcode fmem.
Page 250 Instruction Mnemonic Operand Transfer A, #n4 reg1, #n4 rp, #n8 A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'...
Page 251 Instruction Mnemonic Operand Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA A, #n4 A, @HL XA, rp' rp'1, XA A, #n4...
Page 252 Instruction Mnemonic Operand INCS Increment/ decrement DECS Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' SET1 Carry flag manipula- CLR1 tion NOT1 Memory bit SET1 mem.bit manipula- tion CLR1 mem.bit mem.bit mem.bit SKTCLR AND1 CY, *1 CY, *1 XOR1...
Page 253 Instruction Mnemonic Operand Branch !addr $addr1 PCDE PCXA BCDE BCXA !addr1 BRCB !caddr Subrou- CALLA !addr1 tine/stack control CALL !addr CALLF !faddr RETS RETI PUSH Interrupt control IE××× IE××× A, PORTn PORTn, A CPU control HALT STOP Special GETI taddr CHAPTER 11 INSTRUCTION SET Opcode 1 0 1 0 1 0 1 1 0 0...
Page 254: Instruction Function And Application
This section describes the functions and applications of the respective instructions. The instructions that can be used and the functions of the instructions differ between the MkI and MkII modes of the µ PD754144, and 754244. Read the descriptions on the following pages according to the following guidance.
Page 255: Transfer Instructions
11.4.1 Transfer instructions MOV A, #n4 ← Function: A n4 n4 = I : 0-FH Transfers 4-bit immediate data n4 to the A register (4-bit accumulator). This instruction has a string effect (group A), and if MOV A, #n4 or MOV XA, #n8 follows this instruction, the string-effect instruction following the instruction executed is processed as NOP.
Page 256 MOV A, @HL ← Function: A (HL) Transfers the contents of the data memory content addressed by register pair HL is transferred to the A register. MOV A, @HL+ ← ← Function: A (HL), L skip if L = 0H Transfers the contents of the data memory addressed by register pair HL to the A register.
Page 257 MOV XA, @HL ← ← Function: A (HL), X (HL+1) Transfers the contents of the data memory addressed by register pair HL to the A register, and the contents of the next memory address to the X register. If the contents of the L register are a odd number, an address whose least significant bit is ignored is transferred. Application example To transfer the data at addresses 3EH and 3FH to register pair XA MOV HL, #3EH...
Page 258 MOV mem, A ← Function: (mem) A mem = D Transfers the contents of the A register to the data memory addressed by 8-bit immediate data mem. MOV mem, XA ← Function: (mem) A, (mem+1) Transfers the contents of the A register to the data memory addressed by 8-bit immediate data mem and the contents of the X register to the next memory address.
Page 259 XCH A, @HL ↔ Function: A (HL) Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL. XCH A, @HL+ (HL), L ← L+1 ↔ Function: A skip if L = 0H Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL.
Page 260 XCH XA, @HL ↔ ↔ Function: A (HL), X (HL+1) Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL, and the contents of the X register with the contents of the next address. If the contents of the L register are an odd number, however, an address whose least significant bit is ignored is specified.
Page 261: Table Reference Instructions
11.4.2 Table reference instructions MOV XA, @PCDE ← Function: XA ROM (PC +DE) 11-8 Transfers the lower 4 bits of the table data in the program memory addressed when the lower 8 bits (PC program counter (PC) are replaced with the contents of register pair DE, to the A register, and the higher 4 bits to the X register.
Page 262 Caution The MOVT XA, @PCDE instruction usually references the table data in page where the instruction exists. If the instruction is at address ××FFH, however, the table data in the next page is referenced instead of the table data in the page where the instruction exists.
Page 263 MOVT XA, @PCXA ← Function: XA ROM (PC +XA) 11-8 Transfers the lower 4 bits of the table data in the program memory addressed when the lower 8 bits (PC program counter (PC) are replaced with the contents of register pair XA, to the A register, and the higher 4 bits to the X register.
Page 264 MOVT XA, @BCXA ← Function: XA ROM (BCXA) Transfers the lower 4 bits of the table data (8-bit) in the program memory addressed by the B register and the contents of registers C, X, and A, to the A register, and the higher 4 bits to the X register. However, on the µ...
Page 265: Bit Transfer Instructions
11.4.3 Bit transfer instructions MOV1 CY, fmem.bit MOV1 CY, pmem.@L MOV1 CY, @H+mem.bit ← Function: CY (bit specified by operand) Transfers the contents of the data memory addressed in the bit manipulating addressing mode (fmem.bit, pmem.@L, or @H+mem.bit) to the carry flag (CY). MOV1 fmem.bit, CY MOV1 pmem.@L, CY MOV1 @H+mem.bit, CY...
Page 266: Operation Instructions
11.4.4 Operation instructions ADDS A, #n4 ← Function: A A+n4; Skip if carry. n4 = l Adds 4-bit immediate data n4 to the contents of the A register. If a carry occurs as a result, the next instruction is skipped. The carry flag is not affected. If this instruction is used in combination with ADDC A, @HL or SUBC A, @HL instruction, it can be used as a base number adjustment instruction (refer to 11.1.4 Base number adjustment instruction).
Page 267 ADDC A, @HL ← Function: A, CY A+ (HL) +CY Adds the contents of the data memory addressed by register pair HL to the contents of the A register, including the carry flag. If a carry occurs as a result, the carry flag is set; if not, the carry flag is reset. If the ADDS A, #n4 instruction is placed next to this instruction, and if a carry occurs as a result of executing this instruction, the ADDS A, #n4 instruction is skipped.
Page 268 SUBS XA, rp’ ← Function: XA XA – rp’; Skip if borrow. Subtracts the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) from the contents of register pair XA, and sets the result to register pair XA. If a borrow occurs as a result, the next instruction is skipped. The carry flag is not affected.
Page 269 SUBC rp’1, XA ← Function: rp’1, CY rp’1 – XA – CY Subtracts the contents of register pair XA from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), including the carry flag, and sets the result to specified register pair rp’1. If a borrow occurs as a result, the carry flag is set;...
Page 270 OR A, #n4 ← Function: A n4 n4 = l : 0-FH ORs 4-bit immediate data n4 with the contents of the A register, and sets the result to the A register. Application example To set the lower 3 bits of the accumulator to 1 OR A, #0111B OR A, @HL ←...
Page 271 XOR A, @HL ← Function: A (HL) Exclusive-ORs the contents of the data memory addressed by register pair HL with the contents of the A register, and sets the result to the A register. XOR XA, rp’ ← Function: XA rp’...
Page 272: Accumulator Manipulation Instructions
11.4.5 Accumulator manipulation instructions RORC A ← ← Function: CY Rotates the contents of the A register (4-bit accumulator) 1 bit to the left with the carry flag. RORC A NOT A ← Function: A Takes 1’s complement of the A register (4-bit accumulator) (inverts the bits of the accumulator). CHAPTER 11 INSTRUCTION SET ←...
Page 273: Increment/Decrement Instructions
11.4.6 Increment/decrement instructions INCS reg ← Function: reg reg+1; Skip if reg = 0 Increments the contents of register reg (X, A, H, L, D, E, B, or C). If reg = 0 as a result, the next instruction is skipped.
Page 274: Compare Instructions
11.4.7 Compare instructions SKE reg, #n4 Function: Skip if reg = n4 n4 = I Skips the next instruction if the contents of register reg (X, A, H, L, D, E, B, or C) are equal to 4-bit immediate data SKE @HL, #n4 Function: Skip if (HL) = n4 n4 = I Skips the next instruction if the contents of the data memory addressed by register pair HL are equal to 4-bit...
Page 275: Carry Flag Manipulation Instructions
11.4.8 Carry flag manipulation instructions SET1 CY ← Function: CY Sets the carry flag. CLR1 CY ← Function: CY Clears the carry flag. SKT CY Function: Skip if CY = 1 Skips the next instruction if the carry flag is 1. NOT1 CY ←...
Page 276: Memory Bit Manipulation Instructions
11.4.9 Memory bit manipulation instructions SET1 mem.bit ← Function: (mem.bit) 1 mem = D Sets the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem. SET1 fmem.bit SET1 pmem.@L SET1 @H+mem.bit Function: (bit specified by operand) Sets the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@L, or @H+mem.bit).
Page 277 SKT fmem.bit SKT pmem.@L SKT @H+mem.bit Function: Skip if (bit specified by operand) = 1 Skips the next instruction if the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@L, or @H+mem.bit) is 1. SKF mem.bit Function: Skip if (mem.bit) = 0 mem = D : 00H to FFH, bit = B...
Page 278 AND1 CY, fmem.bit AND1 CY, pmem.@L AND1 CY, @H+mem.bit ← Function: CY (bit specified by operand) ANDs the content of the carry flag with the contents of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@L, or @H+mem.bit), and sets the result to the carry flag. OR1 CY, fmem.bit OR1 CY, pmem.@L OR1 CY, @H+mem.bit...
Page 279: Branch Instructions
11.4.10 Branch instructions BR addr ← Function: PC addr 11-0 addr = 0000H to 0FFFH Branches to an address specified by immediate data addr. This instruction is an assembler directive and is replaced by the assembler at assembly time with the optimum instruction from the BR !addr, BRCB !caddr, and BR $addr instructions.
Page 280 BR $addr1 ← addr1 Function: PC 11-0 addr1 = (PC–15) to (PC–1), (PC+2) to (PC+16) This is a relative branch instruction that has a branch range of (–15 to –1) and (+2 to +16) from the current address. It is not affected by a page boundary or block boundary. BRCB !caddr ←...
Page 281 BR PCDE ← Function: PC + DE 11-0 11-8 ← ← D, PC Branches to an address specified by the lower 8 bits of the program counter (PC of register pair DE. The higher bits of the program counter are not affected. Caution The BR PCDE instruction usually branches execution to the page where the instruction exists.
Page 282 BR BCDE ← Function: PC BCDE 11-0 Example To branch to an address specified by the contents of the program counter replaced by the contents of registers B, C, D, and E However, the PC of the µ PD754244 is 12 bits. The contents of PC are replaced by the contents of registers C, D and E.
Page 283: Subroutine/Stack Control Instructions
11.4.11 Subroutine/stack control instructions CALLA !addr1 ×, ×, MBE, RBE, (SP–3) ← Function: (SP–2) ← (SP–4) , (SP–5) ← (SP–6) 11-8 ← ← addr1, SP 11-0 CALL !addr I/II Function: [MkI mode] ← (SP–1) , (SP–2) ← (SP–3) MBE, RBE, 0, 0 ←...
Page 284 CALLF !faddr I/II Function: [MkI mode] ← (SP–1) , (SP–2) ← (SP–3) MBE, RBE, 0, 0 ← ← (SP–4) , SP 11-8 ← 0+faddr 11-0 faddr = 0000H to 07FFH [MkII mode] ×, ×, MBE, RBE ← (SP–2) ← (SP–3) , (SP–4) ←...
Page 285 I/II ← Function: [MkI mode] 11-8 ← ← ← [MkII mode] PC 11-8 ← ×, ×, MBE, RBE Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter (PC), memory bank enable flag (MBE), and register bank enable flag (RBE), and then increments the contents of the SP. Caution All the flags of the program status word (PSW) other than MBE and RBE are not restored.
Page 286 PUSH rp ← ← Function: (SP–1) , (SP–2) Saves the contents of register pair rp (XA, HL, DE, or BC) to the data memory (stack) addressed by the stack pointer (SP), and then decrements the contents of the SP. The higher 4 bits of the register pair (rp 4 bits (rp : A, L, E, or C) are saved to the stack addressed by (SP–2).
Page 287: Interrupt Control Instructions
11.4.12 Interrupt control instructions ← Function: IME (IPS.3) Sets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to “1” to enable interrupts. Acknowledging an interrupt is controlled by an interrupt enable flag corresponding to the interrupt. EI IE×××...
Page 288: Input/Output Instructions
11.4.13 Input/output instructions IN A, PORTn ← Function: A PORTn n = N : 3, 6, 7, 8 Transfers the contents of a port specified by PORTn (n = 3, 6, 7, 8) to the A register. Caution When this instruction is executed, it is necessary that MBE = 0 or (MBE = 1, MBS = 15). n can be 3, 6, 7, 8. The data of the output latch is loaded to the A register in the output mode, and the data of the port pins are loaded to the register in the input mode.
Page 289: Cpu Control Instruction
11.4.14 CPU control instruction HALT ← Function: PCC.2 Sets the HALT mode (this instruction sets the bit 2 of the processor clock control register). Caution Make sure that a NOP instruction follows the HALT instruction. STOP ← Function: PCC.3 Sets the STOP mode (this instruction sets the bit 3 of the processor clock control register). Caution Make sure that a NOP instruction follows the STOP instruction.
Page 290: Special Instructions
11.4.15 Special instructions SEL RBn ← Function: RBS n n = N : 0-3 Sets 2-bit immediate data n to the register bank select register (RBS). SEL MBn ← Function: MBS n n = N : 0, 4, 15 Transfers 4-bit immediate data n to the memory bank select register (MBS). GETI taddr I/II Function: taddr = T...
Page 291 References the 2-byte data at the program memory address specified by (taddr), (taddr+1) and executes it as an instruction. The area of the reference table consists of addresses 0020H to 007FH. Data must be written to this area in advance. Write the mnemonic of a 1-byte or 2-byte instruction as the data as is.
Page 292 Application example MOV HL, #00H MOV XA, #FFH Replaced by GETI CALL SUB1 SUB2 HL00: HL, #00H XAFF: XA, #FFH CSUB1: TCALL SUB1 BSUB2: TBR SUB2 GETI HL00 GETI BSUB2 GETI CSUB1 GETI XAFF CHAPTER 11 INSTRUCTION SET ; MOV HL, #00H ;...
Page 293: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available to support development of systems using the µ PD754244. With the 75XL Series, a relocatable assembler that can be used in common with any model in the series is used in combination with a device file dedicated to the model being used.
Page 294 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are available as the debugging tools for the µ PD754244. The following table shows the system configuration of the in-circuit emulators. Note1 IE-75000-R The IE-75000-R is an in-circuit emulator that debugs the hardware and software of an application system using the 75X Series or 75XL Series.
Page 295 OS of IBM PC The following OSs are supported as the OS for IBM PCs. Version PC DOS Ver.5.02 to Ver.6.3 Note J6.1/V to J6.3/V MS-DOS Ver.5.0 to Ver.6.22 Note Note 5.0/V to 6.2/V Note IBM DOS J5.02/V Note Only the English mode is supported. Caution Although Ver.5.00 or above has a task swap function, this function cannot be used with this software.
Page 296 IE-75000-R or IE-75001-R Centronics l/F RS-232-C Host machine IE control PC-9800 series program lBM PC/AT [Symbolic debugging possible] Relocatable assembler Device file In-circuit emulator Emulation probe Emulation board EP-754144GS Note 1 IE-75300-R-EM 1. The in-circuit emulator is not provided with IE-75300-R-EM (Sold separately). Notes 2.
Page 297: Appendix B Ordering Mask Rom
After your program has been developed, you can place an order for mask ROM using the following procedure. <1> Reservation for mask ROM ordering Inform NEC Electronics of when you intend to place an order for the mask ROM. (NEC’s response may be delayed if we are not informed in advance.) <2>...
Page 298: Appendix C Instruction Index
APPENDIX C INSTRUCTION INDEX Instruction Index (By Function) [Transfer instruction] A, #n4 ... 242, 255 reg1, #n4 ... 242, 255 XA, #n8 ... 242, 255 HL, #n8 ... 242, 255 rp2, #n8 ... 242, 255 A, @HL ... 242, 256 A, @HL+ ...
Page 299 APPENDIX C INSTRUCTION INDEX A, @HL ... 243, 269 XA, rp' ... 243, 269 rp'1, XA ... 243, 269 A, #n4 ... 243, 270 A, @HL ... 243, 270 XA, rp' ... 243, 270 rp'1, XA ... 243, 270 A, #n4 ... 243, 270 A, @HL ...
Page 300 PCXA ... 245, 281 BCDE ... 245, 282 BCXA ... 245, 282 !addr1 ... 245, 279 BRCB !caddr ... 245, 280 addr ... 247, 282 [Subroutine/stack control instruction] CALLA !addr1 ... 246, 283 CALL !addr ... 246, 283 CALLF !faddr ... 246, 284 TCALL !addr ...
Page 301: Instruction Index (Alphabetical Order)
Instruction Index (Alphabetical Order) ADDC A, @HL ... 243, 267 ADDC rp'1, XA ... 243, 267 ADDC XA, rp' ... 243, 267 ADDS A, #n4 ... 243, 266 ADDS A, @HL ... 243, 266 ADDS rp'1, XA ... 243, 266 ADDS XA, rp' ...
Page 302 A, @rpa1 ... 242, 256 HL, #n8 ... 242, 255 mem, A ... 242, 258 mem, XA ... 242, 258 reg1, A ... 242, 258 reg1, #n4 ... 242, 255 rp'1, XA ... 242, 258 rp2, #n8 ... 242, 255 XA, mem ...
Page 303 APPENDIX C INSTRUCTION INDEX @H+mem.bit ... 244, 277 SKTCLR fmem.bit ... 244, 277 SKTCLR pmem.@L ... 244, 277 SKTCLR @H+mem.bit ... 244, 277 STOP ... 247, 289 SUBC A, @HL ... 243, 268 SUBC rp'1, XA ... 243, 268 SUBC XA, rp' ...
Page 304: Appendix D Hardware Index
BS ... 78 BSB0 to BSB3 ... 184 BT ... 114 BTM ... 115 CY ... 74 ERE ... 81 EWC ... 81 EWE ... 81 EWST ... 81 EWTC4 to EWTC6 ... 81 IE0 ... 190 IE2 ... 212 IEBT ...
Page 305 APPENDIX D HARDWARE INDEX SBS ... 61, 70 SK0 to SK2 ... 75 SP ... 70 T0, T1 ... 54 T2 ... 53 TC2 ... 133, 138 TM0 ... 127 TM1 ... 128 TM2 ... 130 TMOD0, TMOD1 ... 54 TMOD2 ...
Page 306: Appendix E Revision History
Change of EEPROM write time and number of write operations Addition of Note when development tool is used Addition of list of functions of µ PD754144, 754244, and 75F4264 Change of device file name Upgrading of version of OS supported by development tools...

This manual is also suitable for:

Pd754244

NEC PD754144 User Manual

Chapter 1 General

Functional Outline

Ordering Information

Differences between Series Products

Block Diagram

Pin Configuration (Top View)

Chapter 2 Pin Functions

Pin Functions of Μ PD754244

Description of Pin Functions

Pin I/O Circuits

Processing of Unused Pins

Chapter 3 Features of Architecture and Memory Map

Bank Configuration of Data Memory and Addressing Modes

Bank Configuration of General-Purpose Registers

Memory-Mapped I/O

Chapter 4 Internal Cpu Function

Function to Select Mki and Mkii Modes

Program Counter (PC)

Program Memory (ROM)

Data Memory (RAM)

General-Purpose Registers

Accumulator

Stack Pointer (SP) and Stack Bank Select Register (SBS)

Program Status Word (PSW)

Bank Select Register (BS)

Chapter 5 Eeprom

EEPROM Configuration

EEPROM Features

EEPROM Write Control Register (EWC)

Interrupt Related to EEPROM Control

EEPROM Manipulation Method

Cautions on EEPROM Writing

Chapter 6 Peripheral Hardware Function

Digital I/O Ports

Clock Generator

Basic Interval Timer/Watchdog Timer

Timer Counter

Programmable Threshold Port (Analog Input Port)

Bit Sequential Buffer

Chapter 7 Interrupt and Test Functions

Configuration of Interrupt Controller

Types of Interrupt Sources and Vector Table

Hardware Controlling Interrupt Function

Interrupt Sequence

Nesting Control of Interrupts

Servicing of Interrupts Sharing Vector Address

Machine Cycles until Interrupt Servicing

Effective Usage of Interrupts

Application of Interrupt

Test Function

Chapter 8 Standby Function

Settings and Operating Statuses of Standby Mode

Releasing Standby Mode

Operation after Release of Standby Mode

Application of Standby Mode

Chapter 9 Reset Function

Configuration and Operation of Reset Function

Watchdog Flag (WDF), Key Return Flag (KRF)

Chapter 10 Mask Options

Pin Mask Options

Oscillation Stabilization Wait Time Mask Option

Chapter 11 Instruction Set

Unique Instructions

Instruction Set and Operation

Opcode of each Instruction

Instruction Function and Application

Appendix A Development Tools

Appendix B Ordering Mask Rom

Appendix C Instruction Index

Instruction Index (by Function)

Instruction Index (Alphabetical Order)

Appendix D Hardware Index

Appendix E Revision History

Quick Links

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Summary of Contents for NEC PD754144