1. Manuals
  2. Brands
  3. NEC Manuals
  4. Computer Hardware
  5. PD75402A
  6. User manual

NEC PD75402A User Manual

4-bit single-chip microcomputer
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
USER'S MANUAL
4-BIT SINGLE-CHIP MICROCOMPUTER
© NEC Corporation 1989
PD75402A
PD75402A
PD75P402
Document No.
IEU1270C
(O. D. No. IEU-644D)
Date Published March 1994 P
Printed in Japan

Advertisement

Table of Contents
loading

Related Manuals for NEC PD75402A

Summary of Contents for NEC PD75402A

  • Page 1 USER'S MANUAL 4-BIT SINGLE-CHIP MICROCOMPUTER © NEC Corporation 1989 PD75402A PD75402A PD75P402 Document No. IEU1270C (O. D. No. IEU-644D) Date Published March 1994 P Printed in Japan...
  • Page 2 If customers intend to use NEC devices for above applications or those intend to use “Standard” quality grade NEC devices for the application not intended by NEC, please contact our sales people in advance.
  • Page 3 Major Revisions in This Version Section Description Amendment: Fig. 5-52 “Data Transmission from Slave Device P.117 to Master Device” P.179 to 181 Change: Appendix B “Development Tools” The mark shows main revised points.
  • Page 4 This manual is intended for user engineers who wish to understand the PD75402A’s, 75P402’s functions and design an application system using them. OBJECTIVE The objective of this manual is for the user to understand the PD75402A’s, 75P402’s hardware functions shown below. COMPOSITION This manual is composed roughly of the following contents.
  • Page 5 PG-1500 Controller User's Manual Other Related Documents Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Control Guarantee Guide Microcomputer Related Products Guide. Other Manufacturers Note The above documents are subject to change without notice.

  • Page 6: Table Of Contents

    CHAPTER 1. GENERAL ... OUTLINE OF FUNCTIONS ..ORDERING INFORMATION AND QUALITY GRADE ... DIFFERENCES BETWEEN PD75402A AND PD75402, 75P402 ... BLOCK DIAGRAM ... PIN CONFIGURATION ... 1.5.1 28-Pin Plastic DIP (600 mil), Shrink DIP (400 mil) ... 1.5.2 44-Pin Plastic QFP ( CHAPTER 2.
  • Page 7 Clock Generation Circuit Configuration ... 5.2.2 Clock Generation Circuit Function and Operation ... 5.2.3 CPU Clock Setting ... 5.2.4 Differences Between PD75402A and PD75402 ... CLOCK OUTPUT CIRCUIT ... 5.3.1 Clock Output Circuit Configuration ... 5.3.2 Clock Output Mode Register (CLOM) ...
  • Page 8 MACHINE CYCLES BEFORE INTERRUPT SERVICING ... 135 INTERRUPT APPLICATIONS ... 137 CHAPTER 7. STANDBY FUNCTION ..141 STANDBY MODE SETTING AND OPERATION STATES ... 142 STANDBY MODE RESET ... 143 OPERATION AFTER STANDBY MODE RESET ... 145 STANDBY MODE APPLICATION ... 145 CHAPTER 8.
  • Page 9 Use of Variable Minimum Instruction Execution Time Function ... 59 5-15 Change of after Power-On Reset ... 60 5-16 Clock Generation Circuit - Differences between PD75402A and PD75402 ... 61 5-17 PD75402 Processor Clock Control Register Format ... 62 5-18 Clock Output Circuit Configuration ... 63 5-19 Clock Output Mode Register Format ...

  • Page 10: Title

    Fig. No. 5-32 Example of SBI Serial Bus System Configuration ... 93 5-33 SBI Transfer Timing ... 95 5-34 Bus Release Signal ... 96 5-35 Command Signal ... 96 5-36 Address ... 97 5-37 Slave Selection by Address ... 97 5-38 Command ...
  • Page 11 Table No. Differences Between PD75402A and PD75402, 75P402 ... 4 Port Pin List ... 11 List of Pins Other than Port Pins ... 12 Port 0’s, 1’s Dual-Function Pins ... 13 Pin Input/Output Types ... 17 Data Memory Configuration and Address Range in Each Addressing Mode ...

  • Page 12: Chapter 1. General

    PD75P402 is also capable of high-speed processing. It is possible to reduce the burden on the host microcomputer by using the PD75402A, 75P402 as the slave microcomputer by using the PD75402A, 75P402 as the slave microcomputer for decentralized processing. The PD75402A, or 75P402 is most suitable for slave processes for the following devices such as the key input control, LED, etc.

  • Page 13: Outline Of Functions

    • N-ch open-drain input/ output port (LED direct drivable) Pull-up resistor • Pull-up resistor built-in control possible by software • Pull-up resistor built-in control possible by mask option ( PD75402A only) Clock output • 1.05 MHz, 524 kHz, 65.5 kHz (at 4.19 MHz operation) •...

  • Page 14: Ordering Information And Quality Grade

    : ROM code number (2) Quality Grade Standard Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. CHAPTER 1. GENERAL...

  • Page 15: Differences Between Pd75402A And Pd75402, 75P402

    DIFFERENCES BETWEEN PD75402A AND PD75402, 75P402 Table 1-1 shows the differences between the PD75402A and the PD75402, 75P402. Otherwise the PD75402A and the PD75402, 75P402 have the same functions and are pin-compatible. Table 1-1 Differences Between PD75402A and PD75402, 75P402...

  • Page 16: Block Diagram

    BASIC PROGRAM INTERVAL COUNTER(11) TIMER INTBT SERIAL ROM (PROM) SO/SB0 INTERFACE PROGRAM MEMORY INTCSI 1920 INT0 INTERRUPT CONTROL INT2 CLOCK OUTPUT CONTROL Remarks Parentheses for the PD75P402. SP (5) GENERAL REG. DECODE CONTROL DATA MEMORY 64 x 4 bits 8 bits CPU CLOCK CLOCK CLOCK...

  • Page 17: Pin Configuration

    P60 to P63 : Port 6 Remarks Parentheses for the PD75P402. * If using the PD75P402 and the printed circuit board commonly in the PD75402A, the NC pin is to be set to the GND potential. CHAPTER 1. GENERAL P12/INT2...
  • Page 18 (2) PROM mode A0 to A14 O0 to O7 CHAPTER 1. GENERAL : Address input : Data input/output : Chip enable input : Output enable input : Power supply : Program power supply : Ground...

  • Page 19: 44-Pin Plastic Qfp ( 10Mm)

    (1) Normal operating mode Remarks Parentheses for the PD75P402. * If using the PD75P402 and the printed circuit board commonly in the PD75402A, the NC pin of the 30-pin corresponding to the PD75P402’s V CHAPTER 1. GENERAL 44 43 42 41 40 39 38 37 36 35...
  • Page 20 (2) PROM mode CHAPTER 1. GENERAL 44 43 42 41 40 39 38 37 36 35 34 PD75P402GB-3B4 12 13 14 15 16 17 18 19 20 21 22...

  • Page 21: Chapter 2. Pin Functions

    The PD75402A operates by the pin functions in the normal operating mode. For the PD75P402’s pin functions, the 2 modes of the normal operating mode ( PD75402A mode) and the PROM mode are available. The operating mode switches according to the V...

  • Page 22: Pd75402A Pin Function List

    P60 to P63 Input/output Remarks In the PD75402A, 8-bit input/output with 2 ports making up a pair is impossible. For the status of each pin at reset, see CHAPTER 8 “RESET FUNCTION”. CHAPTER 2. PIN FUNCTIONS Table 2-1 Port Pin List A 4-bit input port (Port 0).

  • Page 23: List Of Pins Other Than Port Pins

    2.1.2 List of Pins Other Than Port Pins Table 2-2 List of Pins Other than Port Pins Pin Name Input/Output Dual-Function Pin INT0 Input INT2 Input Input Input/output Input/output Input/output Input/output X1, X2 Input RESET Input NC*8 Remarks For the status of each pin at reset, see CHAPTER 8 “RESET FUNCTION”. * If using the PD75P402 and the printed circuit board commonly, the NC pin should be connected directly to V CHAPTER 2.

  • Page 24: Normal Operating Mode

    NORMAL OPERATING MODE 2.2.1 P00 to P03 (Port 0) ... SCK, SO/SB0, SI Dual-Function Input P10, P12 (Port 1) ... INT0, INT2 Dual-Function Input P00 to P03 are the 4-bit input port: Port 0’s input pins. P10 and P12 are the 2-bit input port: Port 1’s input pins. Ports 0 and 1 also have the functions of the various control signal pins shown in Table 2-1 in addition to the functions as input ports.

  • Page 25: P20 To P23 (Port 2), P30 To P33 (Port 3), P50 To P53 (Port 5), P60 To P63 (Port 6)

    (POGA). PD75402A’s Port 5 allows to designate to build in the pull-up resistor by mask option bit-wise. The PD75P402’s Port 5 cannot be built in with the pull-up resistor. Ports 3, 5 and 6 have large-current output and can drive the LED directly.

  • Page 26: X1, X2

    2.2.7 X1, X2 (Crystal) The built-in clock oscillation crystal/ceramic input. It is also possible to supply the clock from the exterior. (a) Crystal/Ceramic Oscillation PD75402A Crystal Resonator or Ceramic Oscillator (Standard 4.194304 MHz) 2.2.8 RESET (Reset) A low level active system reset input pin. It has Schmitt-triggered input and is built in with the noise eliminator by analog delay.

  • Page 27: Prom Mode

    PROM MODE The PROM mode is designatable in the PD75P402 alone. 2.3.1 A0 to A14 (Address) ... Input A 15-bit address input pin at PROM write/verify, read. As the PROM built into the PD75P402 has 2K bytes, it is addressed by the low-order 11 bits (A0 to A10). A11 to A14 should be fixed to the low level. 2.3.2 O0 to O7 (Data) ...

  • Page 28: Pin Input/Output Circuits

    P60 to P63 RESET Remarks A circle indicates Schmitt-triggered input. CHAPTER 2. PIN FUNCTIONS Table 2-4 Pin Input/output Types Input/Output Type PD75402A F - A F - B B - C B - C E - B E - B...
  • Page 29 Type A (for Types E - B) P-ch N-ch An input buffer of the CMOS standard Type B Schmitt-triggered input having hysteresis characteristics Type B - C P.U.R. P.U.R. P-ch enable P. U. R : Pull-Up Resistor CHAPTER 2. PIN FUNCTIONS Type D (for Type E - B, F - A, Y - D) data output...
  • Page 30 Type F - B P.U.R. enable output disable P-ch data output N-ch disable output disable P. U. R : Pull-Up Resistor Type M P.U.R (Mask Option) IN/OUT data N-ch (+10 V Withstand output Voltage) disable Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P.

  • Page 31: Unused Pin Treatment

    The P00 and RESET pins are provided with the test mode setting function of test mode (for IC test) which tests the internal operation of the PD75402A in addition to the functions described in 2.2.1 and 2.2.8. When a voltage exceeding V is applied to either of these pins, the test mode is set.

  • Page 32: Chapter 3. Features Of Architecture And Memory Map

    The high-order 4-bit address is determined by the memory bank (MB) to be accessed. The PD75402A is built in with only Memory bank 0 and 15 and does not require bank switching unlike other products of the 75X series. The memory bank to be accessed is determined by the addressing mode and the address to be specified (see Tables 3-1 and 3-2).

  • Page 33: Data Memory Configuration And Address Range In Each Addressing Mode

    CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP Table 3-1 Data Memory Configuration and Address Range in Each Addressing Mode Data Memory Adress 000H General Register Area 003H Data Memory Static RAM (Memory Bank 0) 020H Stack Area 03FH Not built in. F80H Peripheral FB0H...

  • Page 34: Addressing Mode List

    CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP Notation Addressing Mode mem. bit The bit indicated by bit of the address indicated by mem. However: 1-bit direct Memory bank 0 is accessed if mem = 00H to 3FH. addressing Memory bank 15 is accessed if mem = 80H to FFH. The address indicated by mem.

  • Page 35: Data Memory Addressing Modes

    3.1.2 Data Memory Addressing Modes In the PD75402A, the 6 types of addressing modes listed on Table 3-2 are available for the data memory space for efficient addressing per the bit length of the data to be processed. Also in the PD75402A, the memory bank to be accessed is fixed by the addressing mode unlike in other products of the 75X series.

  • Page 36: Static Ram Address Updating Method

    CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP (3) 8-bit direct addressing (mem) An addressing mode to specify the whole data memory space directly by the instruction’s operand per 8 bits. The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3EH and MB = 15 if it is 80H to FEH.
  • Page 37 CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP (5) Specific address bit manipulation addressing (fmem. bit) An addressing mode to specify each bit of the input/output port, interrupt, etc. flag, etc. of the peripheral hardware directly by the instruction’s operand. Consequently, the data memory addresses to which this addressing mode is applied are FB0H to FBFH, FF0H to FFFH.
  • Page 38 The Evachip packaged on the board for evaluation can address the whole area of Memory bank 0 in this addressing mode unlike in the PD75402A. To eliminate such a difference during the evaluation, a value not to access beyond the range of 20H to 3FH should be set in the stack pointer.

  • Page 39: Memory-Mapped I/O

    Specify the address to be manipulated by the direct 8-bit manipulation addressing mem. Mem is an even address, however. Table 3-4 summarizes the PD75402A’s I/O map. The items shown in this table have the following meaning. • Symbol: the instruction’s operand column. IME is excepted, however.

  • Page 40: Pd75402A I/O Map

    Clock output mode register (CLOM) FDCH Pull-up resistor specify register Group A (POGA) Remarks is an interrupt enable flag. is an interrupt request flag. Table 3-4 PD75402A I/O Map (1/2) No. of Manipulatable Addressing 1 Bit 4 Bits 8 Bits IRQBT...
  • Page 41 * 1. Bits 3 and 1: W; bit 2: R. 2. Bits 3 and 2: R; bits 1 and 0: W. 3. Bits 3 and 1: R/W; bit 2: R; bit 0: W. Table 3-4 PD75402A I/O Map (2/2) No. of Manipulatable Addressing...

  • Page 42: Chapter 4. Internal Cpu Functions

    CHAPTER 4. INTERNAL CPU FUNCTIONS PROGRAM COUNTER (PC) ... 11 BITS An 11-bit binary counter to hold the program memory address information. PC10 The program counter operates as follows. • Normal operation The content is incremented automatically according to the number of bytes of the instruction every time one is executed.

  • Page 43: Program Memory (Rom)

    CHAPTER 4. INTERNAL CPU FUNCTIONS PROGRAM MEMORY (ROM) ... 1,920 WORDS A mask programmable ROM of a 1,920-word The program memory is addressed by the program counter. It is also possible to read the table data in the ROM by the table refer instruction (MOVT). It is possible to branch to any area of the program memory by the branch instruction, subroutine call instruction (see Fig.

  • Page 44: Data Memory (Ram)

    Area (1) Data area The PD75402A’s data area consists of the static RAM (64 words 4 bits). The data area is used to store processing data and is operated by the memory manipulation instruction. The static RAM is mapped to Memory bank 0 by 64 available as the general register area (000H to 003H) and the stack area (020H to 03FH).
  • Page 45 It is impossible to access an address to which the peripheral hardware is not assigned since the data memory is not built in. (See Table 3-4 “ PD75402A I/O Map".)

  • Page 46: General Register

    CHAPTER 4. INTERNAL CPU FUNCTIONS GENERAL REGISTER ... 4 4 BITS The general register is assigned to a specific address of the data memory. There are four 4-bit registers (H, L, X, A). While each general register is operated per 4 bits, HL and XA make up register pairs, each of which is operated per 8 bits.

  • Page 47: Accumulator

    CHAPTER 4. INTERNAL CPU FUNCTIONS ACCUMULATOR In the PD75402A, the A register and the XA register pair function as accumulators. The 4-bit data process instruction is executed mainly by the A register and the 8-bit data process instruction is executed mainly by the XA register pair.

  • Page 48: Stack Pointer (Sp)

    STACK POINTER (SP) ... 8 BITS The PD75402A uses a static RAM as the stack memory (LIFO format). The 8-bit register holding the top address information of such a stack memory area is the stack pointer (SP). Fig. 4-7 shows its format.

  • Page 49: Data Saved To Stack Memory

    CHAPTER 4. INTERNAL CPU FUNCTIONS PUSH Instruction Stack Register Pair SP - 2 Low Order Register Pair SP - 1 High Order Fig. 4-9 Data Restored from Stack Memory POP Instruction Stack Register Pair Low Order Register Pair SP + 1 High Order SP + 2 Fig.

  • Page 50: Program Status Word (Psw)

    CHAPTER 4. INTERNAL CPU FUNCTIONS PROGRAM STATUS WORD (PSW) ... 8 BITS The program status word (PSW) consists of various flags concerning closely the processor operation. Fig. 4-10 shows its configuration. Saved to the stack memory per 8 bits at the interrupt acceptance and restored from the stack memory per 8 bits at the RETI instruction execution (see Figs.

  • Page 51: Interrupt Status Flag Indication Content

    CHAPTER 4. INTERNAL CPU FUNCTIONS Example Take AND of bit 3 at address 3FH and P33 and set the result in CY. SET1 CLR1 AND1 (2) Skip flag (SK2, SK1, SK0) The skip flag is a flag to store the skip status. It is set/reset automatically as the CPU executes an instruction. It is impossible for the user to operate it directly by the program.

  • Page 52: Chapter 5. Peripheral Hardware Functions

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS DIGITAL INPUT/OUTPUT PORTS The PD75402A has the following digital input/output ports on chip: Ports 0 through 3, 5 and 6. The PD75402A uses memory mapped I/O, and all input/output ports are mapped onto data memory space.

  • Page 53: Digital Input/Output Port Types, Characteristics And Configuration

    * LED direct drive capability On the PD75402A, a pull-up resistor can be incorporated on chip for all port pins except pins P00, P10. On the PD75P402, a pull-up resistor can be incorporated on chip for all port pins except pins P00, P10, and P50 through P53 (see section 5.5).

  • Page 54: Configuration Of Ports 0 And 1

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-2 Configuration of Ports 0 and 1 Selcetor CSIM Input Buffer POGA Bit 1 Input Buffer or f Noise Elimination Circuit Input Buffer with Hysteresis Characteristics INT2 INT0 Internal Pull-Up Resistors POGA Bit 0 P-ch Output Buffer with Capability of Switching between Push-Pull...

  • Page 55: Configuration Of Port 3

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Input Buffer Output Latch PM 3 n PMGA Bit n Remarks n = 0 to 3 Fig. 5-3 Configuration of Port 3 PM 3 n=0 POGA PM 3 n=1 Bit 3 Output Buffer Pull-Up Resistor P-ch P 3 n...

  • Page 56: Configuration Of Ports 2 And 6

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-4 Configuration of Ports 2 and 6 Input Buffer PM2/ PM60 to PMGB Bit 2, PMGA bits 4 to 7 * Input/output mode specification is performed by bit 2 (PM2) of PMGB for port 2 and by bits 4 to 7 (PM60 to 63) of PMGA for port 6.

  • Page 57: Input/Output Mode Setting

    With a RESET input, all bits of each port mode register are cleared to zero, and thus the output buffer is turned off and all ports are set to input mode. Fig. 5-5 Configuration of Port 5 Input Buffer PM5=0 PM5=1 N-ch Open-Drain Output Buffer Pull-Up Resistors (Mask Option; PD75402A Only)

  • Page 58: Digital Input/Output Port Handling Instructions

    5.1.3 Digital Input/Output Port Handling Instructions As all the input/output ports in the PD75402A are mapped onto data memory space, all data memory handling instructions can be used. Those data memory handling instructions which are considered particularly useful for input/output pin operations are shown in Table 5-2 together with their scope of application.

  • Page 59: List Of Input/Output Pin Handling Instructions

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) Bit handling instructions Direct addressing of specific address bits (fmem.bit) can be used on all digital input/output ports. Example To OR P50 and P31 and output the result to P61. SET1 AND1 CY, PORT5.0 CY, PORT3.1 CLRP SET1...

  • Page 60: Digital Input/Output Port Operations

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.4 Digital Input/Output Port Operations Port and port pin operations when a data memory handling instruction is executed for a digital input/output port differ according to the input/output mode setting (see Table 5-3). This is because, as can be seen from the input/ output port configurations, data fetched onto the internal bus is treated as pin data in input mode and as output latch data in output mode.

  • Page 61: Operations With Input/Output Port Handling Instructions

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Table 5-3 Operations with Input/Output Port Handling Instructions Instruction Executed PORTn.bit PORTn.bit AND1 CY, PORTn.bit CY, PORTn.bit XOR1 CY, PORTn.bit A, PORTn A, PORTn PORTn, A PORTn, A A, PORTn INCS PORTn SET1 PORTn.bit CLR1 PORTn.bit SKTCLR PORTn.bit...

  • Page 62: Internal Pull-Up Resistors

    5.1.5 Internal Pull-up Resistors The PD75402A can incorporate internal pull-up resistors for all port pins except P00 and P10. The PD75P402 can incorporate internal pull-up resistors for all port pins except P00, P10, and P50 through P53. As shown in Table 5-4, internal pull-up resistors can be specified by software or by a mask option (although specification by mask option is not possible on the PD75P402).

  • Page 63: Format Of Pull-Up Resistor Specification Register

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-7 Format of Pull-Up Resistor Specification Register Address FDCH – – – The timing for switching of pull-up resistor presence/ absence by the setting of the pull-up resistor specification register (POGA) is shown in Fig. 5-8. Fig.

  • Page 64: Digital Input/Output Port Input/Output Timing

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.6 Digital Input/Output Port Input/Output Timing The timing for outputting data to the output latch and fetching pin data or output latch data onto the internal bus is shown in Fig. 5-9. Fig. 5-9 Digital Input/Output Port Input/Output Timing (a) Data fetch by 1-machine-cycle instruction Instruction Execution...

  • Page 65: Clock Generation Circuit

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS CLOCK GENERATION CIRCUIT The clock generation circuit supplies various clocks to the CPU and peripheral hardware, and controls the operating mode of the CPU. 5.2.1 Clock Generation Circuit Configuration The configuration of the clock generation circuit is shown in Fig. 5-10. Fig.

  • Page 66: Clock Generation Circuit Function And Operation

    CPU operating mode, such as standby mode etc. Clock generation circuit operation is determined by the processor clock control register (PCC). Upon RESET input, the PCC is cleared to 0000 and the PD75402A operates in low-speed mode (15.3 s: when operating at 4.19 MHz).

  • Page 67: Processor Clock Control Register Format

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-11 Processor Clock Control Register Format Address FB3H PCC3 PCC2 PCC1 PCC0 Note When using a calue of f such that 4.19 MHz < f = 11) is set as CPU clock frequency, 1 machine cycle is less than 0.95 s and the standard minimum value 0.95 s is not kept.

  • Page 68: System Clock Oscillation Circuit External Circuitry

    The system clock oscillation circuit oscillates by means of a crystal resonator or ceramic resonator connected to the X1 and X2 pins (standard: 4.194304 MHz). An external clock can also be input. Fig. 5-12 System Clock Oscillation Circuit External Circuitry (a) Crystal/ceramic oscillation PD75402A Crystal Resonator (Standard 4.194304 MHz) or Ceramic Oscillator Note 1.
  • Page 69 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-13 Example of Poor Resonator Connection Circuit (2/2) (c) Signal line close to varyin high current PD75402A High current (e) Signal is picked up. PD75402A (d) Current flows an oscillator power supply line. (potentials at A, B and C fluctuate.)

  • Page 70: Cpu Clock Setting

    5.2.3 CPU Clock Setting The CPU clock is the clock supplied to the PD75402A’s internal CPU, and the reciprocal of this clock is the minimum instruction execution time (defined in this manual as 1 machine cycle). On the PD75402A, can be switched in 3 steps by setting the PCC. In other words, with the same system clock oscillator frequency f , the minimum instruction execution time can be changed in 3 steps.

  • Page 71: Change Of After Power-On Reset

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS As the PCC is set in 0 by RESET input, range is wide). For this reason, in a system with a slow supply voltage rise (such as a system with a high- capacitance capacitor connected), correct operation is possible even when an adequate supply voltage cannot be attained after a power-on reset.

  • Page 72: Differences Between Pd75402A And Pd75402

    5.2.4 Differences Between PD75402A and PD75402 Part of the clock generation circuit differs between the PD75402A and the PD75402. The PD75402 does not include the sections enclosed in dotted lines. Fig. 5-16 Clock Generation Circuit - Differences between PD75402A and PD75402...

  • Page 73: Pd75402 Processor Clock Control Register Format

    FB3H PCC3 PCC2 PCC1 Note 1. Ensure that 0 is always written to PCC bit 0. 2. Unlike the PD75402A, in the PD75402, switching s at 4.19 MHz) cannot be specified. PD75402 Processor Clock Control Register Format Symbol CPU clock selection bits when f...

  • Page 74: Clock Output Circuit

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to peripheral LSIs, etc. 5.3.1 Clock Output Circuit Configuration The configuration of the clock output circuit is shown in Fig. 5-18. Fig.

  • Page 75: Clock Output Mode Register (Clom)

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3.2 Clock Output Mode Register (CLOM) CLOM is a 4-bit register used to control clock output. CLOM is set by a 4-bit memory handling instruction. Bit handling instructions cannot be used. Also, this register cannot be read. RESET input clears CLOM to zero and selects the clock output disabled state.

  • Page 76: Clock Output Procedure

    5.3.4 Examle of Remote Control Application The PD75402A clock output functions can be used in remote control applications. The remote control output carrier frequency is selected by the clock frequency selection bits of the clock output mode register. Pulse output enabling/disabling is performed by software control of the enable/disable bit.

  • Page 77: Basic Interval Timer

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS BASIC INTERVAL TIMER The PD75402A is equipped with an 8-bit basic interval timer which has the following functions: (a) Standard time generation (2 different time intervals) Reading counter contents This basic interval timer can also be used as a watchdog timer for the detection of inadvertent program looping.

  • Page 78: Basic Interval Timer Mode Register (Btm)

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.2 Basic Intercal Timer Mode Register (BTM) BTM is a 4-bit register which controls the operation of the basic interval timer. BTM is set by a 4-bit memory handling instruction. Bit operations are not possible. Example To set the interrupt generation interval to 1.95 ms (4.19 MHz).

  • Page 79: Basic Interval Timer Operation

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.3 Basic Interval Timer Operation The basic interval timer (BT) is constantly incremented by the clock from the clock generation circuit, and sets the interrupt request flag (IRQBT) when it overflows. The BT count operation cannot be stopped. Either of two times can be selected as the interrupt generation interval by setting the BTM (Fig.

  • Page 80: Examples Of Basic Interval Timer Applications

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.4 Examples of Basic Interval Timer Applications Example In this example the basic interval timer is enabled, and the interrupt generation interval is set to 1.95 ms (at 4.19 MHz operation). MB15 A, #1111B BTM,A IEBT Example Example of watchdog timer application...

  • Page 81: Serial Interface

    5.5.1 Serial Interface Functions The PD75402A incorporates a clocked 8-bit serial interface, with the following three modes available. (1) Operation-halted mode This mode is used when no serial transfer is to be performed, and allows power dissipation to be reduced.

  • Page 82: Serial Interface Configuration

    Fig. 5-23 Example of SBI System Configuration Master CPU Note When the PD75402A is used as a slave CPU, its address is limited to the range C0H to C7H. 5.5.2 Serial Interface Configuration The serial interface block diagram is shown in Fig. 5-24.

  • Page 83: Serial Interface Block Diagram

    Test CSIM P03/SI P02/SO/SB0 P01/SCK Fig. 5-24 Serial Interface Block Diagram Internal Bus Slave Address Register (SVA) Match Signal Address Comparator Shift Registe (SIO)r RELD Bus Release/ CMDD Command/Ac- Knowledge ACKD Detection Circuit Serial Clock Copunter Serial Clock Control Cirucit Bit Test Manipulation SBIC...
  • Page 84 (7) Slave address register (SVA), address comparator In SBI mode, this register is used when the PD75402A is used as a slave device. The slave sets its own specification number (slave address value) in the SVA register. The master outputs a slave address to select a specific slave.

  • Page 85: Register Functions

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (8) INTCSI control circuit Controls the generation of interrupt requests. In the following case, the interrupt requests (INTCSI) are generated and interrupt request flags (IRQCSI) are set (see Fig. 6-1 “Interrupt Control Circuit Block Diagram”). •...

  • Page 86: Serial Operating Mode Register (Csim) Format

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-25 Serial Operating Mode Register (CSIM) Format (1/2) Address FE0H CSIE Remarks (R) Read only (W) Write only Note 0 must be written to CSIM bits 4, 2, 0. Serial clock selection bit (W) CSIM1 3-Wire Serial I/O Mode Remarks...
  • Page 87 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-25 Serial Operating Mode Register (CSIM) Format (2/2) Wake-up function specification bit (W) IRQCSI set at end of every serial transfer in each mode. Used only in SBI mode. IRQCSI is set only when the address received after bus release matches the slave address register data (wake-up status).
  • Page 88 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Remarks The operating mode can be selected according to the setting of CSIE and CSIM3. CSIE CSIM3 The P10/SCK pin status depends on the setting of CSIE and CSIM0 as shown below. CSIE CSIM1 The following procedure should be used to clear CSIE during a serial transfer. Clear the interrupt enable flag to set the interrupt disabled state.

  • Page 89: Serial Bus Interface Control Register (Sbic) Format

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) Serial bus interface control register (SBIC) The format of the serial bus interface control register (SBIC) is shown in Fig. 5-26. SBIC is an 8-bit register composed of bits which control the serial bus and flags which indicate various statuses of the input data from the serial bus, and is mainly used in the SBI mode.
  • Page 90 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (2/3) Bus release trigger bit (W) The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this RELT bit (RELT = 1), after which the RELT bit is automatically cleared (0). Note SB0 must not be cleared during a serial transfer: Ensure that it is cleared before a transfer is started or after it is completed.
  • Page 91 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (3/3) Acknowledge enable bit (R/W) Disables automatic output of the acknowledge signal (ACK) (outpt by ACKT is possibel). When set before end of transfer ACKE When set after end of transfer Acknowledge detection flag (R) Clearing Conditions (ACKD = 0) ACKD...

  • Page 92: Configuration Around Shift Register

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Shift register (SIO) The configuration around the shift register is shown in Fig. 5-27. SIO is an 8-bit register which carries out parallel- to-serial conversion and performs serial transmission/reception (shift operations) in synchronization with the serial clock.
  • Page 93 In the SBI mode, the slave address register (SVA) has the following two functions: (a) Slave address detection Used when the PD75402A is connected to the serial bus as a slave device. The high-order 5 bits of the SVA register are fixed at 11000 by hardware. Therefore, the address assigned to the PD75402A is limited to the range C0H to C7H.

  • Page 94: Operation-Halt Mode

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5.4 Operation-Halted Mode The operation-halted mode is used when no serial transfer is performed, allowing power dissipation to be reduced. In this mode, the shift register does not perform shift operations and can be used as an ordinary 8-bit register. When the RESET signal is input the operation-halted mode is set.

  • Page 95: 3-Wire Serial I/O Mode Operation

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Serial clock selection bit (W) The P01/SCK pin status depends on the CSIM1 setting as shown below. CSIM1 P01/SCK Pin Status High impedance High level The following procedure should be used to clear CSIE during a serial transfer. Clear the interrupt enable flag (IECSI) to set the interrupt disabled state.
  • Page 96 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (a) Serial operating mode register (CSIM) When the 3-wire serial I/O mode is used, CSIM is set as shown below (see 5.5.3 (1) “Serial operating mode register” for full details of CSIM). CSIM is manipulated by 8-bit memory manipulation instructions. Bit manipulation of bits 7, 6 and 5 is also possible.
  • Page 97 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Signal from address comparator (R) Clearing Conditions (COI = 0) COI* When slave address register (SVA) and shift register data do not match. * A CIO read is valid only before the start of after completion of a serial transfer. During a transfer an indeterminate value will be read.
  • Page 98 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) When the 3-wire serial I/O mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register” for full details of SBIC). SBIC is manipulated by bit manipulation instructions. Reset input clears the SBIC register to 00H.

  • Page 99: 3-Wire Serial I/O Mode Timing

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) Communication operation In the 3-wire serial I/O mode, data transmission/ reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Shift register shift operations are performed in synchronization with the fall of the serial clock (SCK). Then send data is held in the SO latch output from the SO pin.

  • Page 100: Relt & Cmdt Operation

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Serial clock selection Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the following clocks can be selected. Table 5-6 Serial Clock Selection and Use (in 3-Wire Serial I/O Mode) Mode Serial Clock Register...

  • Page 101: Shift Register (Sio) And Internal Bus Configuration

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (5) Data transfer order The PD75402A 3-wire serial I/O mode differs from that of other 75X series products in that it is not possible to switch between MSB and LSB as the first bit. Serial transfer is performed MSB-first.
  • Page 102 ; Transfer data setting & start of transfer Note From the second time onward, the transfer can be started by setting data in SIO (MOV SIO, XA or XCH XA, SIO). PD75402A SO/SB0 In this application the PD75402A SI pin can be used as an input port.
  • Page 103 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) To transmit/receive MSB-first data using an external clock (slave operation). PD75402A P01/SCK SO/SB0 <Sample program> Main routine XA, #80H CSIM, XA ; Serial operation stopped, external clock specification XA, TDATA SIO, XA ; Transfer data setting & start of transfer...

  • Page 104: Sbi Mode Operation

    5.5.6 SBI Mode Operation The SBI (serial bus interface) is a high-speed serial interface which conforms to the the NEC serial bus format. The SBI is a single-master high-speed serial bus. Its format includes the addition of bus configuration functions to the clocked serial I/O method to enable communication to be performed with multiple devices using two signal lines.
  • Page 105 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) SBI functions Since conventional serial I/O methods have only data transfer functions, when a serial bus is configured with multiple devices connected a large number of ports and wires are required for Chip Select signal and command/ data differentiation, busy status recognition, etc.

  • Page 106: Sbi Transfer Timing

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) SBI definition The SBI serial data format and the meaning of the signals used are explained in the following section. Serial data transmitted via the SBI is classified into three types: Commands, addresses and data. Serial data forms a frame with the configuration shown below.

  • Page 107: Bus Release Signal

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (a) Bus release signal (REL) The bus release signal indicates that the SB0 line has changed from low to high when the SCK line is high (when the serial clock is not being output). This signal is output by the master. The bus release signal indicates that the master is about to send an address to a slave.

  • Page 108: Address

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (c) Address An address is 8-bit data output by the master to slaves connected to the bus line in order to select a particular slave. Bus Release Signal Command Signal The 8-bit data following the bus release signal and command signal is defined as an address. In a slave this condition is detected by hardware and a check is performed by hardware to see if the 8-bit data matches the slave’s own specification number (slave address).

  • Page 109: Command

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (d) Command & data The master performs command transmission to or data transmission/reception to/from the slave selected by address transmission. Command Signal The 8-bit data following the command signal is defined as a command. 8-bit data with no command signal is defined as data.

  • Page 110: Acknowledge Signal

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (e) Acknowledge signal (ACK) The acknowledge signal is used to confirm serial data reception between the sender and receiver. Fig. 5-40 Acknowledge Signal [When output in synchronization with 11th SCK clock cycke] [When output in synchronization with 9th SCK clock cycke] The acknowledge signal is a one-shot pulse synchronized with the fall of SCK after an 8-bit data transfer.

  • Page 111: Busy Signal & Ready Signal

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Busy signal (BUSY), ready signal (READY) The busy signal notifies the master that a slave is preparing for data transmission/reception. The ready signal notifies the master that a slave is ready for data transmission/reception. With the SBI a slave reports its busy status to the master by driving the SB0 line low. The busy signal is output following the acknowledge signal output by the master or slave.
  • Page 112 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Register setting When the device is used in the SBI mode, setting can be performed by means of the following two registers: • Serial operating mode register (CSIM) • Serial bus interface control register (SBIC) (a) Serial operating mode register (CSIM) When the SBI mode is used, CSIM is set as shown below (see 5.5.3 (1) “Serial operating mode register”...
  • Page 113 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Wake-up function specification bit (W) IRQCSI set at end of every serial transfer in SBI mode mask state. User only when functioning as a slave in SBI mode. IRQCSI is set only when the address received after bus release matches the slace address register data (wake-up status).
  • Page 114 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) When the SBI mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register” for full details of SBIC). SBIC is manipulated by bit manipulation instructions. Reset input clears the SBIC register to 00H.
  • Page 115 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Bus release detection flag (R) Clearing Conditions (RELD = 0) When a transfer start instruction is executed RELD When RESET is input When CSIE = 0 (See Fig. 5-25) When SVA and SIO do not match when an address is received Command detection flag (R) Clearing Conditions (CMDD = 0)

  • Page 116: Serial Clock Selection And Use (In Sbi Mode)

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Busy enable bit (R/W) Disablin of automatic busy signal output Busy signal output is stopped in synchronization with the fall of SCK immediately after execution ofthe clearing instruction. BSYE The busy signal is output in synchronization with the fall or SCK following the acknowledge signal.

  • Page 117: Relt, Cmdt, Reld & Cmdd Operation (Master)

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (5) Signals The operation of signals and flags in SBIC in the SBI mode are shown in Figs. 5-42 to 5-47, and SBI signals are listed in Table 5-8. Fig. 5-42 RELT, CMDT, RELD & CMDD Operation (Master) RELT CMDT RELD...

  • Page 118: Ackt Operation

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS ACKT Note ACKT must not be set before the end of a transfer. Fig. 5-44 ACKT Operation When set in this interval ACK signal is output in 1 clock interval immediately after ACKT is set.

  • Page 119: Acke Operation

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (a) When ACKE = 1 on completion of transfer ACKE (b) When ACKE is set after completion of transfer ACKE When ACKE is set in this interval and ACKE = 1 on next fall of SCK (c) When ACKE = 0 on completion of transfer ACKE (d) When ACKE = 1 interval is short...

  • Page 120: Ackd Operation

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (a) When ACK signal is output in 9th SCK clock interval ACKD (b) When ACK signal is output after 9th SCK clock interval ACKD (c) Clearing timing when transfer start directive is given during busy state ACKD BSYE Fig.

  • Page 121: Signals In Sbi Mode

    Output Signal Name Definition Device SB0 rising edge when Bus release Master signal (REL) SCK = 1 SB0 falling edge when Command Master signal (CMD) SCK = 1 Low-level signal output to Acknowledge Master/ SB0 in 1 SCK clock intercal singnl (ACK) slave after serial receive comple-...
  • Page 122 Output Signal Name Definition Device Synchronization clock for Serial Clock Master (SCK) output of address/command/ data, ACK signal, Synchronous BUSY signal, etc. Address/command/ data is transferred in first 8 cycles. Address Master 8-bit data transferred in synchronization with SCK (A7 to A0) after REL signl and CMD signal output.

  • Page 123: Pin Configuration Diagram

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (6) Pin configuration The configuration of the serial clock pin (SCK) and the serial data bus pin SB0 is as shown below. (a) SCK ... Pin for input/output of serial clock Master ... CMOS, push-pull output Slave ...
  • Page 124 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (7) Address match detection method In the SBI mode, master address communication is used to select a specific slave and start communication. Address match detection is performed by hardware. A slave address register (SVA) is provided, and IRQCSI is set only when the address sent from the master and the value set is SVA match in the wake-up state (WUP = 1).

  • Page 125: Address Transmission From Master Device To Slave Device (Wup = 1)

    Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1) Master Device Processing (Transmission Side) Program Write CMDT RELT CMDT Setting Setting Setting Processing to SIO Hardware Operation Transfer Line SCK Pin SB0 Pin Slave Device Processing (Reception Side) Program Processing...

  • Page 126: Command Transmission From Master Device To Slave Device

    Fig. 5-50 Command Transmission from Master Device to Slave Device Master Device Processing Transmission Side) Program Write CMDT Setting Processing to SIO Hardware Operation Transfer Line SCK Pin SB0 Pin Slave Device Processing Reception Side) Program Processing Hardware CMDD Setting Operation Serial Transmit Operation Command...

  • Page 127: Data Transmission From Master Device To Slave Device

    Fig. 5-51 Data Transmission from Master Device to Slave Device Master Device Processing (Transmission Side) Write Program to SIO Processing Hardware Operation Transfer Line SCK Pin SB0 Pin Slave Device Processing (Reception Side) Program Processing Hardware Operation Serial Transmit Operation Data Serial Receive Operation Interrupt Servicing...

  • Page 128: Data Transmission From Slave Device To Master Device

    Fig. 5-52 Data Transmission from Slave Device to Master Device Master Device Processing (Reception Side) Program FFH Write Processing to SIO Hardware Stop- Operation page Transfer Line SCK Pin BUSY READY SB0 Pin Slave Device Processing (Transmission Side) Write Program Processing Hardware BUSY...
  • Page 129 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (10) Start of transfer When the following two conditions are met a serial transfer is started by setting transfer data in the shift register (SIO). • The serial interface operatio enable/disable bit (CSIE) = 1. •...

  • Page 130: Example Of Serial Bus Configuration

    Also, the master can be changed by a command. (a) Serial bus configuration In the serial bus configuration in the application examples given here, the PD75402A is connected to the bus line as one of the devices on the serial bus.
  • Page 131 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Description of commands Command types The following command types are used in these application examples. READ command WRITE command END command STOP command STATUS command : Reads slave-side status. RESET command CHGMST command : Passes mastership to slave side. (ii) Communication procedure The procedure for communication between master and slave is as follows.

  • Page 132: Read Command Transfer Format

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (iii) Command formats The transfer format of each command is shown below. READ command This command performs a read from the slave. The read data length is variable between 1 and 256 bytes, and is specified as a parameter by the master. If 00H is specified as the data length, this is interpreted as a 256-byte data transfer specification.

  • Page 133: Stop Command Transfer Format

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS After the slave receives the data length, if the area for storing the receive data is at least as large as that data length, the slave returns ACK. If the data storage area is too small, ACK is not returned and an error is generated.

  • Page 134: Status Command Transfer Format

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS STATUS command This command is used to read the status of the currently selected slave. Fig. 5-57 STATUS Command Transfer Format STATUS Command Remarks M : Output by master S : Output by slave The format of the status byte returned by the slave is shown below. Fig.

  • Page 135: Reset Command Transfer Format

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS RESET command This command is used to change the currently selected slave to non-selected status. All slaves can be placed in non-selected status by sending the RESET command. Fig. 5-59 RESET Command Transfer Format Remarks M : Output by master S : Output by slave CHGMST command...

  • Page 136: Master And Slave Operations After An Error

    CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (iv) Error occurrence Operation in the event of an error in communication is described below. A slave indicates the occurrence of an error by failing to return ACK to the master. When an error occurs, the status bit indicating the occurrence of an error is set and all command processing being executed is canceled.

  • Page 137: Chapter 6. Interrupt Functions

    CHAPTER 6. INTERRUPT FUNCTIONS On the PD75402A there are 3 vectored interrupt sources and one testable input, enabling a wide variety of applications to be handled. Moreover, the PD75402A’s interrupt control circuit has the following special features, making possible extremely fast interrupt servicing.

  • Page 138: Interrupt Control Circuit Block Diagram

    Sampling Clock Noise Elimination Circuit IRQBT Edge INT0/P10 Detection IRQ0 Circuit INTCSI IRQCSI Rising Edge INT2/P12 IRQ2 Detection Circuit Analog Delay Noise Elimination Circuit Fig. 6-1 Interrupt Control Circuit Block Diagram Internal Bus Interrupt Enable Flag (IE VRQ1 VRQ2 VRQ3 IST0 Decoder Priority...

  • Page 139: Interrupt Source Types And Vector Table

    INTERRUPT SOURCE TYPES AND VECTOR TABLE The PD75402A’s interrupt source types and interrupt vector table are shown in Table 6-1 and Fig. 6-2. Table 6-1 Interrupt Request Source Types Interrupt Request Generation Source INTBT (Basic time interval signal from basic interval timer)

  • Page 140: 6.3 Interrupt Control Circuit Hardware

    6.3 INTERRUPT CONTROL CIRCUIT HARDWARE (1) Interrupt request flag & interrupt enable flag There are four interrupt request flags (IRQ follows. INT0 interrupt request flag (IRQ0) INT2 interrupt request flag (IRQ2) BT interrupt request flag (IRQBT) Serial interface interrupt request flag (IRQCSI) An interrupt request flag is set (1) by generation of an interrupt request and cleared (0) automatically by execution of an interrupt service.

  • Page 141: Configuration Of Int0 And Int2

    (2) External interrupt input pin hardware The configuration of INT0 and INT2 is shown in Fig. 6-3. Sampling Clock INT0/P10 Noise Elimina- tion Circuit Selector Analog Delay INT2/P12 Noise Elimina- tion Circuit Input Buffer with Hysteresis Characteristics Input Buffer INT0 functions as an external interrupt input on which sampling clock noise elimination and detected edge selection can be performed.

  • Page 142: Int0 Noise Elimination Circuit Input/Output Timing

    Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing Sampling Cycle ) or Less INT0 Sheped Output 1 to 2 Times t INT0 Sheped Output INT0 Sheped Output 2 or More Times INT0 Sheped Output Remarks or 64/f Specification of the detected edge of the INT0 input and selection of the sampling clock is performed by the edge detection mode register (IM0).

  • Page 143: Edge Detection Mode Register Format

    The format of the edge detection mode register (IM0) which is used to select the detected edge is shown in Fig. 6-6. IM0 is set by 4-bit memory handling instructions. On an RESET input, all bits of IM0 are cleared to 0 and the rising edge is specified for INT0. Fig.

  • Page 144: Ist0 Interrupt Servicing Status

    (4) Interrupt status flag The interrupt status flag (IST0) is the flag which shows the status of the processing currently being executed by the CPU, and is contained in the PSW. The interrupt priority control circuit performs interrupt control according to the contents of this flag as shown in Table 6-3.

  • Page 145: Interrupt Sequence

    INTERRUPT SEQUENCE When an interrupt is generated, it is serviced by the procedure shown in Fig. 6-8. Interrupt (INT IRQxxx set Corresponding VRQn generation Save PC and PSW contents to stack memory; place data in vector table corresponding to initiated VRQn into PC. Change IST0 contents to 1 Reset (0) acknowledged IRQxxx Branch to start address of interrupt service program proccessing...

  • Page 146: Machine Cycles Before Interrupt Servicing

    MACHINE CYCLES BEFORE INTERRUPT SERVICING On the 75X, the machine cycles from the setting of the interrupt request flag (IRQn) until execution of the interrupt routine program are as shown below. (1) When IRQn is set during execution of an interrupt control instruction When IRQn is set during execution of an interrupt control instruction, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following execution of the next instruction.
  • Page 147 (2) When IRQn is set during execution of an instruction other than an interrupt control instruction (a) When IRQn is set in the last machine cycle of the instruction being executed In this case, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following execution of the instruction which follows the instruction being executed.

  • Page 148: Interrupt Applications

    INTERRUPT APPLICATIONS When the interrupt function is used, the following setting are first carried out in the main program. The interrupt enable flag corresponding to the interrupt to be used is set to “1” (EI IE If INT0 is used, the active edge is selected (IM0 setting). The interrupt master enable flag (IME) is set to “1”...
  • Page 149 (2) Example using INTBT, INT0 (falling edge active), and INTCSI <Main Program> CLR1 All interrupts disabled and status 0 set by RESET input. INT0 set to falling edge active. Interrupts enabled by EI and EI IE On fall of INT0, INT0 interrupt service program is started, status is changed to 1 and all interrupts are disabled.
  • Page 150 (3) Pending interrupt execution - interrupt input in interrupt disabled state <Main program> Reset EI IE0 EI IECSI Although INT0 is set in the interrupt disabled state, the interrupt flag is held pending. The INT0 service program is started at point at which interrupts are enabled by the EI instruction. Same as The INTCSI service routine is started at the point at which the pending INTCSI is enabled.
  • Page 151 (4) Pending interrupt execution <Main Program> If INT0 and INTCSI are generated simultaneously (during execution of the same instruction), INT0, which has the higher interrupt priority, is executed first (INTCSI is held pending). When the INT0 service program is ended by the RETI instruction, the pending INTCSI service program is started.

  • Page 152: Chapter 7. Standby Function

    Data memory low voltage (up to V the contents of data memory at an ultra-low current drain. The PD75402A STOP mode cannot be reset by interrupt request. It is reset only by RESET input. (2) HALT mode This mode stops the CPU operation clock. The system clock oscillator continues to oscillate. In this mode, the...

  • Page 153: Standby Mode Setting And Operation States

    1. When the STOP mode is set, the X1 pin is shorted internally to V oscillator leakage. Therefore, do not use the STOP mode with systems that use an external clock. 2. STOP mode reset by interrupt request differs as follows for the PD75402A and the evachip installed on the evaluation board: •...

  • Page 154: Standby Mode Reset

    (2) HALT mode reset by RESET input When the RESET input drops from high to low, the HALT mode is reset and the PD75402A enters the reset state. When the RESET input level returns from low to high, the program branches to the reset start address and instruction execution begins.

  • Page 155: Standby Mode Reset Operation

    Fig. 7-1 Standby Mode Reset Operation (a) STOP mode reset by RESET input STOP Instruction RESET Input Operating STOP Mode Mode Oscillation Oscillation Stopped Clock (b) HALT mode reset by RESET input HALT Instruction RESET Input Operating Mode Clock (c) HALT mode reset by interrupt generation HALT Instruction Standby...

  • Page 156: Operation After Standby Mode Reset

    OPERATION AFTER STANDBY MODE RESET (1) When the standby mode was reset by RESET input, normal reset operation is executed. (STOP and HALT modes) (2) When the standby mode was reset by interrupt request generation, whether or not a vector interrupt is executed when the CPU resumes instruction execution is determined by the contents of the interrupt master enable flag (IME).

  • Page 157: Chapter 8. Reset Function

    When low level is input to the RESET pin, system reset is applied and the hardware enters the state shown in Table 8-1. When the RESET input goes from low level to high level, the reset state is released. Then, the contents of the lower-order three bits of address 000H of the reset vector table are set into program counter (PC) bits 10 to 8 and the contents of the low-order three bits of address 001H are set into PC bits 7 to 0 and the program branches and begins executing from that branch address.

  • Page 158: State Of Hardware After Reset

    Table 8-1 State of Hardware after Reset Hardware Program counter (PC) Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0) Stack pointer (SP) Data Memory (RAM) General register (X, A, H, L) Basic interval timer Counter (BT) Mode register (BTM) Shift register (SIO) Serial interface...

  • Page 159: Chapter 9. Instruction Set

    The 75X series instruction set is an improved and expanded version of old PD7500 series instruction set. It is a revolutionary new instruction set which retains succession from the PD7500 series. The PD75402A instruction set is a 75X instruction subset, and has the following features:...

  • Page 160: Special Instruction

    SPECIAL INSTRUCTIONS This section outlines the special instructions of the PD75402A instruction set. 9.1.1 Bit Manipulation Instructions PD75402A bit manipulation can be performed by various instructions, such as the following: Bit set SET1 SET1 Bit clear : CLR1 CLR1 Bit test : Bit test : Bit test &...

  • Page 161: Base Correction Instructions

    Skip Instruction and Number of Machine Cycles Required by Skip With the PD75402A instruction set, a program is formed by condition judgment by skip. If the skip condition is satisfied when a skip instruction is executed, the following instruction is skipped and the instruction after the instruction is executed.

  • Page 162: Instruction Set And Its Operation

    Instead of mem, fmem, bit, etc., various kinds of registers and flag symbols shown in Table 3-4 can be written as labels (however, in the case of fmem there are restrictions on the labels that can be written. See Table 3-3 "Applicable Addressing Modes at Peripheral Hardware Operation" and Table 3-4" PD75402A I/O Map" for details. Identifier...
  • Page 163 (3) Description of addressing area field symbols MB = 0 MB = 0 (00H to 3FH) MB = 15 (80H to FFH) MB = 15, fmem = FB0H to FBFH, addr = 000H to 77FH addr = (Current PC) – 15 to (Current PC) – 1, (Current PC) + 16 to (Current PC) + 2 caddr = 000H to 77FH faddr = 000H to 77FH...
  • Page 164 Mnemonic Operand Note 1 Bytes A, #n 4 XA, #n 8 HL, #n 8 A, @HL @HL, A A, mem XA, mem mem, A mem, XA A, @HL A, mem XA, mem A, reg1 MOVT XA, @PCXA A, #n 4 ADDS A, @HL ADDC...
  • Page 165 Note Mnemonic Operand mem. bit SET 1 f mem. bit mem. bit CLR 1 f mem. bit mem. bit f mem. bit mem. bit f mem. bit SKTCLR f mem. bit AND 1 CY, f mem. bit OR 1 CY, f mem. bit XOR 1 CY, f mem.
  • Page 166 Mnemonic Operand Bytes Note 1 A, PORTn PORTn, A HALT STOP Note 1. Instruction Group 2. I/O instructions CHAPTER 9. INSTRUCTION SET Machine Operation Cycle PORTn (n = 0 – 3, 5, 6) PORTn A (n + 2, 3, 5, 6) Set HALT Mode (PCC.2 Set STOP Mode (PCC.3 No Operation...

  • Page 167: Operation Code Of Each Instruction

    OPERATION CODE OF EACH INSTRUCTION (1) Description of operation code symbols IEBT IECSI In : Immediate data for n4, n8 Dn : Immediate data for mem Bn : Immediate data for bit Nn : Immediate data for n, IE An : Immediate data for [relative address distance with branch address (2 to 16)] - 1 Sn : Immediate data for one’s complement of [relative address distance with branch address (15 to 1)] (2) Bit manipulation addressing operation code bit-addr of the second byte of the operation code of an instruction with fmem.
  • Page 168 Mnemonic Operand Note 1 A, #n 4 rp, #n 8 A, @HL @HL, A A,mem XA, mem mem, A mem, XA A, @HL A, mem XA, mem A, reg1 MOVT XA, @PCXA A, #n 4 ADDS A, @HL ADDC A, @HL A, @HL A, @HL A, @HL...
  • Page 169 Mnemonic Note 1 Operand mem. bit SET 1 f mem. bit mem. bit CLR 1 f mem. bit mem. bit f mem. bit mem. bit f mem. bit SKTCLR f mem. bit AND 1 CY, f mem. bit OR 1 CY, f mem.

  • Page 170: Instruction Functions And Application

    INSTRUCTION FUNCTIONS AND APPLICATION 9.4.1 Move Instructions MOV A, #n4 Function: A n4; n4 = I to I : 0 to FH Moves 4-bit immediate data n4 to the A register (4-bit accumulator). This instruction has a stacking effect (group A). When placed after a MOV A, #n4 or MOV XA, #n8 instruction, stack instructions following the executed instruction are processed as NOP.
  • Page 171 MOV @HL, A Function: (HL) Moves the contents of the A register to the data memory addressed by the contents of register pair HL. MOV A, mem Function: A (mem); mem = D Moves the data memory contents addressed by 8-bit immediate data mem to the A register. MOV XA, mem Function: A (mem), X...
  • Page 172 XCH A, @HL Function: A (HL) Exchanges the contents of the A register and the contents of the data memory addressed by the contents of register pair HL. Application example: Exchange the data of data memory addresses 20H to 2FH and the data of addresses 30H to 3FH.

  • Page 173: Table Reference Instructions

    9.4.2 Table Reference Instructions MOVT XA, @PCXA Function: XA ROM (PC to PC Moves the high-order three bits (PC the table data in the program memory addressed by the contents of register pair XA to the A register and the high-order four bits to the X register.

  • Page 174: Arithmetic And Logic Instructions

    9.4.3 Arithmetic and Logic Instructions ADDS A, #n4 Function: A A + n4; Skip if carry; n4 = I Binary adds 4-bit immediate data n4 to the contents of the A register and skips the next instruction if a carry is generated.
  • Page 175 OR A, @HL Function: A (HL) ORs the contents of the A register and the data memory contents addressed by register pair HL and sets the result into the A register. XOR A, @HL Function: A (HL) Exclusive-ORs the contents of the A register and the data memory contents addressed by register pair HL and sets the result into the A register.

  • Page 176: Accumulator Operation Instructions

    9.4.4 Accumulator Operation Instructions RORC A Function: CY An to A An , A Rotates the contents of the A register (4-bit accumulator), including the carry flag, to the right one bit at a time. RORC A NOT A Function: A Takes the one’s complement (inverts each bit) of the A register (4-bit accumulator).

  • Page 177: Increment/Decrement Instructions

    9.4.5 Increment/Decrement Instructions INCS reg Function: reg reg + 1; Skip if reg = 0 Increments the contents of register reg (X, A, H, L). When the contents of register reg become 0 as the result of incrementing, skips the next instruction. INCS mem Functions: (mem) (mem) + 1;...

  • Page 178: Compare Instructions

    9.4.6 Compare Instructions SKE reg, #n4 Function: Skip if reg = n4; n4 = I to I If the contents of register reg (X, A, H, L) equal 4-bit immediate data n4, skips the next instruction. SKE A, @HL Function: Skip if A = (HL) If the contents of the A register and the data memory contents addressed by register pair HL, skips the next instruction.

  • Page 179: Carry Flag Operation Instructions

    9.4.7 Carry Flag Operation Instructions SET1 CY Function: CY Sets the carry flag. CLR1 CY Function: CY Clears the carry flag. SKT CY Function: Skip if CY = 1 When the carry flag is 1, skips the next instruction. NOT1 CY Function: CY Inverts the carry flag.

  • Page 180: Bit Manipulation Instructions

    9.4.8 Bit Manipuration Instructions SET1 mem. bit Function: (mem. bit) 1; mem = D Sets the bit specified by 2-bit immediate data bit of the address specified by 8-bit immediate data mem. SET1 fmem. bit Function: (bit specified by operand) Sets the data memory bit specified by bit manipulation addressing (fmem.
  • Page 181 SKF mem. bit Function: Skit if (mem. bit) = 0; mem = D If the bit specified by 2-bit immediate data bit of the address specified by 8-bit immediate data mem is 0, skips the next instruction. SKF fmem. bit Function: Skip if (bit specified by operand) = 0 If the contents of the data memory bit specified by bit manipulation addressing (fmem.

  • Page 182: Branch Instructions

    9.4.9 Branch Instructions BR addr Function: PC to PC addr; addr = 000H to 77FH Branches to the address addressed by 11-bit immediate data addr. This instruction is an assembler pseudo instruction. During assembly, the assembler automatically replaces this instruction with the optimum instruction from among the BRCB !caddr and BR $addr instructions. BR $addr Function: PC addr;...

  • Page 183: 9.4.10 Subroutine Stack Control Instructions

    9.4.10 Subroutine Stack Control Instructions CALLF !faddr Function: (SP-1) to PC , (SP-2) (SP-3) 0, 0, 0, 0 (SP-4) 0, PC to PC SP-4, PC to A faddr = A to A : 000H to 77FH Saves the contents of the program counter (PC; return address) to the data memory (stack) addressed by the stack pointer (SP) and decrements the SP, then branches to the address addressed by 11-bit immediate data faddr.
  • Page 184 PUSH rp Function: (SP-1) , (SP-2) Saves the contents of register pair rp (XA, HL) to the data memory (stack) addressed by the stack pointer (SP), then decrements the SP. The high-order side (rp : X, H) of the register pair is saved to the stack addressed by (SP-1) and the low- order side (rp : A, L) is saved to the stack addressed by (SP-2).

  • Page 185: 9.4.11 Interrupt Control Instructions

    9.4.11 Interrupt Control Instructions Function: IME Sets the interrupt master enable flag (1), and enables interrupts. Whether or not interrupts are accepted is determined by each interrupt enable flag. EI IEXXX Function: IE to N Sets the interrupt enable flag (IE Function: IME Resets the interrupt master enable flag and disables interrupts regardless of the contents of each interrupt enable flag.

  • Page 186: 9.4.12 Input/Output Instructions

    9.4.12 Input/Output Instructions IN A, PORTn Function: A PORTn; n = N to N Transfers the contents of the port specified by PORTn (n = 0 to 3, 5, 6) to the A register. Note Only 0 to 3, 5 or 6 can be specified at n. Output latch data (output mode) or pin data (input mode) is fetched according to input/output mode specification.

  • Page 187: 9.4.13 Cpu Control Instructions

    9.4.13 CPU Control Instructions HALT Function: PCC. 2 Sets the HALT mode (This instruction sets bit 2 of the processor clock control register.). Note The instruction following the HALT instruction is made an NOP instruction. STOP Function: PCC. 3 Sets the STOP mode (This instruction sets bit 3 of the processor clock control register). Note The instruction following the STOP instruction is made an NOP instruction.

  • Page 188: Appendix A. Table Of Instruction Usable With Evakit-75X Only

    Since EVAKIT-75X (75X series common evaluation board) supports the 75X series functions, it can execute the following instructions not available with the PD75402A. Since the PD75402A and PD75P402 cannot execute these instructions even though they can be executed on the EVAKIT, do not use them.
  • Page 189 APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY Mnemonic Operands DECS A, reg XA, rp’ XA, @HL @HL, #n4 A, mem SET1, CLR1, pmem. @L SKF, SKT, SKTCLR @H + mem. bit AND1, OR1 CY, pmem. @L CY, @H + mem. bit CY,/fmem.

  • Page 190: Appendix B. Development Tools

    APPENDIX B. DEVELOPMENT TOOLS APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the PD75402A: Language Processor RA75X relocatable assembler Host Machine PC-9800 series IBM PC/AT PROM Writing Tools PG-1500 This PROM programmer allows programming, in standalone a mode or via operation from a host computer, of a singlechip microcomputer with on-chip PROM by connection of the d board provided and a separately available programmer adapter.
  • Page 191 Operation of the IE control program is guaranteed only on the above quoted host machines and operating systems. Supply Medium MS-DOS 3.5-inch 2HD Ver. 3.30 Ver. 5.50 A*3 5-inch 2HD PC DOS 5-inch 2HC (Ver. 3.1) PD75402A program Ordering Code (Product Name) S5A13IE75X S5A10IE75X S7B10IE75X...
  • Page 192 In-Circuit Emulator IE-75000-R IE-75001-R Centronics I/F Control RS-232-C Program Host Machine PC-9800 Series IBM PC/AT (Symbolic Debugging PG-1500 Capability) Controller PROM Programmer Relocatable Assembler Programmer Adapter PA-75P402CT PA-75P402GB Development Tool Configuration Emulation Probe EP-75402C-R EP-75402GB-R IE-75000-R-EM On-chip PROM Products PD75P402C/CT/GB PG-1500 * 1.

  • Page 193: Appendix C. Mask Rom Ordering Procedure

    APPENDIX C. MASK ROM ORDERING PROCEDURE APPENDIX C. MASK ROM ORDERING PROCEDURE When completing the PD75402A program and ordering the mask ROM, proceed as follows: Mask ROM order reservation Provide us with the mask ROM ordering schedule through your dealer or our sales department (If we are not informed in advance, processing may be delayed.).

  • Page 194: Appendix D. Instruction Index (Alphabetic Order)

    APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER) Instruction ADDC A, @HL ADDS A, #n4 ADDS A, @HL A, @HL AND1 CY, fmem. bit addr $addr BRCB ! caddr CALLF ! faddr CLR1 CLR1 fmem. bit CLR1 mem. bit DECS HALT A, PORTn INCS INCS A, mem...

  • Page 195: Appendix E. Hardware Index (Alphabetic Order)

    APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER) APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER) Hardware Symbol Name ACKD Acknowledge detect flag ACKE Acknowledge enable flag ACKT Acknowledge trigger bit BSYE Sync busy enable bit Basic interval timer Basic interval timer mode register CLOM Clock output mode register CMDD...

This manual is also suitable for:

Pd75p402

Table of Contents