Pioneer TS7 Service Manual page 67

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CS4334-KS (MAIN ASSY(4/8) : IC4004)
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• DAC IC
¶ Block Diagram
LRCK
SDATA
¶ Pin Layout
SERIAL DATA INPUT
DE-EMPHASIS / SCLK
TE
L 13942296513
LEFT / RIGHT CLOCK
MASTER CLOCK
¶ Pin Function
No. Pin Name
1 SDATA
2 DEM/SCLK
3 LRCK
4 MCLK
5 AOUTR
6 AGND
7 VA
8 AOUTL
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DEM /SCLK
3
Serial Input
De-emphasis
Interface
1
∆Σ
Interpolator
Modulator
∆Σ
Interpolator
Modulator
MCLK
SDATA
DEM/SCLK
LRCK
MCLK
I/O
I Serial Audio Data Input - twoís complement MSB-first serial data is input on this pin.
The data is clocked into the CS4334/5/6/7/8/9 via internal or external SCLK, and the
channel is determined by LRCK.
De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or exter-
I
nal serial clock input.
Left/Right Clock - determines which channel is currently being input on the Audio Serial
I
Data Input pin, SDATA.
I Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and
either 128x or 192x the input sample rate in HRM.
O Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal.
I Analog Ground - analog ground reference is 0V.
I Analog Power - analog power supply is nominally +5V.
O Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal.
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8
AGND VA
2 6 7
Voltage Reference
DAC
DAC
4
1 8 AOUTL
2 7 VA
Q Q
3 6 7 1 3 1 5
3 6
AGND
4 5
AOUTR
Pin Function and Description
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3
9 4 2 8
Analog
AOUT L
Low-Pass
8
Filter
Analog
AOUT R
Low-Pass
5
Filter
ANALOG LEFT CHANNEL OUTPUT
ANALOG POWER
0 5 8 2 9 9 4
ANALOG GROUND
ANALOG RIGHT CHANNEL OUTPUT
m
3
4
9 9
A
B
C
2 8 9 9
D
E
F
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