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Epson S1R72104 Technical Manual

Epson S1R72104 Technical Manual

Scsi interface controller
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MF1529 - 01
SCSI Interface Controller
S1R72104
Technical Manual

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  • Page 1 MF1529 - 01 SCSI Interface Controller S1R72104 Technical Manual...
  • Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
  • Page 3 Configuration of product number DEVICES 72104 00B0 Packing specifications 00: Besides tape & reel 0A: TCP BL 2 directions 0B: Tape & reel Back 0C: TCP BR 2 directions 0D: TCP BT 2 directions 0E: TCP BD 2 directions 0F: Tape & reel FRONT 0G: TCP BT 4 directions 0H: TCP BD 4 directions 0J: TCP SL 2 directions...

  • Page 4: Table Of Contents

    7.3.22 CONFIG1 (CONFIG1) R/W ..................19 7.3.23 Test (TEST) R(/W) ....................20 7.3.24 Revision Reg. (REVISION) R ..................20 7.4 SCSI Control Commands ......................20 7.4.1 Control Commands and Command Codes ..............20 7.4.2 Description of Each Control Command................21 7.4.3 Command Execution and State Transition ..............28 Rev.1.1 EPSON...
  • Page 5 8. ELECTRICAL CHARACTERISTICS....................30 8.1 Absolute Maximum Ratings......................30 8.2 Recommended operational conditions..................30 8.3 DC Characteristics........................30 8.4 AC Characteristics........................33 8.4.1 CPU Interface.......................34 8.4.2 SCSI Interface ......................36 8.4.3 Port Interface ........................49 8.4.4 Others...........................53 9. EXAMPLES OF CONNECTION.......................56 10. EXTERNAL DIMENSIONS DRAWING ..................57 EPSON Rev.1.1...

  • Page 6: Description

    S1R72104 Technical Manual 1. DESCRIPTION S1R72104 is a SCSI interface control IC compatible with SCAM and FAST20 transfer. 2. FEATURES «CPU Interface» Connectable to a general-purpose CPU «SCSI Interface» Compatible with SCSI-2 (10Mbps (synchronous), 5Mbps (asynchronous)) Compatible with SCSI-3 FAST20 (20Mbps (synchronous)) Compatible with SCAM Lv.1 (compatible with Lv.2 with firmware)

  • Page 7: Block Diagram

    S1R72104 Technical Manual 3. BLOCK DIAGRAM SCSI-2(3) interface section Command Sequence XSRST analysis and control execution XSATN Port interface section XSBSY XPDREQ Master mode control Phase XSIO XPDACK control XSCD XPRD Slave mode control XSMSG XPWR XSSEL FIFO PD15-0 XSDB7-0...

  • Page 8: Pin Assignment

    S1R72104 Technical Manual 4. PIN ASSIGNMENT S1R72104F00B (QFP15-100pin) XSATN PD12 XSDBP PD13 XSDB7 EPSO EPSO EPSO EPSON PD14 XSDB6 PD15 XSDB5 PDREQ XPWR S1R72104 XSDB4 XPRD XPDACK XSDB3 XSDB2 XINT XRESET TOP View TOP View TOP View INDEX INDEX INDEX...

  • Page 9: Pin Description

    S1R72104 Technical Manual 5. PIN DESCRIPTION The control signal with “X” at the head of a pin name is LOW-active. Pin No. Symbol Functional description Remarks SCSI interface-related matters (18) XSDB0 Is/Otr SCSI data signal (SD0 to SD7) Drive capability 48mA...
  • Page 10 S1R72104 Technical Manual Pin No. Symbol Functional description Remarks CPU interface-related matters (17) Address input pin (AD0 to AD4) Ipu/O Data pin (DB0 to DB7) Drive capability 3mA Ispu Chip select signal for accessing internal register XINT Interrupt request output signal...

  • Page 11: Functional Description

    S1R72104 Technical Manual 6. FUNCTIONAL DESCRIPTION 6.1 CPU Interface Circuit This block can be interfaced to a general-purpose CPU. It controls the interface with the CPU generally. If XCS signal from CPU is LOW, the block can access the internal register. It decodes the address bus AD4 to AD0 to generate the address of the internal register.

  • Page 12: Pll Circuit (Internal System Clock Generating Section)

    S1R72104 Technical Manual 6.6 PLL Circuit (Internal System Clock Generating Section) This IC has the function to generate 40MHz required for the internal circuit from the clock generated by the oscillation circuit or inputted from EXCK pin by using PLL circuit.

  • Page 13: Function Of Registers

    S1R72104 Technical Manual 7. FUNCTION OF REGISTERS 7.1 List of Registers Address Register name Abridged name Main Interrupt Status MAININT SCSI Interrupt Status 1 SCSIINT1 SCSI Interrupt Status 2 SCSIINT2 - Reserved - - Reserved - - Reserved - - Reserved -...

  • Page 14: List Of Registers/Bits

    S1R72104 Technical Manual 7.2 List of Registers/Bits Address Type Register Name Default value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MAININT GOOD SABT EXEC SCSI1 SCSI2 DTCMP ASCMP SCSIINT1 SPERR IDERR SELTO SATN BFREE ILPHS SCSEL WOATN SCSIINT2 SRST...

  • Page 15: Detailed Description Of Each Register

    S1R72104 Technical Manual 7.3 Detailed Description of Each Register 7.3.1 Main Interrupt Status (MAININT) R/W When the IC interrupted CPU, the CPU first reads this register for processing the interruption to get to know which interrupt status register is the factor.

  • Page 16: Scsi Interrupt Status 1 (Scsiint1) R/W

    S1R72104 Technical Manual 7.3.2 SCSI Interrupt Status 1 (SCSIINT1) R/W Shows the result of a SCSI control command executed. The CPU can recognize the interrupt source by reading this register after receiving the interrupt signal. It clears the bit by writing again the value read.

  • Page 17: Scsi Interrupt Status 2 (Scsiint2) R/W

    S1R72104 Technical Manual 7.3.3 SCSI Interrupt Status 2 (SCSIINT2) R/W Shows the result of a SCSI control command executed. The CPU can recognize the interrupt source by reading this register after receiving the interrupt signal. It clears the bit by writing again the value read.

  • Page 18: Scsi Mode Select0 (Scsimode0) R/W

    S1R72104 Technical Manual 7.3.5 SCSI Mode Select0 (SCSIMODE0) R/W Makes the operational settings related to SCSI interface. SINTEN DTCD ULTRAS AUTO1 AUTO2 AN_C AN_D ACTIVE NEGATION DATA ACTIVE NEGATION CONTROL AUTO2 (status message stop) AUTO1 (auto status) ULTRA SCSI DTCMP DISABLE...

  • Page 19: Scsi Mode Select1 (Scsimode1) R/W

    S1R72104 Technical Manual 7.3.6 SCSI Mode Select1 (SCSIMODE1) R/W Makes the operational settings related to SCSI interface. STPPE ATNPE STATN AUTO RINH SINH DIRECT SPCEN SCSI PARITY CHECK ENABLE SCSI DIRECT ACCESS ENABLE SELECTION INHIBIT RESELECTION INHIBIT AUTO SEND STATUS/MESSAGE...

  • Page 20: Scsi Data (Scsidata) R/W

    S1R72104 Technical Manual 7.3.8 SCSI Data (SCSIDATA) R/W The CPU accesses this register when it controls SCSI data bus directly. For such direct control, DIRECT (bit 1) must be set in the mode setting register (0Ah). The status of each signal is stored as “active HIGH”. DIRECT setting does not decide whether parity bit is output or not;...

  • Page 21: Scsi Own Id (Ownid) R/W

    S1R72104 Technical Manual 7.3.10 SCSI Own ID (OWNID) R/W Sets the SCSI-ID of this IC itself. OID2 OID2 OID0 7.3.11 Source/Destination ID (SDID) R/W Sets both the SCSI-ID of the selector side and the target SCSI-ID when selection is made.

  • Page 22: Fifo Data (Fifodata) R/W

    S1R72104 Technical Manual 7.3.14 FIFO Data (FIFODATA) R/W This is a register to access SCSI-FIFO from CPU. 7.3.15 Non DMA Transfer Size (NDMASIZ) R/W Sets the bytes number of data transferred in Non-DMA mode (the message and command phases). In Read mode, the register allows to read out the size of data yet to be transferred.

  • Page 23: Dma Transfer Byte Count 0 (Dtbc0) R/W

    S1R72104 Technical Manual 7.3.20 DMA Transfer Byte Count 0 (DTBC0) R/W Sets the least significant byte of the byte-length (3 bytes) for DMA transfer. DBC7 DBC6 DBC5 DBC4 DBC3 DBC2 DBC1 DBC0 7.3.21 CONFIG0 (CONFIG0) R/W Sets the operation mode of the IC.

  • Page 24: Config1 (Config1) R/W

    S1R72104 Technical Manual * Operational settings of the port interface Shown below is a list of the operational settings made by the bit setting. 1) Switching master/slave of the port by PSLV bit PDREQ XPDACK XPRD/XPWR Remarks PSLV=0 Input Output...

  • Page 25: Test (Test) R(/W)

    S1R72104 Technical Manual 7.3.23 Test (TEST) R(/W) Used for testing a LSI. Basically, writing in this register is prohibited. CKOUTbit is valid, however, even when no test is done. If this bit is used, be sure to set all the other bits to “0”.

  • Page 26: Description Of Each Control Command

    S1R72104 Technical Manual 7.4.2 Description of Each Control Command Abort_SCSI(01H) Suspends a SCSI control command under execution. After suspension, this command sets SABT bit of MAININT register and the status block, causing interruption. This command, if issued in a non-operational condition, is ignored.
  • Page 27 S1R72104 Technical Manual Select_WithATN_Command(0AH) Asserts SCSI ATN signal, executes selection, and then executes the message-out command phase. This command is valid in either disconnected or connected condition. It causes a command error if issued when any other command is under execution.
  • Page 28 S1R72104 Technical Manual After the execution, the IC enters Initiator mode. Reselect(0DH) Executes the re-selection phase.. Valid only when it is not connected. If issued in the connected condition, it sets SCSIINT2 and CMDER bits, causing interruption. If any other command is under execution then, it continues execution.
  • Page 29 S1R72104 Technical Manual It causes interruption. CPU reads a command from FIFO In Initiator mode CPU issues this command after setting the command byte number in NON-DMA data-size register. Then it writes the command data in FIFO. The IC acts as follows: Negates XSACK if it is asserted at the start of execution.
  • Page 30 S1R72104 Technical Manual Non-DMA_Data_Out(14H) Executes the data-out phase between SCSI and CPU interface. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
  • Page 31 S1R72104 Technical Manual Non-DMA_Data_In(16H) Executes the data-in phase between SCSI and CPU interface. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
  • Page 32 S1R72104 Technical Manual Message_In (18H) Executes the message-in phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If it is issued in the disconnected condition, It sets SCSIINT2 and CMDER bits, causing interruption.

  • Page 33: Command Execution And State Transition

    S1R72104 Technical Manual Status_Message(1AH) Executes the message-in phase after executing the status phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.

  • Page 34: Others And Cautions About Operation

    S1R72104 Technical Manual 7.5 Others and Cautions about Operation Operation responding to the selection without SCSI-1 arbitration phase The IC operates responding to the selection of only a target ID of SCSI-1 as mentioned below. Note that there occurs no (automatic) transition to the message or command phase after selection, as in the usual cases after Wait_selection command.

  • Page 35: Electrical Characteristics

    S1R72104 Technical Manual 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings = 0[V] Item Symbol Ratings Unit Supply voltage -0.3 to +6.0 -0.3 to +4.6 Input voltage -0.3 to HV + 0.5 -0.3 to LV + 0.5 Output voltage -0.3 to HV + 0.5...
  • Page 36 S1R72104 Technical Manual (2) TTL input characteristics (Ta = 0 to70°C, V =0V) Names of signals covered: AD0 to 4,DB0 to 7, PD0 to 15, EXCLK, XSATN, XSBSY, XSRST, XSMSG, XSSEL, XSCD, XSIO Item Symbol Conditions Min. Typ. Max. Unit HIGH level =5.5V...
  • Page 37 S1R72104 Technical Manual (7) Output characteristics (Ta = 0 to 70°C, V = 0V) (I = 3mA) Names of signals covered: XPDACK, PD0 to 15, DB0 to 7, XPRD, XPWR Item Symbol Conditions Min. Typ. Max. Unit HIGH level =5.0V Output voltage =-1.5mA...

  • Page 38: Ac Characteristics

    S1R72104 Technical Manual 8.4 AC Characteristics Measurement conditions of AC characteristics: Ta = 0 to 70 HV = 5V±10% LV = 3.3V±0.3V = 0V DC level to decide input 0.8V to 2.4V Operating clock = 40MHz oscin Loading conditions of output pins except SCSI pins Drives load capacitance of 50pF and 1TTL.

  • Page 39: Cpu Interface

    S1R72104 Technical Manual 8.4.1 CPU Interface 8.4.1.1 Register Read Timing AD[4:0] DB[7:0] Symbol Specification Min. Typ. Max. Unit XCS fall → XRD fall AD[4:0] valid → XRD fall XRD rise → AD[4:0] invalid XRD rise → XCS rise XRD LOW level pulse width XRD HIGH level pulse width XRD fall →...
  • Page 40 S1R72104 Technical Manual 8.4.1.2 Register Write Timing AD[4:0] DB[7:0] Symbol Specification Min. Typ. Max. Unit XCS fall → XWR fall AD [4:0] valid → XWR fall XWR rise → AD [4:0] invalid XWR rise → XCS rise XWR LOW level pulse width XWR HIGH level pulse width DB [7:0] valid →...

  • Page 41: Scsi Interface

    S1R72104 Technical Manual 8.4.2 SCSI Interface 8.4.2.1 Selection Timing XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P XSATN XSIO Symbol Specification Min. Typ. Max. Unit XSBSY(IN) ↑ -XSBSY(OUT) ↓, 1600 OWNID valid XSBSY(OUT) ↓ -XSSEL ↓ 3000 XSSEL ↓ -SELID valid 1500 SELID valid -XSBSY(OUT) ↑...
  • Page 42 S1R72104 Technical Manual 8.4.2.2 Re-selection Timing XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P XSIO Symbol Specification Min. Typ. Max. Unit XSBSY(IN) ↑ -XSBSY(OUT) ↓, 1600 OWNID valid XSBSY(OUT) ↓ -XSSEL ↓ 3000 XSSEL ↓ -SELID valid, 1500 XSIO ↓ SELID valid -XSBSY(OUT) ↑...
  • Page 43 S1R72104 Technical Manual 8.4.2.3 Timing of Being Selected XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P Symbol Specification Min. Typ. Max. Unit SELID valid -XSBSY(IN) ↑ XSBSY(IN) ↑ XSBSY(OUT) ↓ XSBSY(OUT) ↓ XSSEL ↑ EPSON Rev.1.1...
  • Page 44 S1R72104 Technical Manual 8.4.2.4 Timing of Being Selected XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P XSIO Symbol Specification Min. Typ. Max. Unit SELID valid -XSBSY(IN) ↑ XSBSY(IN) ↑ XSBSY(OUT) ↓ XSBSY(OUT) ↑ XSSEL ↑ XSSEL ↓ -XSBSY(OUT) ↑ Rev.1.1 EPSON...
  • Page 45 S1R72104 Technical Manual 8.4.2.5 XSATN Output Timing XSATN XSREQ XSACK XSDB0-7,P LAST MESSAGE XSMSG XSIO XSCD Symbol Specification Min. Typ. Max. Unit XSREQ ↓ -XSATN ↑ XSATN ↑ -XSACK ↓ EPSON Rev.1.1...
  • Page 46 S1R72104 Technical Manual 8.4.2.6 Initiator Asynchronous Data-out Timing (Data output) XSDB0-7,P XSREQ XSACK Symbol Specification Min. Typ. Max. Unit XSREQ ↓ -XSACK ↓ XSDB valid –XSACK ↓ XSREQ ↑ -XSACK ↑ XSACK ↑ -XSDB invalid Rev.1.1 EPSON...
  • Page 47 S1R72104 Technical Manual 8.4.2.7 Initiator Asynchronous Data-in Timing (Data input) XSDB0-7,P XSREQ XSACK Symbol Specification Min. Typ. Max. Unit XSDB valid -XSREQ ↓ XSREQ ↓ -XSACK ↓ XSACK ↓ -XSDB invalid XSREQ ↑ -XSACK ↑ EPSON Rev.1.1...
  • Page 48 S1R72104 Technical Manual 8.4.2.8 Initiator Synchronous Data-out Timing (Data output) XSDB0-7,P XSACK Symbol Specification Min. Typ. Max. Unit XSDB valid -XSACK ↓ XSACK ↓ -XSDB invalid XSACK ↓ -XSACK ↑ XSACK ↑ - (NEXT) XSACK ↓ Note: Value of when RATE3 to 0bit is “0000”...
  • Page 49 S1R72104 Technical Manual 8.4.2.9 Initiator Synchronous Data-in Timing (Data input) XSDB0-7,P XSREQ Symbol Specification Min. Typ. Max. Unit XSDB0-7, P valid –XSREQ ↓ XSREQ ↓ -XSDB0-7, P invalid XSREQ ↓ -XSREQ ↑ XSREQ ↑ -XSREQ ↓ EPSON Rev.1.1...
  • Page 50 S1R72104 Technical Manual 8.4.2.10 Target Asynchronous Data-in Timing (Data output) XSDB0-7,P XSREQ 242a XSACK 242b Symbol Specification Min. Typ. Max. Unit XSDB valid -XSREQ ↓ XSACK ↑ -XSREQ ↑ XSREQ ↑ -XSDB invalid XSACK ↑ - (NEXT) XSREQ ↓ 242a XSREQ ↑...
  • Page 51 S1R72104 Technical Manual 8.4.2.11 Target Asynchronous Data-out Timing (Data input) XSDB0-7,P XSREQ 246a XSACK 246b Symbol Specification Min. Typ. Max. Unit XSDB valid -XSACK ↓ XSACK ↓ -XSREQ ↑ XSREQ ↑ -XSDB invalid XSACK ↑ -XSREQ ↓ 246a XSREQ ↑ -XSREQ ↓...
  • Page 52 S1R72104 Technical Manual 8.4.2.12 Target Synchronous Data-in Timing (Data output) XSDB0-7,P XSREQ Symbol Specification Min. Typ. Max. Unit XSDB valid –XSREQ ↓ XSREQ ↓ -XSDB invalid XSREQ ↓-XSREQ ↑ XSREQ ↑ -XSREQ ↓ Note: Value of when RATE3 to 0bit is “0000”...
  • Page 53 S1R72104 Technical Manual 8.4.2.13 Target Synchronous Data-out Timing (Data input) XSDB0-7,P XSACK Symbol Specification Min. Typ. Max. Unit XSDB valid -XSACK ↓ XSACK ↓ -XSDB invalid XSACK ↓-XSACK ↑ XSACK ↑ -XSACK ↓ EPSON Rev.1.1...

  • Page 54: Port Interface

    S1R72104 Technical Manual 8.4.3 Port Interface 8.4.3.1 DMA Read (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72104 HOST PDREQ(0) (PRQLV=1) XPDACK(I) XPRD(I) PD15-0(0) XPWR(I) Symbol Specification Min. Typ. Max. Unit XPWR → XPDACK ↓ XPDACK setup time XPDACK ↑ → XPWR XPDACK hold time XPRD ↓...
  • Page 55 S1R72104 Technical Manual 8.4.3.2 DMA Write (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72104 HOST PDREQ(0) (PRQLV=1) XPDACK(I) XPWR(I) PD15-0(I) XPRD(I) Symbol Specification Min. Typ. Max. Unit XPRD → XPDACK ↓ XPDACK setup time XPDACK ↑ → XPRD XPDACK hold time XPWR ↓...
  • Page 56 S1R72104 Technical Manual 8.4.3.3 DMA Write (PSLV=0: Master mode) Prosessor S1R72104 HOST Direction of data transfer PDREQ(I) XPDACK(0) XPWR(0) PD15-0(0) Symbol Specification Min. Typ. Max. Unit XPWR ↓ → PDREQ negate PDREQ negate delay time XPDACK ↓ → XPWR ↓...
  • Page 57 S1R72104 Technical Manual 8.4.3.4 DMA Read (PSLV=0: Master mode) Prosessor Direction of data transfer S1R72104 HOST PDREQ(I) XPDACK(0) XPRD(0) PD15-0(I) Symbol Specification Min. Typ. Max. Unit XPRD ↓ → PDREQ negate PDREQ negate delay time XPDACK ↓ → XPRD ↓...

  • Page 58: Others

    S1R72104 Technical Manual 8.4.4 Others 8.4.4.1 OSCIN Input Clock (ex.40MHz) Note: Maximum input voltage: LV 1.9V 0.9V Symbol Specification Min. Typ. Max. Unit CLK cycle *1 (1/f) CLK HIGH width *1 (1/f)×0.4 (1/f)×0.6 CLK LOW width *1 (1/f)×0.4 (1/f)×0.6 CLK rise time...
  • Page 59 S1R72104 Technical Manual 8.4.4.2 EXCLK Input Clock (ex.40MHz) Note: Maximum input voltage: HV 1.9V 0.9V Symbol Specification Min. Typ. Max. Unit CLK cycle *1 (1/f) CLK HIGH width *1 (1/f)×0.4 (1/f)×0.6 CLK LOW width *1 (1/f)×0.4 (1/f)×0.6 CLK rise time...
  • Page 60 S1R72104 Technical Manual 8.4.4.3 XRESET Input Pulse Width XRESET Symbol Specification Min. Typ. Max. Unit XRESET LOW width 8.4.4.4 TESTMON (CLKOUT = HIGH) Output Pulse * When PLL is operated (When PLL is not used, the waveform inputted is output to CLKINorEXCLK pin.)

  • Page 61: Examples Of Connection

    S1R72104 Technical Manual 9. EXAMPLES OF CONNECTION (When 20MHz OSC oscillation is used) S1R72104 ∗CPU Interface (5V type) AD [4:0] AD [4:0] DB [7:0] DB [7:0] XINT XINT ∗PORT Interface (5V type) PD [15:0] PD [15:0] PDREQ PDREQ ∗SCSI Interface...

  • Page 62: External Dimensions Drawing

    S1R72104 Technical Manual 10. EXTERNAL DIMENSIONS DRAWING Plastic QFP15-100 pin ±0.4 ±0.1 INDEX +0.1 0.18 -0.05 +0.05 0.125 -0.025 0° 10° ±0.2 Unit : mm Rev.1.1 EPSON...
  • Page 63 FAX: +852-2827-4346 Crystal Lake, IL 60014, U.S.A. Telex: 65542 EPSCO HX Phone: +1-815-455-7630 FAX: +1-815-455-7633 EPSON TAIWAN TECHNOLOGY & TRADING LTD. Northeast 10F, No. 287, Nanking East Road, Sec. 3 301 Edgewater Place, Suite 120 Taipei Wakefield, MA 01880, U.S.A.
  • Page 64 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
  • Page 65 S1R72104 Technical Manual SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com/ First issue October, 2002 Printed in Japan...

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