Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 2 Page ii Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 3 Page iii Vancouver Design Center CUSTOMER SUPPORT INFORMATION Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board •...
Page 4 Page iv Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 5 Epson Research and Development Page v Vancouver Design Center TABLE OF CONTENTS INTRODUCTION S1D13503 Graphics LCD Controller Data Sheet SPECIFICATION S1D13503 Hardware Functional Specification PROGRAMMER’S REFERENCE S1D13503 Programming Notes and Examples UTILITIES 13503SHOW.EXE Display Utility 13503VIRT.EXE Display Utility 13503BIOS.COM Display Utility 13503MODE.EXE Display Utility...
Page 6 Page vi Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 7 S1D13503 GRAPHICS LCD CONTROLLER DESCRIPTION The S1D13503 is a dot matrix graphic LCD controller supporting resolutions up to 1024x1024. It is capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades. Design flexibility allows the S1D13503 to interface to either an MC68000 family microprocessor or an 8/16-bit MPU/bus with minimum external logic.
Page 8 Copyright ©1997, 2001 Epson Research and Development, Inc. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/ EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
Page 9 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 10 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Hardware Functional Specification X18A-A-001-08 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 11: Table Of Contents
Epson Research and Development Page 3 Vancouver Design Center Table of Contents INTRODUCTION ........9 Scope .
Page 12 Page 4 Epson Research and Development Vancouver Design Center Display Memory Interface Timing ......39 7.3.1 Write Data to Display Memory ....... . 39 7.3.2 Read Data From Display Memory .
Page 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 4-1: PAD Coordinates ..........20 Table 5-1: Bus Interface .
Page 14 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Hardware Functional Specification X18A-A-001-08 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 15 S1D13503 Pinout Diagram ........
Page 16 16-Bit Mode - 128K bytes SRAM ........82 Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503) ......87 Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503).
Page 17: Introduction
13502). The S1D13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous colors. In gray shade modes, a 16x4 Look-Up Table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel.
Page 18: Features
Page 10 Epson Research and Development Vancouver Design Center 2 FEATURES 2.1 Technology • low power CMOS • 2.7 to 5.5 volt operation • 100 pin QFP5-S2 surface mount package • 100 pin QFP15-STD surface mount package 2.2 System •...
Page 19: Display Support
Epson Research and Development Page 11 Vancouver Design Center 2.4 Display Support • example resolutions: • 1024 x 768 black-and-white • 640 x 480 with 4 colors/grays • 640 x 400 with 16 colors/grays • 320 x 240 with 256 colors •...
Page 20: Typical System Block Diagrams
Vancouver Design Center 3 TYPICAL SYSTEM BLOCK DIAGRAMS The following figures show typical system implementations of the S1D13503. All of the following block diagrams are shown without SRAM or LCD display. Refer to the interface specific Application Notes for complete details.
Page 21: Mpu With Ready (Or Wait#) Signal
Epson Research and Development Page 13 Vancouver Design Center 3.2 MPU with READY (or WAIT#) signal Decoder S1D13503 MEMCS# MREQ# A10 to A15 Decoder IOCS# IORQ# AB0 to AB15 A0 to A15 D0 to D7 DB0 to DB7 WAIT# READY...
Page 22: Isa Bus
Page 14 Epson Research and Development Vancouver Design Center 3.3 ISA Bus 8-Bit ISA Bus S1D13503 REFRESH SA16 to SA13 MEMCS# Decoder MEMW# SMEMW# MEMR# SMEMR# READY IOCHRDY DB0 to DB7 SD0 to SD7 AB0 to AB19 SA0 to SA19...
Page 23: Internal Block Diagram
Epson Research and Development Page 15 Vancouver Design Center 3.4 Internal Block Diagram Control Registers IOR#, IOW#, IOCS#, MEMCS#, MEMR#, MEMW#, BHE#, AB[19:0] Port Signal Decoder Sequence LCDENB Controller Translation UD[3:0] Memory Lookup Decoder Table LD[3:0] Panel READY LP, YD,...
Page 24: Look-Up Table
Page 16 Epson Research and Development Vancouver Design Center 3.5.5 Look-Up Table The Look-Up Table contains three 16x4-bit wide palettes. In gray shade modes, the “green” palette can be configured for the re-mapping of 16 possible shades of gray. In color modes, all three palettes can be configured for the re-mapping of 4096 possible colors.
Page 25: Pinout Diagram
Epson Research and Development Page 17 Vancouver Design Center 4 PINOUT DIAGRAM XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# VA10 MEMW# MEMR# S1D13503F00A READY BHE# OSC1 OSC2 RESET AB19 Figure 7: S1D13503F00A Pinout Diagram Package type: 100 pin surface mount QFP5-S2.
Page 26: Figure 8: S1D13503 Pinout Diagram
Page 18 Epson Research and Development Vancouver Design Center WF/XSCL2* XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# VA10 READY S1D13503F01A BHE# OSC1 OSC2 RESET AB19 AB18 AB17 Figure 8: S1D13503F01A Pinout Diagram Package type: 100 pin surface mount QFP15-STD.
Page 27: Figure 9: S1D13503 Pad Diagram
Epson Research and Development Page 19 Vancouver Design Center Dummy Pad WF/XSCL2* XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# VA10 MEMR# S1D13503D00A READY BHE# OSC1 OSC2 RESET AB19 Dummy Pad Chip Size 5.030 mm x 5.030 mm Chip Thickness 0.400 mm...
Page 28: Table 4-1: Pad Coordinates
Page 20 Epson Research and Development Vancouver Design Center Table 4-1: PAD Coordinates Pad Center Pad Center Coordinate Coordinate Name Name -2.165 -2.390 RESET 2.390 -1.535 -2.000 -2.390 2.390 -1.388 -1.840 -2.390 2.390 -1.246 -1.685 -2.390 2.390 -1.106 -1.535 -2.390 2.390...
Page 29 Epson Research and Development Page 21 Vancouver Design Center Table 4-1: PAD Coordinates Pad Center Pad Center Coordinate Coordinate Name Name VD13 0.969 2.390 VOE# -2.390 1.388 VD14 0.835 2.390 IOCS# -2.390 1.246 VD15 0.703 2.390 IOW# -2.390 1.106 0.573 2.390...
Page 30: Table 5-1: Bus Interface
Page 22 Epson Research and Development Vancouver Design Center 5 PIN DESCRIPTION 5.1 Description Key: Input Output Bidirectional (Input/Output) Power pin CMOS level output driver, x denotes driver type (see Table 6-4, “Output Specifications,” on page 28) COxS CMOS level output driver with slew rate control for noise reduction, x denotes driver type (see Table 6-4, “Output Specifications,”...
Page 31: Pin Description
Epson Research and Development Page 23 Vancouver Design Center Table 5-1: Bus Interface F00A F01A D00A Pin Name Type Driver Description Pin # Pin # Pad # In MC68000 MPU interface, this pin is connected to the R/W# pin of MC68000. This input pin defines whether the data...
Page 32: Description
Page 24 Epson Research and Development Vancouver Design Center Table 5-2: Display Memory Interface F00A F01A D00A Type Driver Description Name Pin # Pin # Pad # These pins are connected to the display memory data bus. For 16- bit interface, VD0-VD7 are connected to the display memory data bus of even byte addresses and VD8-VD15 are connected to the display memory data bus of odd byte addresses.
Page 33: Table 5-3: Lcd Interface
Epson Research and Development Page 25 Vancouver Design Center Table 5-3: LCD Interface F00A F01A D00A FPDI-1 Pin Name Type Driver Description Pin Name Pin # Pin # Pad # Panel display data bus. The data format depends on the...
Page 34: Table 5-6: Summary Of Power On / Reset Options
5.2 Summary of Configuration Options The S1D13503 requires some configuration information on power-up. This information is provided through the SRAM data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to configure the following...
Page 35: Table 6-1: Absolute Maximum Ratings
Epson Research and Development Page 27 Vancouver Design Center 6 D.C. CHARACTERISTICS Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units -0.3 to + 6.0 Supply Voltage -0.3 to V + 0.5 Input Voltage -0.3 to V + 0.5 Output Voltage °...
Page 36: Table 6-4: Output Specifications
Page 28 Epson Research and Development Vancouver Design Center Table 6-3: Input Specifications (Continued) Symbol Parameter Condition Units f =1 MHz, Input Pin Capacitance = 0V = 5.0V kΩ Pull Down Resistance = 3.3V kΩ Pull Down Resistance = 3.0V kΩ...
Page 37: Table 7-1: Iow# Timing (Mc68000)
Epson Research and Development Page 29 Vancouver Design Center 7 A.C. CHARACTERISTICS = -40 °C to 85 °C Conditions : V = 3.0V ± 10%, V = 3.3V ± 10%, or V = 5.0V ± 10% T and T for all inputs must be < 5 nsec (10% ~ 90%)
Page 38: Table 7-2: Ior# Timing (Mc68000)
Page 30 Epson Research and Development Vancouver Design Center IOR# Timing AB[9:1] VALID IOCS# UDS#/LDS# INVALID R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 11: IOR# Timing (MC68000) Table 7-2: IOR# Timing (MC68000) 3V/3.3V Symbol Parameter Min Max Min Max...
Page 39: Table 7-3: Memw# Timing (Mc68000)
Epson Research and Development Page 31 Vancouver Design Center MEMW# Timing AB[19:1] VALID MEMCS# UDS#/LDS# INVALID R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 12: MEMW# Timing (MC68000) Table 7-3: MEMW# Timing (MC68000) 3V/3.3V Symbol Parameter Units AB[19:1] and MEMCS# valid before AS# falling edge AB[19:1] and MEMCS# hold from AS# rising edge 3.5 *...
Page 40: Table 7-4: Memr# Timing (Mc68000)
Page 32 Epson Research and Development Vancouver Design Center MEMR# Timing AB[19:1] VALID MEMCS# UDS#/LDS# INVALID R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 13: MEMR# Timing (MC68000) Table 7-4: MEMR# Timing (MC68000) 3V/3.3V Symbol Parameter Units AB[19:1] and MEMCS# valid before AS# falling edge AB[19:1] and MEMCS# hold from AS# rising edge 3.5 *...
Page 41: Non-Mc68000, Mpu/Bus With Ready (Or Wait#) Signal
Epson Research and Development Page 33 Vancouver Design Center 7.1.2 Non-MC68000, MPU/Bus With READY (or WAIT#) Signal IOW# Timing AB[9:0] VALID BHE# IOCS# IOW# Hi-Z Hi-Z DB[15:0] VALID Figure 14: IOW# Timing (Non-MC68000) Table 7-5: IOW# Timing (Non-MC68000) 3V/3.3V Symbol...
Page 42: Table 7-6: Ior# Timing (Non-Mc68000)
Page 34 Epson Research and Development Vancouver Design Center IOR# Timing AB[9:0] VALID BHE# IOCS# IOR# Hi-Z Hi-Z DB[15:0] VALID Figure 15: IOR# Timing (Non-MC68000) Table 7-6: IOR# Timing (Non-MC68000) 3V/3.3V Symbol Parameter Min Max Min Max Units AB[9:0], BHE# and IOCS# valid before IOR# falling...
Page 43: Table 7-7: Memw# Timing (Non-Mc68000)
Epson Research and Development Page 35 Vancouver Design Center MEMW# Timing AB[19:0] VALID BHE# MEMCS# MEMW# Hi-Z Hi-Z READY Hi-Z Hi-Z DB[15:0] VALID Figure 16: MEMW# Timing (Non-MC68000) Table 7-7: MEMW# Timing (Non-MC68000) 3V/3.3V Symbol Parameter Units AB[19:0], BHE# and MEMCS# valid before MEMW#...
Page 44: Table 7-8: Memr# Timing (Non-Mc68000)
Page 36 Epson Research and Development Vancouver Design Center MEMR# Timing AB[19:0] VALID BHE# MEMCS# MEMR# Hi-Z Hi-Z READY Hi-Z Hi-Z DB[15:0] VALID Figure 17: MEMR# Timing (Non-MC68000) Table 7-8: MEMR# Timing (Non-MC68000) 3V/3.3V Symbol Parameter Units AB[19:0], BHE# and MEMCS# valid before MEMR#...
Page 45: Clock Input Requirements
Epson Research and Development Page 37 Vancouver Design Center 7.2 Clock Input Requirements Clock Input Waveform Figure 18: Clock Input Requirements Table 7-9: Clock Input Requirements Symbol Parameter Units Input Clock Period (CLKI) Input Clock Pulse Width High (CLKI) Input Clock Pulse Width Low (CLKI)
Page 46: Recommended Clock Input
The crystal oscillator must be “fundamental mode” and have the following recommended RC load values: = 2MΩ ± 5% = 6.8 pF The figure below demonstrates both a crystal interface and an oscillator interface to the S1D13503. Crystal Interface Oscillator Interface...
Page 47: Display Memory Interface Timing
Epson Research and Development Page 39 Vancouver Design Center 7.3 Display Memory Interface Timing 7.3.1 Write Data to Display Memory VA[15:0] VALID VCS0#, VCS1# VWE# VOE# Hi-Z Hi-Z Hi-Z Hi-Z VD[15:0] INPUT OUTPUT INPUT Figure 20: Write Data to Display Memory Table 7-10: Write Data to Display Memory 3V/3.3V...
Page 48: Read Data From Display Memory
Page 40 Epson Research and Development Vancouver Design Center 7.3.2 Read Data From Display Memory VA[15:0] VALID VCS0#, VCS1# INPUT INPUT VD[15:0] INPUT Figure 21: Read Data From Display Memory Table 7-11: Read Data From Display Memory 3V/3.3V Symbol Parameter...
Page 49: Lcd Interface
Epson Research and Development Page 41 Vancouver Design Center 7.4 LCD Interface 7.4.1 LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels S1D13503 outputs S1D13503 outputs (AUX[01] bit 5 = 0) XSCL UD[3:0] LD[3:0] S1D13503 outputs (AUX[01] bit 5 = 1)
Page 50: Table 7-12: Lcd Interface Timing - 4-Bit Single And 8-Bit Single/Dual Monochrome Panel
Page 42 Epson Research and Development Vancouver Design Center Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel 4-Bit Single 8-Bit Single/Dual Symbol Parameter Max Units HT + HNDP - HT + HNDP - LP period (single panel mode)
Page 51 Epson Research and Development Page 43 Vancouver Design Center Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel UD[3:0], LD[3:0] setup to XSCL falling edge (AUX[03] bit 2 - 10** - 10** = 1) UD[3:0], LD[3:0] hold from XSCL falling edge (AUX[03] bit...
Page 52: Lcd Interface Timing - 4-Bit Single Color Panel
Page 44 Epson Research and Development Vancouver Design Center 7.4.2 LCD Interface Timing - 4-Bit Single Color Panel XSCL Figure 23: LCD Interface Timing - 4-Bit Single Color Panel S1D13503 Hardware Functional Specification X18A-A-001-08 Issue Date: 01/01/29 Downloaded from Elcodis.com...
Page 53: Table 7-13: Lcd Interface Timing - 4-Bit Single Color Panel
Epson Research and Development Page 45 Vancouver Design Center Table 7-13: LCD Interface Timing - 4-Bit Single Color Panel Symbol Parameter Units HT + HNDP - 10 LP period - 10 YD hold from LP falling edge LP pulse width...
Page 54: Lcd Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
Page 46 Epson Research and Development Vancouver Design Center 7.4.3 LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels XSCL UD/LD Figure 24: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels...
Page 55: Table 7-14: Lcd Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
Epson Research and Development Page 47 Vancouver Design Center Table 7-14: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels Symbol Parameter Units HT + HNDP - 10 LP period (single panel mode) 2(HT + HNDP) - 10...
Page 56: Lcd Interface Timing - 16-Bit Single/Dual Color Panels
Page 48 Epson Research and Development Vancouver Design Center 7.4.4 LCD Interface Timing - 16-Bit Single/Dual Color Panels XSCL UD/LD Figure 25: LCD Interface Timing - 16-Bit Single/Dual Color Panels S1D13503 Hardware Functional Specification X18A-A-001-08 Issue Date: 01/01/29 Downloaded from Elcodis.com...
Page 57: Table 7-15: Lcd Interface Timing - 16-Bit Single/Dual Color Panels
Epson Research and Development Page 49 Vancouver Design Center Table 7-15: LCD Interface Timing - 16-Bit Single/Dual Color Panels Symbol Parameter Units HT + HNDP - 10 LP period (single panel mode) 2(HT + HNDP) - 10 LP period (dual panel mode)
Page 58: Lcd Interface Timing - 8-Bit Single Color Panels Format 1
Page 50 Epson Research and Development Vancouver Design Center 7.4.5 LCD Interface Timing - 8-Bit Single Color Panels Format 1 t14b t11b t10b XSCL2 (WF) t11a t10a t14a XSCL t12b t12a t13a t13b UD/LD Figure 26: LCD Interface Timing - 8-Bit Single Color Panels Format 1...
Page 59: Table 7-16: Lcd Interface Timing - 8-Bit Single Color Panels Format 1
Epson Research and Development Page 51 Vancouver Design Center Table 7-16: LCD Interface Timing - 8-Bit Single Color Panels Format 1 Symbol Parameter Units HT + HNDP - 10 LP period - 10 YD hold from LP falling edge LP pulse width LP setup to XSCL falling edge 19.5t...
Page 60: Lcd Interface Options
Page 52 Epson Research and Development Vancouver Design Center 7.4.6 LCD Interface Options LP : 240 PULSES LP: 4 PULSES UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 XSCL: 80 CLOCK PERIODS XSCL 1-317 1-318 1-319 1-320 Example Timing for a 320x240 single panel...
Page 61: Figure 28: 8-Bit Single Monochrome Panel Timing
Epson Research and Development Page 53 Vancouver Design Center LP: 4 PULSES LP : 480 PULSES UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 XSCL:80 CLOCK PERIODS XSCL 1-633 1-10 1-634 1-635 1-11 1-12 1-636 1-13 1-637 1-14...
Page 62: Figure 29: 8-Bit Dual Monochrome Panel Timing
Page 54 Epson Research and Development Vancouver Design Center LP: 2 PULSES LP : 240 PULSES UD[3:0], LD[3:0] LINE1/241 LINE2/242 LINE3/243 LINE4/244 LINE 239/479 LINE240/480 LINE1/241 LINE2/242 XSCL: 160 CLOCK PERIODS XSCL 1-637 1-638 1-639 1-640 241-1 241-5 241-637 241-2...
Page 63: Figure 30: 4-Bit Single Color Panel Timing
Epson Research and Development Page 55 Vancouver Design Center LP: 4 PULSES LP : 240 PULSES UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 XSCL: 240 CLOCK PERIODS XSCL 1-B319 1-R1 1-G2 1-B3 1-G1 1-B2 1-R4 1-R320 1-G320 1-B1...
Page 64: Figure 31: 8-Bit Single Color Panel Timing - Format 1
Page 56 Epson Research and Development Vancouver Design Center LP: 480 PULSES LP: 4 PULSES UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 LD[3:0] XSCL2: 120 CLOCK PERIODS XSCL2 XSCL: 120 CLOCK PERIODS XSCL 1-R1 1-G1 1-G6 1-B6 1-B11...
Page 65: Figure 32: 8-Bit Single Color Panel Timing - Format 2
Epson Research and Development Page 57 Vancouver Design Center LP: 4 PULSES LP : 240 PULSES UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 LD[3:0] XSCL: 120 CLOCK PERIODS XSCL 1-G318 1-R1 1-B3 1-G6 1-G1 1-R4 1-B318 1-B6 1-R319...
Page 66: Figure 33: 8-Bit Dual Color Panel Timing
Page 58 Epson Research and Development Vancouver Design Center LP: 2 PULSES LP: 240 PULSES UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 LINE241 LINE242 LINE243 LINE244 LINE479 LINE480 LINE241 LINE242 LD[3:0] XSCL: 480 CLOCK PERIODS XSCL 1-R1 1-G2...
Page 67: Figure 35: 16-Bit Single Color Panel Timing With External Circuit
Epson Research and Development Page 59 Vancouver Design Center LP : 480 PULSES LP: 4 PULSES Pixel Data LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 XSCL: 120 CLOCKS XSCL 1-R1 1-B3 1-B635 1-G638 1-B1 1-G4 1-G636 1-R639 1-R5 1-G2...
Page 68: Figure 36: 16-Bit Dual Color Panel Timing With External Circuit
Page 60 Epson Research and Development Vancouver Design Center LP: 2 PULSES LP : 240 PULSES Pixel Data LINE1/241 LINE2/242 LINE3/243 LINE4/244 LINE239/479 LINE240/480 LINE1/241 LINE2/242 XSCL: 240 CLOCKS XSCL 1-R1 1-G2 1-B3 1-G638 1-B639 1-G1 1-B2 1-R4 1-B638 1-R640...
Page 69: Hardware Register Interface
Vancouver Design Center 8 HARDWARE REGISTER INTERFACE The S1D13503 is configured and controlled via 16 internal 8-bit registers. There are two ways to map these registers into the system I/O space. Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped address...
Page 70: Table 8-1: Gray Shade/Color Mode Selection
Page 62 Epson Research and Development Vancouver Design Center AUX[01] Mode Register 0 I/O address = 0001b, Read/Write. Mask Gray Shade / LCD Data Memory DISP Panel LCDE RAMS XSCL Color Width Bit 0 Interface bit 7 DISP This bit selects display on or off. When this bit = 0, Display OFF is selected (LD0-3 and UD0-3 are forced to 0 ).
Page 71: Table 8-2: Lcd Data Width
Epson Research and Development Page 63 Vancouver Design Center bit 2 LCD Data Width Bit 0 Together with LCD Data Width bit 1 (AUX[03] bit 3) this bit selects different display data formats. The following table shows the function of these two bits:...
Page 72: Table 8-3: Maximum Value Of Line Byte Count Register - 8-Bit Display Memory Interface
Page 64 Epson Research and Development Vancouver Design Center The following two tables summarize the maximum value of the Line Byte Count Register for different display modes and display memory interface. Table 8-3: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface...
Page 73 Epson Research and Development Page 65 Vancouver Design Center bit 3 LCD Data Width Bit 1 Together with LCD Data Width bit 0 (AUX[01] bit 2), this bit selects different display data formats. See Table 8-2, “LCD Data Width,” on page 63 for details. This bit goes low on RESET.
Page 74 Page 66 Epson Research and Development Vancouver Design Center AUX[05] Total Display Line Count (MSB) and WF Count Register I/O address = 0101b, Read/Write Total Disp. Total Disp. WF Count WF Count WF Count WF Count WF Count WF Count...
Page 75 Epson Research and Development Page 67 Vancouver Design Center AUX[08] Screen 2 Display Start Address Register (LSB) I/O address = 1000b, Read/Write. Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display...
Page 76 Page 68 Epson Research and Development Vancouver Design Center AUX[0A] Screen 1 Display Line Count Register (LSB) I/O address = 1010b, Read/Write. Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Display...
Page 77 Epson Research and Development Page 69 Vancouver Design Center AUX[0C] Horizontal Non-Display Period I/O address = 1100b, Read/Write. Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Non- Non- Non- Non- Non- Non- Non- Non- Display Display Display Display Display Display...
Page 78: Table 8-6: Id Bit Usage
These bits have dual purpose; ID Bits: After power on or hardware reset, these bits can be read to identify the S1D13503. These same bits are used to identify the pin compatible S1D13502 and would only be used in system implementations where common software is being used.
Page 79 Epson Research and Development Page 71 Vancouver Design Center Note When auto-increment is selected, an internal pointer will default to the Red palette on power on reset. Each read/write access to Aux[0F] will increment the counter to point to the next palette in order (RGB). Whenever the Look-Up Table Address register Aux[0E] is written, the RGB Index will reset the pointer to the Red palette.
Page 80: Look-Up Table Architecture
Page 72 Epson Research and Development Vancouver Design Center 8.2 Look-Up Table Architecture Table 8-8: Look-Up Table Configurations Display Mode 4-bit wide Palette GREEN BLUE Black & White 4-level gray 4 banks of 4 16-level gray 1 bank of 16...
Page 81: Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture
Epson Research and Development Page 73 Vancouver Design Center 16-Level Gray Shade Mode Green Look-Up Table 16x4 4-bit pixel data 4-bit Look-Up Table data output ( P3, P2, P1, P0 ) Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture Note...
Page 82: Color Display Modes
Page 74 Epson Research and Development Vancouver Design Center 8.2.2 Color Display Modes 4-Level Color Mode RED Look-Up Table Bank 0 2-bit pixel data Bank 1 4-bit ‘RED’ Bank display data output Select Bank 2 Logic Bank 3 Red Bank Select bits [1:0]...
Page 83: Figure 40: 16-Level Color Mode Look-Up Table Architecture
Epson Research and Development Page 75 Vancouver Design Center 16-Level Color Mode Red Look-Up Table 16x4 4-bit pixel data 4-bit ‘RED’ Look-Up Table data output Green Look-Up Table 16x4 4-bit ‘GREEN’ Look-Up Table data output Blue Look-Up Table 16x4 4-bit ‘BLUE’ Look-Up Table data output...
Page 84: Figure 41: 256-Level Color Mode Look-Up Table Architecture
Page 76 Epson Research and Development Vancouver Design Center 256-Level Color Mode 256 Color Data Format: Red Look-Up Table 7 6 5 4 3 2 1 0 Bank 0 3-bit pixel data (R2, R1, R0) 4-bit ‘RED’ Bank display data output...
Page 85: Power Save Modes
8.3.1 Power Save Mode 1 Power Save Mode 1 has two states. Initially when set, the S1D13503 enters State 1. If no valid memory cycle is detected within 1, 2, or 4 clocks (input clock frequency dependent), the chip will enter State 2. The number of clocks of inactivity before entering State 2 is dependent on the display memory interface and the number of Gray shades.
Page 86: Power Save Mode Function Summary
Page 78 Epson Research and Development Vancouver Design Center 8.3.3 Power Save Mode Function Summary Table 8-10: Power Save Mode Function Summary Power Save Mode (PSM) Function Normal PSM1 PSM2 (Active) State 1 State 2 Display Active? I/O Access Possible?
Page 87: Display Memory Interface
Epson Research and Development Page 79 Vancouver Design Center 9 DISPLAY MEMORY INTERFACE 9.1 SRAM Configurations Supported 9.1.1 8-Bit Mode VD0-7 VWE# 8Kx8 S1D13503 VCS0# VCS1# VA0-12 Figure 42: 8-Bit Mode - 8K bytes SRAM VD0-7 VWE# 8Kx8 8Kx8 S1D13503...
Page 88: Figure 44: 8-Bit Mode - 32K Bytes Sram
Page 80 Epson Research and Development Vancouver Design Center VD0-7 VWE# 32Kx8 S1D13503 VCS0# VCS1# VA0-14 Figure 44: 8-Bit Mode - 32K bytes SRAM (Requires AUX[01] bit 0 = 1) VD0-7 VWE# 8K/32Kx8 32K/8Kx8 S1D13503 VCS0# VCS1# VA0-14 Figure 45: 8-Bit Mode - 40K bytes SRAM...
Page 89: 16-Bit Mode
Epson Research and Development Page 81 Vancouver Design Center VD0-7 VWE# 32Kx8 32Kx8 S1D13503 VCS0# VCS1# VA0-14 Figure 46: 8-Bit Mode - 64K bytes SRAM (Requires AUX[01] bit 0 = 1) 9.1.2 16-bit Mode VD0-7 VWE# 8Kx8 S1D13503 VCS0# VA0-12...
Page 90: Figure 48: 16-Bit Mode - 64K Bytes Sram
Page 82 Epson Research and Development Vancouver Design Center VD0-7 VWE# 32Kx8 S1D13503 VCS0# VA0-14 VCS1# 32Kx8 VD8-15 Figure 48: 16-Bit Mode - 64K bytes SRAM VWE# S1D13503 VCS0# VCS1# VA0-15 A0-15 VD0-7 I/O 1-8 VD8-15 I/O 9-16 Figure 49: 16-Bit Mode - 128K bytes SRAM...
Page 91: Sram Access Time
Epson Research and Development Page 83 Vancouver Design Center 9.2 SRAM Access Time 9.2.1 8-bit Display Memory Interface: Table 9-1: 8-Bit Display Memory Interface SRAM Access Time Display Mode 3V/3.3V 16-level gray shades / 16-level colors Access time < 1 / f - 40ns Access time <...
Page 92: Frame Rate Calculation
Page 84 Epson Research and Development Vancouver Design Center 9.3 Frame Rate Calculation 9.3.1 For single panel Black-and-White (BW) Display Mode: × osc FrameRate ------------------------------------------------------------------------------------------------------------------------------------------------------------------- - × HorizontalPixels PHNDP DHNDP VerticalLines All Other Display Modes: f osc FrameRate ------------------------------------------------------------------------------------------------------------------------------------------------------------------- - ×...
Page 93: Memory Size Calculation
175 ns 60 ns 75 ns (1) Memory more than 128KB cannot be supported by S1D13503. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. (3) 256 color mode must use 16-bit display memory interface.
Page 94: Table 9-4: Memory Size Requirement: Number Of Horizontal Pixels = 480
375 ns 160 ns 175 ns (1) Memory more than 128KB cannot be supported by S1D13503. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. (3) 256 color mode must use 16-bit display memory interface.
Page 95: Mechanical Data
Epson Research and Development Page 87 Vancouver Design Center 10 MECHANICAL DATA QFP5-100PIN-S2 (S1D13503) ± 0.04 23.2 ± 0.1 20.0 Index ± 0.1 ± 0.1 0.65 0.30 0~12° ± 0.1 All dimensions in mm Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503F00A)
Page 96: Figure 51: Mechanical Drawing Qfp15-100-Std (S1D13503)
Page 88 Epson Research and Development Vancouver Design Center QFP15-100PIN-STD (S1D13503) ± 0.4 16.0 ± 0.1 14.0 Index ± 0.1 0.168 0~12° ± 0.2 All dimensions in mm Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503F01A) S1D13503 Hardware Functional Specification X18A-A-001-08 Issue Date: 01/01/29 Downloaded from Elcodis.com...
Page 97 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 98 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Programming Notes and Examples X18A-G-002-06 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 99 INTRODUCTION ........9 INITIALIZING THE S1D13503 ......10 GRAY SHADES / COLORS AND LOOK-UP TABLES .
Page 100 Power Save Modes ........54 IDENTIFYING THE S1D13503 ......56 PROGRAMMING THE S1D13503 .
Page 101 Table 3-5: S1D13503 Color Look-up Table For 256 Color Mode..... . .23 Table 3-6: S1D13503 Black-To-White Look-Up Table ......24 Table 3-7: S1D13503 Inverted Look-Up Table (White-To-Black) .
Page 102 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Programming Notes and Examples X18A-G-002-06 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 103 Epson Research and Development Page 7 Vancouver Design Center LIST OF FIGURES Figure 1: Pixel Storage For 1 Bit (Black-and-White) In One Byte Of Display Memory ..18 Figure 2: Pixel Storage For 2 Bits (4 Colors/Gray Shades) In One Byte Of Display Memory ..18 Figure 3: Pixel Storage For 4 Bits (16 Colors/gray Shades) In One Byte Of Display Memory .
Page 104 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Programming Notes and Examples X18A-G-002-06 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 105: Introduction
Vancouver Design Center 1 INTRODUCTION The purpose of this guide is to demonstrate how to program the S1D13503 LCD controller, with reference made to the S5U13503B00C evaluation board. The first half of this guide presents the basic concepts of LCD controllers.
Page 106: Initializing The S1D13503
Vancouver Design Center 2 INITIALIZING THE S1D13503 This section presents two examples to show how to initialize the S1D13503 registers and write a pixel to the display. Code to initialize the S1D13503 is provided in Section 7.2, “Initialization Code” on page 60.
Page 107 Epson Research and Development Page 11 Vancouver Design Center Data Notes See Also (in Binary) Register • bits 7-2: 0 = WF output toggles every frame (panel specific) AUX[05h] 0000 0000 • bits 1-0 = bits 9-8 of Total Display Line Count (panel specific, see AUX[04h]) •...
Page 108 Page 12 Epson Research and Development Vancouver Design Center Data Notes See Also (in Binary) Register AUX[0Fh] 0000 0100 write Red data AUX[0Fh] 0000 0100 write Green data AUX[0Fh] 0000 1010 write Blue data AUX[0Eh] 0000 0011 increment palette address...
Page 109 Epson Research and Development Page 13 Vancouver Design Center Data Notes See Also (in Binary) Register AUX[0Fh] 0000 1101 write Blue data AUX[0Eh] 0000 1101 increment palette address AUX[0Fh] 0000 0100 write Red data AUX[0Fh] 0000 0100 write Green data...
Page 110 Initialize the registers for a 4 gray shade 640 x 480 dual panel LCD with 128k of display memory. Afterwards write one pixel to the top left corner of the display’s second panel. Program S1D13503 Registers in the following order with the data supplied: Data...
Page 111 Epson Research and Development Page 15 Vancouver Design Center Data Notes See Also (in Binary) Register • bits 15-0 of Screen 1 Display Start Address - normally Screen 1 see Section 4.2.1, Start Address = 0000h (application and panel specific) “S5U13503B00C...
Page 112 Page 16 Epson Research and Development Vancouver Design Center Data Notes See Also (in Binary) Register AUX[0Fh] 0000 1010 write Blue data AUX[0Eh] 0000 0011 increment palette address AUX[0Fh] 0000 0110 write Red data AUX[0Fh] 0000 0110 write Green data...
Page 113 Epson Research and Development Page 17 Vancouver Design Center Data Notes See Also (in Binary) Register AUX[0Fh] 0000 0100 write Red data AUX[0Fh] 0000 0100 write Green data AUX[0Fh] 0000 1001 write Blue data AUX[0Eh] 0000 1110 increment palette address...
Page 114: Gray Shades / Colors And Look-Up Tables
Vancouver Design Center 3 GRAY SHADES / COLORS AND LOOK-UP TABLES This section discusses how the S1D13503 shows color and monochrome images on LCD panels. 3.1 Pixels A pixel is physically stored in display memory as a series of bits. The more bits, the more colors the pixel can show.
Page 115: Memory Organization For Four Bit Pixels (16 Colors/Gray Shades)
Epson Research and Development Page 19 Vancouver Design Center 3.1.3 Memory Organization for Four Bit Pixels (16 Colors/Gray Shades) To store four bit pixels, two pixels are grouped into one byte of display memory as shown below: Bit 7 Bit 6...
Page 116: Look-Up Table (Lut)
Bit 0 The S1D13503 has three internal 16 position, 4-bit wide Look-Up Tables (also referred to as palettes). The 4-bit value programmed into each table position determines the output gray shade / color weighting of display data. These tables are bypassed in black-and-white (BW) display mode.
Page 117 Epson Research and Development Page 21 Vancouver Design Center RGB Index bits [1:0]: These bits are also used to provide access to the three internal Look-Up Tables (RGB). Table 3-3: Look-Up Table Access Aux[0E] Look-Up Table Access bit 5 bit 4...
Page 118: Look-Up Table Description
Indicates the palette is not used for that display mode 3.2.2.1 Color Mode In color mode, the S1D13503 supports three 16 position, 4 bit wide color LUTs (red, green, and blue). Depending on the selected pixel size, these LUTs will provide from 1 to 4 banks.
Page 119 Vancouver Design Center 3.2.2.2 Monochrome Mode In monochrome mode, the S1D13503 treats the green LUT as a 16 position, 4 bit wide monochrome LUT. Depending on the selected pixel size, this LUT will provide from 1 to 4 banks. •...
Page 120 Write LUT index to Look-Up Table Address Register AUX[0Eh]. Write LUT entry value to Look-Up Table Data Register AUX[0Fh]. Repeat steps 1 and 2 until all 16 LUT entries have been written. Table 3-6: S1D13503 Black-To-White Look-Up Table Look-Up Look-Up...
Page 121: Black-And-White (One Bit/Pixel)
This example shows how to invert an image by changing only the LUT. Inverting means that pixels formally shown as light gray shades are now shown as dark gray shades, and vise versa. It does not matter whether the S1D13503 is in 4 gray shade or 16 gray shade mode.
Page 122: Four Gray Shades (Two Bits/Pixel In Monochrome Mode)
3.2.4 Four Gray Shades (Two Bits/Pixel in Monochrome Mode) When the S1D13503 is configured for two bit pixels in monochrome mode, each pixel can index one of four monochrome LUT entries. Note that in monochrome mode, the S1D13503 uses the green LUT as the monochrome LUT. The 16 LUT entries are divided into four separate Look-Up tables or banks, each having four entries (see Figure 5).
Page 123 Epson Research and Development Page 27 Vancouver Design Center 4-Level Gray Shade Mode Green Look-Up Table Bank 0 2-bit pixel data Bank 1 Bank 4-bit display data output Select Bank 2 Logic Bank 3 Bank Select bits [1:0] (Aux[0E] bits [7:6]) Note: the above depiction is intended to show the display data output path only.
Page 124: Four Colors (Two Bits/Pixel In Color Mode)
3.2.5 Four Colors (Two Bits/Pixel in Color Mode) When the S1D13503 is configured for two bit pixels in color mode, each pixel can index one of four color LUT entries. The 16 LUT entries are divided into four separate Look-Up tables or banks, each having four entries (see Figure 6). The following examples show how to program and select these banks.
Page 125 Epson Research and Development Page 29 Vancouver Design Center 4-Level Color Mode RED Look-Up Table Bank 0 2-bit pixel data Bank 1 4-bit ‘RED’ Bank display data output Select Bank 2 Logic Bank 3 Red Bank Select bits [1:0] (Aux[0F] bits [7:6])
Page 126: Sixteen Gray Shades (Four Bits/Pixel In Monochrome Mode)
Vancouver Design Center 3.2.6 Sixteen Gray Shades (Four Bits/Pixel in Monochrome Mode) When the S1D13503 has 4-bit monochrome pixels, each pixel can index into one of 16 LUT entries. The LUT bank bits are ignored in this mode. 16-Level Gray Shade Mode...
Page 127: Sixteen Colors (Four Bits/Pixel In Color Mode)
Vancouver Design Center 3.2.7 Sixteen Colors (Four Bits/Pixel in Color Mode) When the S1D13503 has 4-bit color pixels, each pixel can index into each of the three color LUTs. The LUT bank bits are ignored in this mode. 16-Level Color Mode...
Page 128: Colors (Eight Bits/Pixel In Color Mode)
3.2.8 256 Colors (Eight Bits/Pixel in Color Mode) When the S1D13503 has 8-bit color pixels, bits 7-5 represent the red LUT index, bits 4-2 represent the green LUT index, and bits 1-0 represent the blue LUT index (see Figure 9, “256-Level Color Mode Look-Up Table Architecture,” on page 33).
Page 129 Epson Research and Development Page 33 Vancouver Design Center 256-Level Color Mode 256 Color Data Format: 7 6 5 4 3 2 1 0 Red Look-Up Table Bank 0 3-bit pixel data (R2, R1, R0) 4-bit ‘RED’ Bank display data output...
Page 130: Display Memory Models
Page 34 Epson Research and Development Vancouver Design Center 4 DISPLAY MEMORY MODELS This section includes a concise description of the Display Start Address Registers, followed by a description of display memory. Afterwards examples are provided, illustrating how to calculate the display memory model for a given display resolution and color/gray level mode.
Page 131 Epson Research and Development Page 35 Vancouver Design Center AUX[08] Screen 2 Display Start Address Register (LSB) I/O address = 1000b, Read/Write. Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display...
Page 132: Description
Vancouver Design Center 4.2 Description When displaying an image, the S1D13503 must read pixel data from display memory. This memory is organized to match the display resolution of the given LCD panel. To organize display memory, the following registers must be programmed:...
Page 133: Display Start Address Registers
The S1D13503 has 128k available, so there is 131,072 bytes available. Since this number is greater than the 76,800 bytes required for 640 x 480 with 4 colors, the S1D13503 implementation can support a 640 x 480 LCD with 4 colors.
Page 134: Common Display Memory Requirements For Lcd Panel Sizes
The following is a list of memory requirements and memory maps for common LCD resolutions. Note that the memory required for 640 x 480 with 4 or 16 bits/pixel exceeds 128k and is therefore not supported on the S1D13503. Table 4-1: Memory Size Requirements...
Page 135 Epson Research and Development Page 39 Vancouver Design Center Offset Offset (hex) (hex) 0000 0000 Scan Line 0 0000 013F 0000 0140 Scan Line 1 027F 0001 2980 Scan Line 238 0001 2ABF 0001 2AC0 Scan Line 239 0001 2BFF...
Page 136: Advanced Techniques
5 ADVANCED TECHNIQUES This section presents information on the following: • virtual displays • bitmaps and text displays • reading and writing to the S1D13503 registers • split screen displays • panning and scrolling • power saving 5.1 Virtual Displays This section presents a detailed description of the Address Pitch Adjustment Register, followed by a description of a virtual display.
Page 137: Description
5.1.2 Description The S1D13503 can be programmed to wrap memory offsets in such a way that the physical display behaves as a viewport into a much larger “virtual” memory space. This viewport can be panned and/or scrolled to display this larger memory space.
Page 138: Bitmaps And Text Displays
Page 42 Epson Research and Development Vancouver Design Center 5.2 Bitmaps and Text Displays For the scope of this guide, a bitmap is a data structure which represents the image shown on the LCD. The bitmap includes the dimensions of the image, and the color or gray shade palette used to program the lookup table. Text is shown by creating a font, which in this example is a series of bitmaps, one bitmap per alphanumeric character.
Page 139: Mapping Of Registers
Figure 15: Display Memory Contents For Message “Text” In 256 Color Mode 5.3 Mapping of Registers The S1D13503 has an internal set of 16-/8-bit read/write registers which configure it for various modes of operation. The registers can be accessed in two ways; Indexed Addressing and Direct Addressing.
Page 140: Direct Mapping
SRAM data lines VD[7 through 12]. See “Summary of Configuration Options” in the S1D13503 Hardware Functional Specification, Drawing Office No. X18A-A-001-xx. To access the internal 16 registers of the S1D13503, simply perform I/O read/write functions to the absolute address as defined in the previous paragraph.
Page 141: Split Screen
Epson Research and Development Page 45 Vancouver Design Center 5.4 Split Screen This section describes how to create a split screen for both single and dual LCD panels. For single panel displays, the Screen 1 Display Line Count Registers are used. For dual panel displays, the Screen 2 Display Start Address Registers are used.
Page 142: Single Panel Lcd
Page 46 Epson Research and Development Vancouver Design Center 5.4.2 Single Panel LCD The following is the procedure to show a split screen image on a 16 color 320 x 240 single panel LCD. For this example the S5U13503B00C is used with the Memory Interface set to 16 bits (required for 128k of display memory). In addition, the two images shown on the split screen are each 320 x 240;...
Page 143 Epson Research and Development Page 47 Vancouver Design Center Determine the display memory location for image 2. Place image 2 immediately after image 1 (see Figure 16). Assign the starting address for image 2 as follows: image 2 address base display memory address...
Page 144: Dual Panel Lcd
Page 48 Epson Research and Development Vancouver Design Center • If the line count is set to 99, then the first 100 scan lines of image 1 are shown, following by the first part of im- age 2 (see Figure 17).
Page 145 Notes When using a dual panel, the Screen 1 Display Line Count Register is ignored by the S1D13503. Once the two Display Start Address Registers are programmed, the top panel will show the beginning of image 1, and the bottom panel will show the beginning of image 2 (see Figure 18).
Page 146 Page 50 Epson Research and Development Vancouver Design Center Each image can be scrolled or panned by appropriate programming of the respective Display Start Address Registers. The following are some examples: • To scroll image 1 up, the Screen 1 Start Address Register must point to the following scan line.
Page 147 Epson Research and Development Page 51 Vancouver Design Center Determine the display memory location for the first half of the image. For simplicity, assign the beginning of display memory as the starting address of the image’s first half (see Figure 19). For the S5U13503B00C, this address is D000:0000h, bank 0.
Page 148: Panning And Scrolling
Screen 1 Display Start Address Register. Note that the S1D13503 can pan right or left by either 1, 2, 4, 8, or 16 pixels. This is because the Screen 1 Display Start Address Register refers to either bytes or words (see Section 4.2.1, “S5U13503B00C Evaluation Board Display Memory”...
Page 149: Scrolling Up And Down
Epson Research and Development Page 53 Vancouver Design Center 5.5.3 Scrolling Up and Down To scroll up, increase the value in the Screen 1 Display Start Address Register by the number of bytes in one virtual scan line. To scroll down, decrease the value in the Screen 1 Display Start Address Register by the number of bytes in one virtual scan line.
Page 150: Power Saving
Epson Research and Development Vancouver Design Center 5.6 Power Saving The following section introduces the power saving capabilities of the S1D13503. A detailed description of the Power Save Register is provided, followed by a description of the power save modes. 5.6.1 Registers Register bits discussed in this section are highlighted.
Page 151 Epson Research and Development Page 55 Vancouver Design Center 5.6.2.3 Power Save Mode Function Summary Table 5-4: Power Save Mode Function Summary Power Save Mode (PSM) Function PSM1 PSM2 Normal (Active) State 1 State 2 Display Active? I/O Access Possible?
Page 152: Identifying The S1D13503
Page 56 Epson Research and Development Vancouver Design Center 6 IDENTIFYING THE S1D13503 To identify the LCD controller upon power up / reset, perform the following steps: Power up LCD controller. Read AUX[0Eh], bits 5-4. Refer to Table 6-1 below to decode chip ID.
Page 153: Programming The S1D13503
7 PROGRAMMING THE S1D13503 The purpose of this section is to show how to program the S1D13503 exercising the specific capabilities of this chip. A series of functions written in ‘C’ will be presented, each illustrating a basic feature of the S1D13503. These functions are written for the S5U13503B00C evaluation board, and are combined under a menu-driven program called 13503DEMO.EXE.
Page 154: Main Loop Code
Page 58 Epson Research and Development Vancouver Design Center 7.1 Main Loop Code //------------------------------------------------------------------------- // FUNCTION: main() // DESCRIPTION: Start of demo program. // INPUTS: Command line arguments. // RETURN VALUE: None. //------------------------------------------------------------------------- void main(char argc, char **argv) int ch;...
Page 155 Epson Research and Development Page 59 Vancouver Design Center break; case '2': GrayShadeBars(); break; case '3': SplitScreen(); break; case '4': PanScroll(); break; case '5': PowerSaving(); break; case ESC: exit(0); Programming Notes and Examples S1D13503 Issue Date: 01/01/30 X18A-G-002-06 Downloaded from Elcodis.com...
Page 156: Initialization Code
Vancouver Design Center 7.2 Initialization Code //------------------------------------------------------------------------- // FUNCTION: Initialize() // DESCRIPTION: Intialize S1D13503 registers. // INPUTS: This function looks at the followingl global variables to determine the appropriate register settings: PanelX, PanelY, PanelType // OUTPUTS: The following global variables are changed:...
Page 157 Epson Research and Development Page 61 Vancouver Design Center // Line Byte/Word Count Register // Bits 0-7 are in AUX[2], Bit 8 is in AUX[3]. // Because the Memory Interface is set to 16 bits, the // Line Byte/Word Count Register counts in words.
Page 158 Page 62 Epson Research and Development Vancouver Design Center case 2: BytesPerScanLine = (PanelX / 8); break; case 4: BytesPerScanLine = (PanelX / 4); break; case 16: BytesPerScanLine = (PanelX / 2); break; case 256: BytesPerScanLine = PanelX; break; //--------------------------------------...
Page 159 Epson Research and Development Page 63 Vancouver Design Center --val; WriteRegister(4, val & 0xff); // Write to Total Display Line Count Reg WriteRegister(0x0a, val & 0xff); // Write to Screen 1 Display Line Count Reg WriteRegister(5, (val >> 8) & 0x03); // Total Disp Line Cnt (MSB)/WF Count Reg WriteRegister(0x0b, (val >>...
Page 160 Page 64 Epson Research and Development Vancouver Design Center // Set Address Pitch Adjustment to 0 WriteRegister(0x0d, 0); // Write to Address Pitch Adjustment Register //-------------------------------------- // Update Lookup Table for 16 gray shades/ 256 colors if (PanelD == PANEL_MONO) for (x = 0;...
Page 161 Epson Research and Development Page 65 Vancouver Design Center ChipID = ID_NOT_DETECTED; // If the chip was just powered up, and no registers have been initialized, // then use the following code: outp(PortAddr, 0x0e); switch (inp(PortAddr+1) & 0x30) case 0x00: ChipID = ID_13503;...
Page 162: Advanced Functions
7.3 Advanced Functions #define VIRTUAL_X (360L) #define VIRTUAL_Y (360L) //------------------------------------------------------------------------- // FUNCTION: ShowRegisters() // DESCRIPTION: Shows the contents of the S1D13503 registers. // INPUTS: None. // RETURN VALUE: None. //------------------------------------------------------------------------- void ShowRegisters(void) static unsigned char x; static unsigned char red, green, blue;...
Page 163 Epson Research and Development Page 67 Vancouver Design Center For monochrome displays, bars are shown for black and white, 4, and 16 gray shades. // INPUTS: None. // RETURN VALUE: None. //------------------------------------------------------------------------- void GrayShadeBars(void) static unsigned int val, val2, x;...
Page 164 Page 68 Epson Research and Development Vancouver Design Center // are ((x horizontal pixels)/8) bytes per scan line. This means that // there are ((x horizontal pixels)/16) words per scan line. // Since the Memory Interface is set to 16 bits, the Line Byte/Word Count // refers to words.
Page 165 Epson Research and Development Page 69 Vancouver Design Center str = Gray4; else // 4 colors val = ReadRegister(1); val &= 0xf7; // Clear AUX[01] bit 3 WriteRegister(1, val); val = ReadRegister(3); val &= 0xfb; // Clear AUX[03] bit 2 val |= 0x02;...
Page 166 Page 70 Epson Research and Development Vancouver Design Center // Show text. The lightest color/gray shade is set to PanelGrayLevel-1. ShowText(pVideo, BANK0, str, PanelGrayLevel-1); ShowText(pVideo + BytesPerScanLine*8, BANK0, "BANK: 0", PanelGrayLevel-1); SetDisplay(ON); Delay(2000); val = ReadRegister(0x0e); val &= 0x3f; val |= 0x40;...
Page 167 Epson Research and Development Page 71 Vancouver Design Center for (x = 0; x < 16; ++x) WriteRegister(0x0e, x); WriteRegister(0x0f, MonoLUT16[x]); str = Gray16; else // 16 colors val = ReadRegister(1); val |= 0x08; // Set AUX[01] bit 3 WriteRegister(1, val);...
Page 168 Page 72 Epson Research and Development Vancouver Design Center PanelGrayLevel = 16; ShowVerticalBars(pVideo, 0); // Show text. The lightest color/gray shade is set to PanelGrayLevel-1. ShowText(pVideo, BANK0, str, PanelGrayLevel-1); SetDisplay(ON); Delay(2000); //-------------------------------------- if (PanelD == PANEL_COLOR) SetDisplay(OFF); ClearLCDScreen(); // Select 256 colors val = ReadRegister(3);...
Page 169 Epson Research and Development Page 73 Vancouver Design Center val2 = ReadRegister(3); val2 &= 0xfe; // Clear bit 0 val2 |= (val >> 8) & 0x01; WriteRegister(3, val2); // Mode Register 1 PanelGrayLevel = 256; ShowVerticalBars(pVideo, 0); // Show text.
Page 170 Page 74 Epson Research and Development Vancouver Design Center { 0x30, 0x78, 0x78, 0x30, 0x30, 0x00, 0x30, 0x00 }, // ! { 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00 }, // " { 0x6C, 0x6C, 0xFE, 0x6C, 0xFE, 0x6C, 0x6C, 0x00 },...
Page 171 Epson Research and Development Page 75 Vancouver Design Center { 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0x78, 0x30, 0x00 }, // V { 0xC6, 0xC6, 0xC6, 0xD6, 0xFE, 0xEE, 0xC6, 0x00 }, // W { 0xC6, 0xC6, 0x6C, 0x38, 0x38, 0x6C, 0xC6, 0x00 },...
Page 172 Page 76 Epson Research and Development Vancouver Design Center else inp(PanelPortAddr+2); switch (PanelGrayLevel) case 2: // If there are 2 gray levels, there are 8 pixels/byte color &= 0x01; while (*str != 0) ch = *str++; if ((ch < ' ') || (ch - ' ' > MAX_FONT-1)) ch = '.';...
Page 173 Epson Research and Development Page 77 Vancouver Design Center Video |= color; *pVideo++ = (unsigned char) Video; CheckBank(pVideo, &bank); pVideoFirstColumn += BytesPerScanLine; ++pVideoStart; // Point to next character pVideoFirstColumn = pVideoStart; break; case 4: // If there are 4 colors/gray levels, there are 4 pixels/byte color &= 0x03;...
Page 174 Page 78 Epson Research and Development Vancouver Design Center Video = 0; if (val & 0x08) Video |= (color << 6); if (val & 0x04) Video |= (color << 4); if (val & 0x02) Video |= (color << 2); if (val & 0x01) Video |= color;...
Page 175 Epson Research and Development Page 79 Vancouver Design Center *pVideo++ = (unsigned char) Video; CheckBank(pVideo, &bank); Video = 0; if (val & 0x20) Video |= (color << 4); if (val & 0x10) Video |= color; *pVideo++ = (unsigned char) Video;...
Page 176 Page 80 Epson Research and Development Vancouver Design Center pVideo = pVideoFirstColumn; Video = 0; val = *pFont++; // Since there are 256 colors, each bit in the font will be // represented in video memory as an 8 bit pixel.
Page 177 Epson Research and Development Page 81 Vancouver Design Center printf("Showing Split Screen\n"); Initialize(); SetDisplay(OFF); ClearLCDScreen(); // Access memory banks FP_SEG(pVideoImage1) = 0xd000; FP_OFF(pVideoImage1) = 0x0000; switch (PanelGrayLevel) case 2: BytesPerScanLine = (PanelX / 8); break; case 4: BytesPerScanLine = (PanelX / 4);...
Page 178 Page 82 Epson Research and Development Vancouver Design Center else Image2Bank = BANK0; ShowHorizontalBars(pVideoImage2, Image2Bank); // Show text. The lightest color/gray shade is set to PanelGrayLevel-1. ShowText(pVideoImage1, BANK0, "SPLIT SCREEN IMAGE ONE", PanelGrayLevel-1); ShowText(pVideoImage2, Image2Bank, "SPLIT SCREEN IMAGE TWO", PanelGrayLevel-1);...
Page 179 Epson Research and Development Page 83 Vancouver Design Center WriteRegister(0x0a, val & 0xff); // Total Display Line Count WriteRegister(0x0b, (val >> 8) & 0x03); // Total Disp Line Cnt/WF Count Delay(DELAY_SHORT); // Scroll image 2 up for (val = OriginalLineCount; val > (unsigned int) MinLineCount; val -= 1) WriteRegister(0x0a, val &...
Page 180 Page 84 Epson Research and Development Vancouver Design Center static unsigned int MaxX, MaxY; static unsigned int val, pitch; static unsigned char _far *pVideo; static unsigned char bank, color; printf("Showing Panning and Scrolling\n"); Initialize(); SetDisplay(OFF); ClearLCDScreen(); switch (PanelGrayLevel) case 16: pitch = (unsigned int) (((VIRTUAL_X / 2) - BytesPerScanLine) / 2);...
Page 181 Epson Research and Development Page 85 Vancouver Design Center FP_OFF(pVideo) = (unsigned int) ((rand() * 0xffffL) / RAND_MAX); val = rand() % 50; switch (PanelGrayLevel) case 16: color = (unsigned char) (rand() % 16); break; case 256: color = (unsigned char) (rand() % 256);...
Page 182 Page 86 Epson Research and Development Vancouver Design Center ShowMenu(); //------------------------------------------------------------------------- // FUNCTION: PowerSaving() // DESCRIPTION: Starts power saving mode 2. // INPUTS: None. // RETURN VALUE: None. //------------------------------------------------------------------------- void PowerSaving(void) static unsigned int val; printf("Starting Power Saving\n"); // The following are the steps to enter a power save mode.
Page 183 Epson Research and Development Page 87 Vancouver Design Center printf("Press any key to cancel power saving\n"); getch(); // The following are the steps to exit a power save mode. // Step 1: Exit Power Save Mode val = ReadRegister(3); val &= 0x3f;...
Page 184: Glossary
The up and down movement of the viewport in a virtual display. S1D13503 The 13503 chip. S5U13503B00C The evaluation board for the S1D13503. The S5U13503B00C is an ISA board for a PC- compatible computer. viewport The visible portion of a virtual display.
Page 185 1 n/a bits should be written 0. 2 These bits are used to identify the S1D13503 at power on / RESET. If these bits read 00b at Power On / Reset the device is an S1D13503F00A. If this bit reads 10b at Power On / Reset the device is an...
Page 186 S1D13503F00A Register Summary X18A-Q-002-05 Page 2 01/03/02 Downloaded from Elcodis.com electronic components distributor...
Page 187 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 188 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 13503SHOW.EXE Display Utility X18A-B-001-05 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 189 13503SHOW.EXE DISPLAY UTILITY 13503SHOW is a utility used to load and display GIF images. It can also be used to demonstrate the split screen capabilities of the S1D13503 by loading two images and vertically scrolling one image. Program Requirements Video Controller...
Page 190 Page 4 Epson Research and Development Vancouver Design Center Examples: with no arguments will run the program in split screen mode. 13503show This will display two predefined images, with screen one displaying horizontal bars and screen two displaying vertical bars. Screen two may be scrolled up and down using the arrow, page up, page down, home and end keys.
Page 191 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 192 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 13503VIRT.EXE Display Utility X18A-B-002-05 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 193 Vancouver Design Center 13503VIRT.EXE DISPLAY UTILITY 13503VIRT.EXE demonstrates the virtual panning capabilities of the S1D13503. Two images larger than the display resolution are loaded in display memory. 13503VIRT.EXE will then display, in a split screen, a portion of each complete image while providing panning capabilities using the arrow keys for navigation.
Page 194 Page 4 Epson Research and Development Vancouver Design Center Comments • 13503VIRT requires 13503BIOS.COM to be loaded prior to running. Program Messages ERROR: This program requires 13503BIOS to be loaded! The program 13503BIOS.COM must be run before 13503VIRT.EXE. Load 13503BIOS.COM and then re-run 13503VIRT.EXE.
Page 195 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 196 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 13503BIOS.COM Utility X18A-B-003-05 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 197 INT 10h. This program provides text, scroll, and cursor functionality when no VGA BIOS is present. Although the S1D13503 is not a VGA or EGA compatible controller, this program is supplied to give the user a familiar prompt. Within limits 13503BIOS simulates a VGA BIOS and will allow standard output functions to work. DOS programs such as Edlin, Format, Debug, and internal commands such as Copy, Ren, Mkdir, etc., should work.
Page 198 The panel specified is too large to run in 16 gray shades mode. Select 4 gray shades instead. ERROR: Video memory and VGA BIOS memory conflict. Both the S1D13503 video memory and the VGA BIOS are trying to use the memory at location C000h to CFFFh. ERROR: only 64k or 128k memory allowed.
Page 199 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 200 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 13503MODE.EXE Display Utility X18A-B-004-05 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 201 Vancouver Design Center 13503MODE.EXE DISPLAY UTILITY 13503MODE is a menu driven display utility for the S1D13503 which demonstrates the color /gray shades as well as available palettes. For 128K bytes of display memory either 4, 16 or 256 colors/gray shades are available.
Page 202 Page 4 Epson Research and Development Vancouver Design Center Comments • 13503MODE requires 13503BIOS.COM to be loaded prior to running. Program Messages ERROR: This program requires 13503BIOS to be loaded! The program 13503BIOS.COM must be run before 13503MODE. Load 13503BIOS.COM and then re-run 13503MODE.EXE.
Page 203 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 204 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 13503PD.EXE Power Down Utility X18A-B-005-05 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 205 13503PD.EXE POWER DOWN UTILITY 13503PD is an OEM utility program for setting power down modes in the S1D13503 LCD Display Controller that supports the SOLLEX Super VGA Standard video BIOS extensions. It provides a simple method for setting power modes during power consumption testing.
Page 206 Program Messages Power Down Mode xx is set. The power down mode xx has been set. This message may not be visible if the active display controller is the S1D13503. ERROR: Cannot set power mode xx! 13503PD.EXE cannot set the power down mode requested - either 13503BIOS.COM is not loaded or the power down mode number exceeds 2.
Page 207 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 208 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 13503READ.EXE Diagnostic Utility X18A-B-006-05 Issue Date: 01/01/29 Downloaded from Elcodis.com electronic components distributor...
Page 209 13503READ.EXE DIAGNOSTIC UTILITY 13503READ is an OEM utility program which enables the user to read the S1D13503 register contents. It is a useful utility for OEMs wishing to submit a problem report for the video controller. If run with 13503BIOS loaded, it will try to interpret the BIOS settings.
Page 210 Program Messages ERROR: 13503 registers not responding at port address [port]. 13503READ has not found an S1D13503 at the port address specified. Check the command line port setting for 13503BIOS and/or 13503READ to ensure it is correct and re-run the program.
Page 211 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 212 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 213 Epson Research and Development Page 3 Vancouver Design Center TABLE OF CONTENTS S5U13503B00C REV 1.0 EVALUATION BOARD ....7 Features ....... . 7 INSTALLATION AND CONFIGURATION .
Page 214 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 215 Epson Research and Development Page 5 Vancouver Design Center LIST OF TABLES Table 2-1: Configuration DIP Switch Settings ......8 Table 2-2: I/O Mapping Example .
Page 216 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 217: S5U13503B00C Rev 1.0 Evaluation Board
Vancouver Design Center 1 S5U13503B00C REV 1.0 EVALUATION BOARD This manual reflects the use of the S5U13503B00C Rev 1.0 evaluation board in conjunction with the S1D13503 LCD Controller. All appropriate components are surface-mount to reduce cost and minimize board space.
Page 218: Installation And Configuration
2 INSTALLATION AND CONFIGURATION The S1D13503 uses the display memory data lines (VD[15:0]) as configuration inputs which are read on power-up. For the purpose of this design, most of these configuration inputs have been factory set and therefore are not configurable. An eight...
Page 219 For Non-ISA bus support (see page 14), the following signal lines may require the 10K ohm pull-up resistors installed: VD4 (R18), VD5 (R19), VD6 (R20), VD10 (R21) and/or VD13 (R17) See the S1D13503 Hardware Functional Specification, X18A-A-001-xx, page 21 for configuration details. S5U13503B00C Rev. 1.0 Evaluation Board User Manual...
Page 220 /LCDPWR /LCDPWR /LCDPWR /LCDPWR /LCDPWR /LCDPWR /LCDPWR See Sections 7.4.3 and 7.4.5 of the S1D13503 Hardware Functional Specification, X18A-A-001.01, for details. From external logic; see Section 3.5 for details. S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com...
Page 221 +12V 12 volt supply /SBHE Connected to the BHE# signal of the S1D13503 IOCHRDY Connected to the READY signal of the S1D13503 /IOSC Connected to the IOCS# signal of the S1D13503 /MEMCS Connected to the MEMCS# signal of the S1D13503 S5U13503B00C Rev.
Page 222 Connected to AB19 of the S1D13503 Ground Ground 5 volt supply 5 volt supply /IOW Connected to the IOW# signal of the S1D13503 /IOR Connected to the IOR# signal of the S1D13503 /SMEMW Connected to the MEMW# signal of the S1D13503 /SMEMR...
Page 223: Technical Description
ISA Bus support have been assembled, refer to Hard-Wired Configuration Inputs, on page 9 for configuration details. External logic has been added to provide signals which the S1D13503 does not directly support. See Application Note X18A-G-003-xx for details.
Page 224: Non-Isa Bus Support
Voltage lines are provided on the header strips. U2, a TIBPAL22V10 PAL, is currently used to provide the S1D13503 IOCS# (pin 23) and MEMCS# (pin 22) input signals for ISA bus use. This functionality must now be provided externally as U2 must be removed.
Page 225: Color Lcd Support
XSCL This circuit provides 16-bit color panel support by latching the 8 bits of output data from the S1D13503 to provide 16 bits of data on the next clock. Refer to Table 2-4, LCD Signal Connector J1 Pinout, on page 10 for specific settings.
Page 226: Crystal Support
When the oscillator package is used capacitors C7, C8 and resistor R16 must be removed. 3.11 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of S1D13503, with the exception of SA16, are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than the ISA bus.
Page 227: Appendix A Parts List
Epson Research and Development Page 17 Vancouver Design Center Appendix A Parts List Item # Qty/board Designation Part Value Description C11-C23 0.01uF 0.01uF, 1206 pckg C9 -C10 10uF 10uF / 25V Tantalum D-SIZE C7-C8 7pF, 1206 pckg C2-C4 10uF / 63V...
Page 228: Appendix B S5U13503B00C Rev. 1.0 Schematic Diagrams
Page 18 Epson Research and Development Vancouver Design Center Appendix B S5U13503B00C Rev. 1.0 Schematic Diagrams Figure 1: S5U13503B00C Rev. 1.0 Schematic Diagram (1 of 7) S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com...
Page 229 Epson Research and Development Page 19 Vancouver Design Center Figure 2: S5U13503B00C Rev. 1.0 Schematic Diagram (2 of 7) S5U13503B00C Rev. 1.0 Evaluation Board User Manual S1D13503 Issue Date: 01/01/30 X18A-G-007-05 Downloaded from Elcodis.com electronic components distributor...
Page 230 Page 20 Epson Research and Development Vancouver Design Center Figure 3: S5U13503B00C Rev. 1.0 Schematic Diagram (3 of 7) S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 231 Epson Research and Development Page 21 Vancouver Design Center Figure 4: S5U13503B00C Rev. 1.0 Schematic Diagram (4 of 7) S5U13503B00C Rev. 1.0 Evaluation Board User Manual S1D13503 Issue Date: 01/01/30 X18A-G-007-05 Downloaded from Elcodis.com electronic components distributor...
Page 232 Page 22 Epson Research and Development Vancouver Design Center Figure 5: S5U13503B00C Rev. 1.0 Schematic Diagram (5 of 7) S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 233 Epson Research and Development Page 23 Vancouver Design Center Figure 6: S5U13503B00C Rev. 1.0 Schematic Diagram (6 of 7) S5U13503B00C Rev. 1.0 Evaluation Board User Manual S1D13503 Issue Date: 01/01/30 X18A-G-007-05 Downloaded from Elcodis.com electronic components distributor...
Page 234 Page 24 Epson Research and Development Vancouver Design Center Figure 7: S5U13503B00C Rev. 1.0 Schematic Diagram (7 of 7) S1D13503 S5U13503B00C Rev. 1.0 Evaluation Board User Manual X18A-G-007-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 235 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 236 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 Power Consumption X18A-G-006-04 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 237 Epson Research and Development Page 3 Vancouver Design Center 1 S1D13503 POWER CONSUMPTION 1.1 Conditions Table 1-1: S1D13503 Total Power Consumption - 3.0V Operation Total Power Consumption Gray Shades / Test Condition Power Save Mode Colors Active 5.4 mW 1.2 mW...
Page 238 Page 4 Epson Research and Development Vancouver Design Center S1D13503 Total Power Consumption - 3V Condition 1 - BW Condition 1 - 4 grays Condition 1 - 16 grays Condition 2 - 4 color Condition 2 - 16 color Condition 2 - 256 color...
Page 239 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 240 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 ISA Bus Interface Considerations X18A-G-003-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 241 Additional Discrete Logic Description ......7 S1D13503 Default Setup ......7 2.3.1 Configuration Options .
Page 242 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 ISA Bus Interface Considerations X18A-G-003-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 243: Introduction
Vancouver Design Center 1 INTRODUCTION The S1D13503 is a general purpose LCD controller capable of interfacing to a variety of microprocessors. In some cases this interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the S1D13503 and the ISA Bus both 8 and 16-bit implementations.
Page 244: 16-Bit Isa Bus Interface
This memory configuration will conflict with a VGA card installed on the same bus, therefore either a serial terminal or monochrome display adapter is recommended as the primary console. This section provides the necessary logic equations and settings to complete the interface between the S1D13503 and the 16-bit ISA Bus.
Page 245: Pal Equations
IOCS# = !(!AEN & !A15 & !A14 & !A13 & !A12 & !A11 & !A10) As the S1D13503 is capable of 16-bit I/O access, the IOCS16# bus signal must be driven externally to indicate such a cycle. As stated in the ISA specification, the IOCS16# is a straight address decode without qualification.
Page 246: Register Setting
Page 8 Epson Research and Development Vancouver Design Center 2.3.2 Register Setting All register settings are completely programmable with the following exceptions: - Memory Interface, AUX[1] bit 1 = 0 for 16-bit memory interface. Note This bit is forced = 0 when 16-bit CPU Interface is selected through VD0 on power-up.
Page 247: 8-Bit Isa Bus Interface
This section provides the necessary settings to complete the interface between the S1D13503 and the 8-bit ISA Bus. Since I/O addresses are partially decoded, there is no need to use a PAL for decoding.
Page 248: S1D13503 Default Setup
3.1.1 Configuration Options The S1D13503 latches the state of the SRAM data bus during RESET to determine the power-on configuration. The chip has internal pull-down resistors and therefore external pull-ups are only necessary when requiring a ’1’ state, see below.
Page 249 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 250 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 MC68340 Interface Considerations X18A-G-004-04 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 251 PAL Equations ....... . . 7 S1D13503 Default Setup ......7 List of Figures Figure 1: MC68340 MPU Interface Block Diagram .
Page 252 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 MC68340 Interface Considerations X18A-G-004-04 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 253: Introduction
Vancouver Design Center 1 INTRODUCTION The S1D13503 is a general purpose LCD controller capable of interfacing to a variety of microprocessors. This interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the S1D13503 and the 16-bit MC68340 microcontroller.
Page 254: Mc68340 Mpu Interface
The internal chip select signal CS3 of the MC68340, along with external DSACK1 response, is employed to access the S1D13503. Direct mapping of the I/O with starting address at 00000000h, and 128Kbytes of display memory with starting address 00020000h are also used.
Page 255: Pal Equations
S1D13503; IOCS# = !(!CS3 & !A17 & !A16 & !A15 & !A14 & !A13 & !A12 & !A11 & !A10) With memory locations from 00020000h to 003FFFFh and A17 to A19 decoded internally to S1D13503; MEMCS# = CS3 BHE# becomes valid for two conditions: 1.
Page 256 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 MC68340 Interface Considerations X18A-G-004-04 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 257 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 258 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 LCD Panel Options / Memory Requirements X18A-G-005-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 259 Epson Research and Development Page 3 Vancouver Design Center Table of Contents INTRODUCTION ........5 Reference Material .
Page 260 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 LCD Panel Options / Memory Requirements X18A-G-005-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 261: Introduction
Vancouver Design Center 1 INTRODUCTION The S1D13503 is a highly configurable general purpose LCD controller. The LCD panel frame-rate, resolution, and number of colors / gray shades all determine the memory and input clock requirements. This application note describes the equations used to determine the various parameters.
Page 262: Configuration Equations
Page 6 Epson Research and Development Vancouver Design Center 2 CONFIGURATION EQUATIONS This application note will follow one example through all the required calculations. For a complete description of all formula and associated parameters refer to the Hardware Functional Specification.
Page 263: Sram Size And Access Time Requirements
Functional Specification, drawing office number X18A-A-001-xx. 2.2.2 SRAM Access Time To support 256 color modes the S1D13503 must be configured to support a 16-bit data path into display memory (SRAM). For 16-bit display memory interface the required SRAM access time must be: SRAM Access time <...
Page 264: Implementation
Page 8 Epson Research and Development Vancouver Design Center 4 IMPLEMENTATION 4.1 16-Bit Display Memory Interface Since 76.8K bytes with at least 127ns access time SRAM is required, one 64Kx16 byte SRAM with 120ns access time will be used for this example.
Page 265 GREEN:[00 02 04 06 09 0B 0D 0F]0F 0D 0B 09 06 04 02 00 BLUE: [00 05 0A 0F]0F 0A 05 00 01 06 09 0E 0D 09 04 02 Note Refer to S1D13503 Programming Notes and Examples, X18A-G-002-xx, for further information. LCD Panel Options / Memory Requirements S1D13503...
Page 266 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 LCD Panel Options / Memory Requirements X18A-G-005-05 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 267 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Downloaded from Elcodis.com...
Page 268 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13503 / S1D13502 Comparison X18A-G-008-04 Issue Date: 01/01/30 Downloaded from Elcodis.com electronic components distributor...
Page 269 1 S1D13503 / S1D13502 Comparison The S1D13503 is pin compatible with, and includes all features of the S1D13502. This allows an easy upgrade path for the system designer, both from the hardware and software aspect. The purpose of this document is to briefly describe the differ- ences between these two controllers, for further details refer to the individual Hardware Functional Specifications.
Page 270 Page 4 Epson Research and Development Vancouver Design Center 1.2 S1D13503 Register Changes / Additions From The S1D13502 See the S1D13503 Hardware Functional Specification, X18A-A-001-xx, for details on these registers. AUX[01h] bit 2 LCD Data Width bit 0 bit 3...

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