Epson S1D13503 Series Technical Manual
  1. Manuals
  2. Brands
  3. Epson Manuals
  4. Controller
  5. S1D13503 Series
  6. Technical manual

Epson S1D13503 Series Technical Manual

Dot matrix graphics lcd controller
Hide thumbs Also See for S1D13503 Series:
Table of Contents

Advertisement

Quick Links

Download this manual
MF1020-02
Dot Matrix Graphics LCD Controller
S1D13503 Series
Technical Manual

Advertisement

Table of Contents
loading

Related Manuals for Epson S1D13503 Series

Summary of Contents for Epson S1D13503 Series

  • Page 1 MF1020-02 Dot Matrix Graphics LCD Controller S1D13503 Series Technical Manual...
  • Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products.
  • Page 3 The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.

  • Page 4: Hardware Functional Specification

    S1D13503F00A Technical Manual HARDWARE FUNCTIONAL SPECIFICATION PROGRAMMING NOTES AND EXAMPLES UTILITIES S5U13503P00C PCI BUS EVALUATION BOARD USER’S MANUAL APPLICATION NOTES...

  • Page 6: Table Of Contents

    HARDWARE FUNCTIONAL SPECIFICATION Table of Contents .........................1-1 NTRODUCTION 1.1 Scope ............................1-1 1.2 Overview Description ........................1-1 ..........................1-2 EATURES 2.1 Technology ............................1-2 2.2 System ............................1-2 2.3 Display Modes ..........................1-2 2.4 Display Support ..........................1-3 2.5 Power Management ........................1-3 ..................1-4 YPICAL YSTEM LOCK IAGRAMS 16-Bit MC68000 MPU ........................1-4 MPU with READY (or WAIT#) Signal..................1-5 ISA Bus .............................1-6...
  • Page 7 LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels ......1-25 LCD Interface Timing - 4-Bit Single Color Panel ..............1-27 LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels.... 1-28 LCD Interface Timing - 16-Bit Single/Dual Color Panels ............1-29 LCD Interface Timing - 8-Bit Single Color Panels Format 1 ............
  • Page 8 List of Figures Figure 3-1 16-Bit 68000 Series (example implementation only - actual may vary) .......1-4 Figure 3-2 8-Bit Mode, Example: Z80 (example implementation only - actual may vary) .....1-5 Figure 3-3 16-Bit Mode, Example: i8086 (maximum mode) (example implementation only - actual may vary)1-5 Figure 3-4 8-Bit Mode (ISA) (example implementation only - actual may vary) ........1-6...
  • Page 9 Figure 9-6 16-Bit Mode - 16K bytes SRAM ..................1-55 Figure 9-7 16-Bit Mode - 64K bytes SRAM ..................1-55 Figure 9-8 16-Bit Mode - 128K bytes SRAM ..................1-56 Figure 10-1 Mechanical Drawing QFP5-100-S2 ................... 1-60 Figure 10-2 Mechanical Drawing QFP15-100-STD................1-61...
  • Page 10 List of Tables Table 5-1 Bus Interface ........................1-13 Table 5-2 Display Memory Interface....................1-14 Table 5-3 LCD Interface ........................1-14 Table 5-4 Clock Inputs........................1-14 Table 5-5 Power Supply ........................1-14 Table 5-6 Summary of Power On / Reset Options ................1-15 Table 5-7 I/O and Memory Addressing Example................1-15 Table 6-1 Absolute Maximum Ratings....................1-16 Table 6-2...

  • Page 11: Introduction

    S1D13503 Series Hardware Functional Specification NTRODUCTION 1.1 Scope This is the Functional Specification for the S1D13503 Dot Matrix Graphic Color LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences, Video Subsystem Designers and Software Developers.

  • Page 12: Features

    EPSON EATURES 2.1 Technology • low power CMOS • 2.7 to 5.5 volt operation • S1D13503F00A is 100 pin QFP5-S2 surface mount package • S1D13503F01A is 100 pin QFP15-STD surface mount package • S1D13503D00A is Die form 2.2 System • maximum 25 MHz input clock (or pixel clock) •...

  • Page 13: Display Support

    S1D13503 Series Hardware Functional Specification 2.4 Display Support • example resolutions: – 1024 × 768 black-and-white – 640 × 480 with 4 colors/grays – 640 × 400 with 16 colors/grays – 320 × 240 with 256 colors • passive monochrome LCD panels: –...

  • Page 14: 16-Bit Mc68000 Mpu

    EPSON YPICAL YSTEM LOCK IAGRAMS The following figures show typical system implementations of the S1D13503. All of the following block diagrams are shown without SRAM or LCD display. Refer to the interface specific Applica- tion Notes for complete details. 16-Bit MC68000 MPU...

  • Page 15: Mpu With Ready (Or Wait#) Signal

    S1D13503 Series Hardware Functional Specification MPU with READY (or WAIT#) Signal S1D13503 Decoder MEMCS# MREQ# A10 to A15 Decoder IOCS# IORQ# AB0 to AB15 A0 to A15 DB0 to DB7 D0 to D7 READY WAIT# MEMW# MEMR# IOR# IOW# RESET...

  • Page 16: Isa Bus

    EPSON ISA Bus 8-Bit ISA Bus S1D13503 REFRESH MEMCS# SA13 to SA16 Decoder MEMW# SMEMW# MEMR# SMEMR# READY IOCHRDY DB0 to DB7 SD0 to SD7 AB0 to AB19 SA0 to SA19 Decoder SA10 to SA15 IOCS# IOW# IOW# IOR# IOR#...

  • Page 17: Internal Block Diagram

    S1D13503 Series Hardware Functional Specification 3.1 Internal Block Diagram Control Registers IOR#, IOW#, IOCS#, MEMCS#, Port LCDENB MEMR#, MEMW#, Decoder Bus Signal Sequence UD[3:0], BHE#, AB[19:0] Translation Controller LD[3:0], Memory Look-Up Panel LP, YD, READY Decoder Table Interface XSCL, WF (XSCL2)

  • Page 18: Data Bus Conversion

    EPSON Data Bus Conversion According to configuration setting VD0, the Data Bus Conversion Block maps the external data bus, either 8-bit or 16-bit, into the internal odd and even data bus. Address Generator The Address Generator generates display refresh addresses to be used to access display memory.

  • Page 19: Pinout Diagram

    S1D13503 Series Hardware Functional Specification INOUT IAGRAM XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# VA10 MEMR# READY S1D13503F00A BHE# OSC1 OSC2 INDEX RESET AB19 Figure 4-1 S1D13503F00A Pinout Diagram Note: Package type: 100 pin surface mount QFP5-S2 ∗ Pin 80 = WF in all display modes except format 1 for 8-bit single color panel.

  • Page 20: Figure 4-2 S1D13503F01A Pinout Diagram

    EPSON WF/XSCL2* XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# VA10 READY S1D13503F01A BHE# OSC1 OSC2 INDEX RESET AB19 AB18 AB17 Figure 4-2 S1D13503F01A Pinout Diagram Note: Package type: 100 pin surface mount QFP15-STD ∗ Pin 77 = WF in all display modes except format 1 for 8-bit single color panel.

  • Page 21: Figure 4-3 S1D13503D00A Pad Diagram

    S1D13503 Series Hardware Functional Specification Dummy Pad WF/XSCL2* XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# VA10 MEMR# S1D13503D00A READY BHE# OSC1 OSC2 RESET AB19 AB18 Dummy Pad = 5.030 mm × 5.030 mm Chip Size Chip Thickness = 0.400 mm = 0.090 mm ×...
  • Page 22 EPSON PAD Coordinates (Unit: mm) Pad Center Coordinate Pad Center Coordinate Pad No. Pad Name Pad No. Pad Name -2.165 -2.390 – 2.000 2.390 – -2.000 -2.390 1.840 2.390 -1.840 -2.390 1.685 2.390 -1.685 -2.390 1.535 2.390 -1.535 -2.390 VD10 1.388...

  • Page 23: Description

    S1D13503 Series Hardware Functional Specification ESCRIPTION 5.1 Description Key: = Input = Output = Bidirectional (Input/Output) = Power pin = CMOS level output driver, x denotes driver type (see Table 6-4, “Output Specifications,” on page 17) COxS = CMOS level output driver with slew rate control for noise reduction, x denotes driver type (see Table 6-4, “Output Specifications,”...

  • Page 24: Table 5-2 Display Memory Interface

    EPSON Table 5-2 Display Memory Interface F00A F01A D00A Pin Name Type Driver Description Pin No. Pin No. Pad No. VD0–VD15 44–51, 41–48, 54–55, TS1D2 These pins are connected to the display memory data bus. For 16-bit 54–61 51–58 57–61, interface, VD0–VD7 are connected to the display memory data bus...

  • Page 25: Summary Of Configuration Options

    S1D13503 Series Hardware Functional Specification 5.2 Summary of Configuration Options The S1D13503 requires some configuration information on power-up. This information is provided through the SRAM data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to configure the following options:...

  • Page 26: Table 6-1 Absolute Maximum Ratings

    EPSON 6 D.C. C HARACTERISTICS Table 6-1 Absolute Maximum Ratings Symbol Parameter Rating Units Supply Voltage -0.3 to +6.0 Input Voltage -0.3 to V + 0.5 Output Voltage -0.3 to V + 0.5 Storage Temperature -65 to 150 °C Solder Temperature/Time 260 for 10 sec.

  • Page 27: Table 6-4 Output Specifications

    S1D13503 Series Hardware Functional Specification Table 6-4 Output Specifications Symbol Parameter Condition Min. Typ. Max. Units Low Level Output Voltage = Min. – – (5.0V) Type 1 - TS1D2, CO1 = 4mA Type 2 - TS2 = 8mA Type 3 - TS3, CO3, CO3S...

  • Page 28: Bus Interface Timing

    EPSON 7 A.C. C HARACTERISTICS Conditions: V = 3.0V ± 10%, V = 3.3V ± 10% or V = 5.0V ± 10%, T = -40°C to 85°C for all inputs must be ≤ 5 nsec (10% ~ 90%) rise fall...

  • Page 29: Ior# Timing

    S1D13503 Series Hardware Functional Specification IOR# Timing AB[9:1] VALID IOCS# UDS#/LDS# R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 7-2 IOR# Timing (MC68000) Table 7-2 IOR# Timing (MC68000) 3V/3.3V Symbol Parameter Units Min. Max. Min. Max. AB[9:1] and IOCS# valid before AS# falling edge –...

  • Page 30: Memr# Timing

    EPSON MEMR# Timing AB[19:1] VALID MEMCS# UDS#/LDS# R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 7-4 MEMR# Timing (MC68000) Table 7-4 MEMR# Timing (MC68000) 3V/3.3V Symbol Parameter Units Min. Max. Min. Max. AB[19:1] and MEMCS# valid before AS# falling edge –...

  • Page 31: Non-Mc68000, Mpu/Bus With Ready (Or Wait#) Signal

    S1D13503 Series Hardware Functional Specification Non-MC68000, MPU/Bus with READY (or WAIT#) Signal IOW# Timing AB[9:0] VALID BHE# IOCS# IOW# Hi-Z Hi-Z DB[15:0] VALID Figure 7-5 IOW# Timing (Non-MC68000) Table 7-5 IOW# Timing (Non-MC68000) 3V/3.3V Symbol Parameter Units Min. Max. Min.

  • Page 32: Memr# Timing

    EPSON Table 7-7 MEMW# Timing (Non-MC68000) 3V/3.3V Symbol Parameter Units Min. Max. Min. Max. AB[19:0], BHE# and MEMCS# valid before MEMW# falling edge – – AB[19:0], BHE# and MEMCS# hold from MEMW# rising edge – – MEMW# falling edge to READY falling edge –...

  • Page 33: Clock Input Requirements

    S1D13503 Series Hardware Functional Specification 7.2 Clock Input Requirements Clock Input Waveform Figure 7-9 Clock Input Requirements Table 7-9 Clock Input Requirements Symbol Parameter Min. Typ. Max. Units Input clock period (CLKI) – – Input clock pulse width high (CLKI) –...

  • Page 34: Display Memory Interface Timing

    EPSON 7.3 Display Memory Interface Timing Write Data to Display Memory VA[15:0] VALID VCS0#, VCS1# VWE# VOE# Hi-Z Hi-Z Hi-Z Hi-Z VD[15:0] INPUT OUTPUT INPUT Figure 7-11 Write Data to Display Memory Table 7-10 Write Data to Display Memory 3V/3.3V...

  • Page 35: Lcd Interface

    S1D13503 Series Hardware Functional Specification 7.4 LCD Interface LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels S1D13503 outputs S1D13503 outputs (AUX[01] bit 5 = 0) XSCL UD[3:0] LD[3:0] S1D13503 outputs (AUX[01] bit 5 = 1) XSCL UD[3:0] LD[3:0]...

  • Page 36: Table 7-12 Lcd Interface Timing - 4-Bit Single And 8-Bit Single/Dual Monochrome Panel

    EPSON Table 7-12 LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel 4-Bit Single 8-Bit Single/Dual Symbol Parameter Units Min. Max. Min. Max. LP period (single panel mode) HT + HNDP – HT + HNDP – - 10 - 10 2 ∗...

  • Page 37: Lcd Interface Timing - 4-Bit Single Color Panel

    S1D13503 Series Hardware Functional Specification LCD Interface Timing - 4-Bit Single Color Panel XSCL Figure 7-14 LCD Interface Timing - 4-Bit Single Color Panel Table 7-13 LCD Interface Timing - 4-Bit Single Color Panel Symbol Parameter Min. Typ. Max. Units...

  • Page 38: Lcd Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels

    EPSON LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels XSCL UD/LD Figure 7-15 LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels Table 7-14 LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels...

  • Page 39: Lcd Interface Timing - 16-Bit Single/Dual Color Panels

    S1D13503 Series Hardware Functional Specification LCD Interface Timing - 16-Bit Single/Dual Color Panels XSCL UD/LD Figure 7-16 LCD Interface Timing - 16-Bit Single/Dual Color Panels Table 7-15 LCD Interface Timing - 16-Bit Single/Dual Color Panels Symbol Parameter Min. Typ. Max.

  • Page 40: Lcd Interface Timing - 8-Bit Single Color Panels Format 1

    EPSON LCD Interface Timing - 8-Bit Single Color Panels Format 1 XSCL2 (WF) XSCL UD/LD Figure 7-17 LCD Interface Timing - 8-Bit Single Color Panels Format 1 Table 7-16 LCD Interface Timing - 8-Bit Single Color Panels Format 1 Symbol Parameter Min.

  • Page 41: Lcd Interface Options

    S1D13503 Series Hardware Functional Specification LCD Interface Options LP: 240 PULSES LP: 4 PULSES UD[3:0] ---------- LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 XSCL: 80 CLOCK PERIODS XSCL ------------------------- 1-317 ------------------------- 1-318 ------------------------- 1-319 ------------------------- 1-320 Example timing for a 320 × 240 panel...

  • Page 42: Figure 7-20 8-Bit Dual Monochrome Panel Timing

    EPSON LP: 240 PULSES LP: 2 PULSES UD[3:0] ---------- LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 LD[3:0] LINE241 LINE242 LINE243 LINE244 ---------- LINE479 LINE480 LINE241 LINE242 XSCL: 160 CLOCK PERIODS XSCL ------------------------- 1-637 ------------------------- 1-638 ------------------------- 1-639 ------------------------- 1-640...
  • Page 43 S1D13503 Series Hardware Functional Specification LP: 480 PULSES LP: 4 PULSES UD[3:0], LD[3:0] ---------- LINE1 LINE2 LINE3 LINE4 LINE479 LINE4840 LINE1 LINE2 XSCL2: 120 CLOCK PERIODS XSCL2 XSCL: 120 CLOCK PERIODS XSCL -------------------------------------- 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12 1-B635...
  • Page 44 EPSON LP: 240 PULSES LP: 4 PULSES UD[3:0], LD[3:0] ---------- LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 XSCL: 120 CLOCK PERIODS XSCL ------------------------- 1-R1 1-B3 1-G6 1-G318 ------------------------- 1-G1 1-R4 1-B6 1-B318 ------------------------- 1-B1 1-G4 1-R7 1-R319 ------------------------- 1-R2...

  • Page 45: Figure 7-24 8-Bit Dual Color Panel Timing

    S1D13503 Series Hardware Functional Specification LP: 240 PULSES LP: 2 PULSES UD[3:0] ---------- LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 LD[3:0] LINE241 LINE242 LINE243 LINE244 ---------- LINE479 LINE480 LINE241 LINE242 XSCL: 480 CLOCK PERIODS XSCL ------------------------------------- 1-R1 1-G2 1-B3...

  • Page 46: Figure 7-26 16-Bit Single Color Panel Timing With External Circuit

    EPSON LP: 480 PULSES LP: 4 PULSES Pixel Data ---------- LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 XSCL: 120 CLOCK PERIODS XSCL ------- 1-R1 1-B3 1-B635 1-G638 ------- 1-B1 1-G4 1-G636 1-R639 ------- 1-G2 1-R5 1-R637 1-B639 ------- 1-R3...

  • Page 47: Figure 7-27 16-Bit Dual Color Panel Timing With External Circuit

    S1D13503 Series Hardware Functional Specification LP: 240 PULSES LP: 2 PULSES Pixel Data ---------- LINE1/241 LINE2/242 LINE3/243 LINE4/244 LINE239/479 LINE240/480 LINE1/241 LINE2/242 XSCL: 240 CLOCK PERIODS XSCL ------- 1-R1 1-G2 1-B3 1-G638 1-B639 ------- 1-G1 1-B2 1-R4 1-B638 1-R640 -------...

  • Page 48: Register Descriptions

    EPSON ARDWARE EGISTER NTERFACE The S1D13503 is configured and controlled via 16 internal 8-bit registers. There are two ways to map these registers into the system I/O space. 1. Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped address (where base I/O address is selected by VD7–VD12, see Table 5-6.)

  • Page 49: Table 8-1 Gray Shade/Color Mode Selection

    S1D13503 Series Hardware Functional Specification AUX[01] Mode Register 0 I/O address = 0001b, Read/Write DISP Panel Mask LCDE Gray Shade / LCD Data Memory RAMS XSCL Color Width Bit 0 Interface bit 7 DISP This bit selects display on or off. When this bit = 0, Display OFF is selected (LD0–3 and UD0–3 are forced to 0).
  • Page 50 EPSON bit 2 LCD Data Width Bit 0 Together with LCD Data Width bit 1 (AUX[03] bit 3) this bit selects different display data formats. The following table shows the function of these two bits: Table 8-2 LCD Data Width...

  • Page 51: Table 8-3 Maximum Value Of Line Byte Count Register - 8-Bit Display Memory Interface

    S1D13503 Series Hardware Functional Specification The following two tables summarize the maximum value of the Line Byte Count Register for different display modes and display memory interface. Table 8-3 Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface...
  • Page 52 EPSON bit 1 Color Mode When this bit = 1, color display modes are selected. When bit = 0, BW/gray shade display modes are selected. This bit goes low on RESET. See Table 8-1, “Gray Shade/Color Mode Selection,” on page 39 for details.
  • Page 53 S1D13503 Series Hardware Functional Specification AUX[06] Screen 1 Display Start Address Register (LSB) I/O address = 0110b, Read/Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Start Display Start Display Start...
  • Page 54 EPSON AUX[0A] Screen 1 Display Line Count Register (LSB) I/O address = 1010b, Read/Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Line Display Line Display Line Display Line Display Line...
  • Page 55 S1D13503 Series Hardware Functional Specification AUX[0D] Address Pitch Adjustment Register I/O address = 1101b, Read/Write Addr Pitch Addr Pitch Addr Pitch Addr Pitch Addr Pitch Addr Pitch Addr Pitch Addr Pitch Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Bit 7...

  • Page 56: Table 8-6 Id Bit Usage

    EPSON bits 5–4 ID Bits / RGB Index Bits [1:0] These bits have dual purpose; ID Bits: After power on or hardware reset, these bits can be read to identify the current revision of the S1D13503. These same bits are used to identify the pin compatible SED1352 and would only be used in system implementations where common software is being used.
  • Page 57 S1D13503 Series Hardware Functional Specification bits 3–0 Palette Data Bits [3:0] These 4 bits are the gray shade / color values used for display data output. They are pro- grammed into the 4-bit Look-Up Table (palettes) positions pointed to by Palette Address bits [3:0] and RGB Index bits [1:0] (if in color display modes).

  • Page 58: Look-Up Table Architecture

    EPSON 8.2 Look-Up Table Architecture Table 8-8 Look-Up Table Configurations 4-Bit Wide Palette Display Mode GREEN BLUE Black & White 4-level gray 4 banks of 4 16-level gray 1 bank of 16 4 color 4 banks of 4 4 banks of 4...

  • Page 59: Color Display Modes

    S1D13503 Series Hardware Functional Specification Color Display Modes 4-Level Color Mode Red Look-Up Table Bank 0 2-bit pixel data Bank 1 Bank 4-bit ‘RED’ display data output Select Bank 2 Logic Bank 3 Bank Select bits [1:0] AUX[0F] bits [7:6]...

  • Page 60: 16-Level Color Mode

    EPSON 16-Level Color Mode Red Look-Up Table 16 x 4 4-bit pixel data 4-bit ‘RED’ Look-Up Table data output Green Look-Up Table 16 x 4 4-bit ‘GREEN’ Look-Up Table data output Blue Look-Up Table 16 x 4 4-bit ‘BLUE’ Look-Up Table data output...

  • Page 61: 256-Level Color Mode

    S1D13503 Series Hardware Functional Specification 256-Level Color Mode 256 Color Data Format: Red Look-Up Table Bank 0 3-bit pixel data Bank Select Bank 1 Logic Bank Select bits [1:0] AUX[0F] bit 6 Green Look-Up Table Bank 0 3-bit pixel data...

  • Page 62: Power Save Modes

    EPSON 8.3 Power Save Modes Two software-controlled Power Save Modes have been incorporated into the S1D13503 to accom- modate the important need for power reduction in the hand-held devices market. These modes can be enabled by setting the two Power Save bits (AUX[03] bits 7:6).

  • Page 63: Pin States In Power Save Modes

    S1D13503 Series Hardware Functional Specification Pin States in Power Save Modes Table 8-11 Pin States in Power Save Modes Pin State Normal PSM1 PSM2 (Active) State 1 State 2 UD[3:0], LD[3:0], LP, Active High High High XSCL, YD, WF/XSCL2 Impedance...

  • Page 64: Display Memory Interface

    EPSON ISPLAY EMORY NTERFACE 9.1 SRAM Configurations Supported 8-Bit Mode VD0-7 VWE# 8K × 8 S1D13503 VCS0# VCS1# VA0-12 Figure 9-1 8-Bit Mode - 8K bytes SRAM (Requires AUX[01] bit 0 = 0) VD0-7 VWE# 8K × 8 8K × 8...

  • Page 65: 16-Bit Mode

    S1D13503 Series Hardware Functional Specification VD0-7 VWE# S1D13503 8K/32K × 8 32K/8K × 8 VCS0# VCS1# VA0-14 Figure 9-4 8-Bit Mode - 40K bytes SRAM [Either (8K × 8 + 32K × 8) requiring AUX[01] bit 0 = 0 or (32K × 8 + 8K × 8) requiring AUX[01] bit 0 = 1]...
  • Page 66 EPSON VD0-7 VWE# 32K × 8 S1D13503 VCS0# VA0-14 VCS1# 32K × 8 VD8-15 Figure 9-7 16-Bit Mode - 64K bytes SRAM VWE# 64K × 16 S1D13503 VCS0# VCS1# VA0-15 A0-15 VD0-7 I/O 1-8 VD8-15 I/O 9-16 Figure 9-8 16-Bit Mode - 128K bytes SRAM...

  • Page 67: Sram Access Time

    S1D13503 Series Hardware Functional Specification 9.2 SRAM Access Time 8-Bit Display Memory Interface Table 9-1 8-Bit Display Memory Interface SRAM Access Time Display Mode 3V/3.3V 16-level gray shades / 16-level colors Access time ≤ 1 / f - 40ns Access time ≤ 1 / f - 25ns Access time ≤...

  • Page 68: Memory Size Calculation

    EPSON 9.4 Memory Size Calculation × × HorizontalPixels VerticalLines BitsPerPixel Memory Size (bytes) = ---------------------------------------------------------------------------------------------------------------------------------------------- - Example: For a 640 × 480, 4 gray shades (2 bits-per-pixel) system: × × 2 ( ) Memory Size (bytes) = ----------------------------------------------- - 76800bytes 75Kbytes 9.5 Memory Size Requirement...
  • Page 69 S1D13503 Series Hardware Functional Specification Table 9-4 Memory Size Requirement: Number of Horizontal Pixels = 480 Number of Horizontal Pixels = 480 Display Black-and-White (BW) 4 Grays / 4 Colors 16 Grays / 16 Colors 256 Colors Mode (1 bit-per-pixel)

  • Page 70: Mechanical Data

    EPSON 10 M ECHANICAL ±0.4 23.2 ±0.1 INDEX +0.1 0.65 –0.05 ±0.05 0.15 0° 10° ±0.2 All dimensions in mm Figure 10-1 Mechanical Drawing QFP5-100-S2 1-60 S18A-A-011-01...
  • Page 71 S1D13503 Series Hardware Functional Specification ±0.4 ±0.1 INDEX +0.1 0.18 –0.05 +0.05 0.125 –0.025 0° 10° ±0.2 All dimensions in mm Figure 10-2 Mechanical Drawing QFP15-100-STD S18A-A-011-01 1-61...
  • Page 72 EPSON THIS PAGE IS BLANK. 1-62 S18A-A-011-01...
  • Page 74 PROGRAMMER’S REFERENCE Table of Contents .........................2-1 NTRODUCTION S1D13503.....................2-2 NITIALIZING THE ...............2-8 HADES OLORS AND ABLES 3.1 Pixels .............................2-8 Memory Organization for One Bit Pixel (Black-and-White) ............2-8 Memory Organization for Two Bit Pixels (4 Colors/Gray Shades) ..........2-8 Memory Organization for Four Bit Pixels (16 Colors/Gray Shades)...........2-8 Memory Organization for Eight Bit Pixels (256 Colors)..............2-9 3.2 Look-Up Table (LUT)........................2-9 LUT Registers ..........................2-9...
  • Page 75 S1D13503 ....................2-43 ROGRAMMING THE 7.1 Main Loop Code.......................... 2-44 7.2 Initialization Code........................2-46 7.3 Advanced Functions........................2-51 ..........................2-69 LOSSARY 8 S1D13503 R ....................2-70 EGISTER UMMARY...
  • Page 76 List of Figures Figure 3-1 Pixel Storage for 1 Bit (Black-and-White) in one byte of Display Memory ......2-8 Figure 3-2 Pixel Storage for 2 Bits (4 colors/gray shades) in one byte of Display Memory....2-8 Figure 3-3 Pixel Storage for 4 Bits (16 colors/gray shades) in one byte of Display Memory....2-8 Figure 3-4 Pixel Storage for 8 Bits (256 colors) in one byte of Display Memory ........2-9 Figure 3-5...

  • Page 77: Introduction

    S1D13503 Programming Notes and Examples NTRODUCTION The purpose of this guide is to demonstrate how to program the S1D13503 LCD controller, with ref- erence made to the S5U13503P00C evaluation board. The first half of this guide presents the basic concepts of LCD controllers. The second half of this guide presents programming examples which are combined in a simple menu-driven program.

  • Page 78: Initializing The S1D13503

    EPSON S1D13503 NITIALIZING THE This section presents two examples to show how to initialize the S1D13503 registers and write a pixel to the display. Code to initialize the S1D13503 is provided in Section 7.2, “Initialization Code” on page 46. The following examples describe values written to registers.
  • Page 79 S1D13503 Programming Notes and Examples Data Notes See Also Register (in Binary) AUX[06h] 0000 0000 • bits 15–0 of Screen 1 Display Start Address - normally see “S5U13503P00C Evaluation AUX[07h] 0000 0000 Screen 1 Start Address = 0000h (application and panel spe- Board Display Memory”...
  • Page 80 EPSON Data Notes See Also Register (in Binary) AUX[0Fh] 0000 1111 write Green data AUX[0Fh] 0000 0000 write Blue data AUX[0Eh] 0000 1000 increment palette address AUX[0Fh] 0000 1111 write Red data AUX[0Fh] 0000 1111 write Green data AUX[0Fh] 0000 0001 write Blue data...
  • Page 81 S1D13503 Programming Notes and Examples Note: The S5U13503P00C evaluation board maps the 128K of display memory into two banks of 64K, starting at D000:0000. This permits a VGA card to work along with the S5U13503P00C card. Bank 0 represents the first 64K of display memory, and is selected by reading from the base port address + 2.
  • Page 82 EPSON Data Notes See Also Register (in Binary) AUX[0Ah] 1110 1111 • bits 7–0 = bits 7–0 of Screen 1 Display Line Count see Section 5.4, “Split Screen” bits 9–8 of Screen 1 Display Line Count in bits 1–0 of...
  • Page 83 S1D13503 Programming Notes and Examples Data Notes See Also Register (in Binary) AUX[0Fh] 0000 1011 write Green data AUX[0Fh] 0000 1001 write Blue data AUX[0Eh] 0000 1100 increment palette address AUX[0Fh] 0000 0110 write Red data AUX[0Fh] 0000 0110 write Green data AUX[0Fh] 0000 1101 write Blue data AUX[0Eh] 0000 1101 increment palette address AUX[0Fh] 0000 0100 write Red data...

  • Page 84: Gray Shades / Colors And Look -U P Tables

    EPSON HADES OLORS AND ABLES This section discusses how the S1D13503 shows color and monochrome images on LCD panels. 3.1 Pixels A pixel is physically stored in display memory as a series of bits. The more bits, the more colors the pixel can show.

  • Page 85: Memory Organization For Eight Bit Pixels (256 Colors)

    S1D13503 Programming Notes and Examples Memory Organization for Eight Bit Pixels (256 Colors) To store eight bit pixels, one pixel is stored in one byte of display memory as shown below: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 86 EPSON RGB Index Bits [1:0]: These bits are also used to provide access to the three internal Look-Up Tables (RGB). Table 3-3 Look-Up Table Access AUX[0E] Look-Up Table Access Bit 5 Bit 4 Auto-increment (see Note) Red palette R/W access...

  • Page 87: Look-Up Table Description

    S1D13503 Programming Notes and Examples Look-Up Table Description • The Look-Up Table (LUT, or palette) treats the value of a pixel as an index into an array of colors or gray shades. For example, a pixel value of zero would point to the first LUT entry; a pixel value of 7 would point to the eighth LUT entry.
  • Page 88 EPSON • 2 bits-per-pixel (4 gray shades) In this format the pixel is an index into the monochrome LUT. The monochrome LUT supports 4 banks (see “Four Gray Shades (Two Bits/Pixel in Monochrome Mode)” on page 14). • 4 bits-per-pixel (16 gray shades) In this format the pixel is an index into the monochrome LUT.
  • Page 89 S1D13503 Programming Notes and Examples Example 4 Initialize the Look-Up Table for 16 gray shades The following describes how to initialize the Look-Up table for 16 gray shades. Table 3-6 shows a LUT with gray shades starting from black (index 0) and finishing in white (index 15, or 0Fh). 1.

  • Page 90: Black-And-White (One Bit/Pixel)

    EPSON Black-and-White (One Bit/Pixel) When the S1D13503 is configured for one bit pixels, the monochrome (green) LUT is not used. Instead, a pixel value of 0 represents black and a pixel value of 1 represents white. Note: One bit/pixel is only available in monochrome mode.
  • Page 91 S1D13503 Programming Notes and Examples 4-Level Gray Shade Mode Green Look-Up Table Bank 0 2-bit pixel data Bank 1 Bank 4-bit display data output Select Bank 2 Logic Bank 3 Bank Select bits [1:0] AUX[0E] bits [7:6] Note: The above depiction is intended to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the various ‘banking’...

  • Page 92: Four Colors (Two Bits/Pixel In Color Mode)

    EPSON Four Colors (Two Bits/Pixel in Color Mode) When the S1D13503 is configured for two bit pixels in color mode, each pixel can index one of four color LUT entries. The 16 LUT entries are divided into four separate Look-Up tables or banks, each having four entries (see Figure 3-6).

  • Page 93: Figure 8-4 16-Level Color Mode Look-Up Table Architecture

    S1D13503 Programming Notes and Examples 4-Level Color Mode Red Look-Up Table Bank 0 2-bit pixel data Bank 1 Bank 4-bit ‘RED’ display data output Select Bank 2 Logic Bank 3 Bank Select bits [1:0] AUX[0F] bits [7:6] Green Look-Up Table Bank 0 Bank 1 Bank...

  • Page 94: Sixteen Gray Shades (Four Bits/Pixel In Monochrome Mode)

    EPSON Sixteen Gray Shades (Four Bits/Pixel in Monochrome Mode) When the S1D13503 has 4-bit monochrome pixels, each pixel can index into one of 16 LUT entries. The LUT bank bits are ignored in this mode. 16-Level Gray Shade Mode Green Look-Up Table 16 x 4...

  • Page 95: Sixteen Colors (Four Bits/Pixel In Color Mode)

    S1D13503 Programming Notes and Examples Sixteen Colors (Four Bits/Pixel in Color Mode) When the S1D13503 has 4-bit color pixels, each pixel can index into each of the three color LUTs. The LUT bank bits are ignored in this mode. 16-Level Color Mode Red Look-Up Table 16 x 4 4-bit pixel data 4-bit ‘RED’...

  • Page 96: Colors (Eight Bits/Pixel In Color Mode)

    EPSON 256 Colors (Eight Bits/Pixel in Color Mode) When the S1D13503 has 8-bit color pixels, bits 7–5 represent the red LUT index, bits 4–2 represent the green LUT index, and bits 1-0 represent the blue LUT index (see Figure 3-9, “256-Level Color Mode Look-Up Table Architecture,”...
  • Page 97 S1D13503 Programming Notes and Examples 256-Level Color Mode 256 Color Data Format: Red Look-Up Table Bank 0 3-bit pixel data Bank Select Bank 1 Logic Bank Select bits [1:0] AUX[0F] bit 6 Green Look-Up Table Bank 0 3-bit pixel data Bank Select Bank 1...

  • Page 98: Registers

    EPSON ISPLAY EMORY ODELS This section includes a concise description of the Display Start Address Registers, followed by a description of display memory. Afterwards examples are provided, illustrating how to calculate the display memory model for a given display resolution and color/gray level mode. Once this model is calculated, examples on programming the Display Start Address Registers are provided.
  • Page 99 S1D13503 Programming Notes and Examples AUX[08] Screen 2 Display Start Address Register (LSB) I/O address = 1000b, Read/Write Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Start Display Start Display Start Display Start Display Start Display Start...

  • Page 100: Description

    EPSON 4.2 Description When displaying an image, the S1D13503 must read pixel data from display memory. This memory is organized to match the display resolution of the given LCD panel. To organize display memory, the following registers must be programmed: 1.

  • Page 101: Display Start Address Registers

    S1D13503 Programming Notes and Examples Display Start Address Registers This section illustrates how to properly calculate the values for the Screen Start Address Registers for a given LCD panel resolution. However, this section is limited to single panel displays; refer to “Dual Panel LCD”...

  • Page 102: Common Display Memory Requirements For Lcd Panel Sizes

    EPSON 4.3 Common Display Memory Requirements for LCD Panel Sizes The following is a list of memory requirements and memory maps for common LCD resolutions. Note that the memory required for 640 × 480 with 4 or 8 bits/pixel exceeds 128K and is therefore not supported on the S1D13503.

  • Page 103: Virtual Displays

    S1D13503 Programming Notes and Examples DVANCED ECHNIQUES This section presents information on the following: • virtual displays • bitmaps and text displays • reading and writing to the S1D13503 registers • split screen displays • panning and scrolling • power saving 5.1 Virtual Displays This section presents a detailed description of the Address Pitch Adjustment Register, followed by a description of a virtual display.

  • Page 104: Description

    EPSON Description The S1D13503 can be programmed to wrap memory offsets in such a way that the physical display behaves as a viewport into a much larger “virtual” memory space. This viewport can be panned and/ or scrolled to display this larger memory space.

  • Page 105: Bitmaps And Text Displays

    S1D13503 Programming Notes and Examples 5.2 Bitmaps and Text Displays For the scope of this guide, a bitmap is a data structure which represents the image shown on the LCD. The bitmap includes the dimensions of the image, and the color or gray shade palette used to program the lookup table.

  • Page 106: Mapping Of Registers

    EPSON 5.3 Mapping of Registers The S1D13503 has an internal set of 16-/8-bit read/write registers which configure it for various modes of operation. The registers can be accessed in two ways; Indexed Addressing and Direct Addressing. Note: Refer to the S1D13503 Hardware Functional Specification for more information on the S1D13503 registers.

  • Page 107: Split Screen

    S1D13503 Programming Notes and Examples Note: The S5U13503P00C is normally configured for indexed mapping, not direct mapping. Refer to the S5U13503P00C Evaluation Board User’s Manual for more information configuring the S5U13503P00C board for indexed or direct mapping. 5.4 Split Screen This section describes how to create a split screen for both single and dual LCD panels.
  • Page 108 EPSON 1. Determine whether the Display Start Address Registers refer to bytes or words. Since the Memory Interface is set to 16 bits, the Display Start Address Registers refer to words. Note that when addresses refer to words, the image must be aligned in memory such that the beginning is found on a word boundary (the least significant bit of the memory address must be...

  • Page 109: Dual Panel Lcd

    S1D13503 Programming Notes and Examples 7. Program the Screen 2 Display Start Address Register to point to the beginning of image 2. Image 2 is placed right after image 1, as shown below: Size of image 1 in bytes Screen 2 display start address Screen 1 display start address -------------------------------------------------------------- - 2 bytes per word...
  • Page 110 EPSON 2. Calculate the number of bytes per scan line. → 4 gray shades 2 bits per pixel → 2 bits per pixel 4 pixels per byte Pixels per scan line Number of bytes per scan line -------------------------------------------------- - --------- -...
  • Page 111 S1D13503 Programming Notes and Examples Notes When using a dual panel, the Screen 1 Display Line Count Register is ignored by the S1D13503. Once the two Display Start Address Registers are programmed, the top panel will show the begin- ning of image 1, and the bottom panel will show the beginning of image 2 (see Figure 5-6). Scan Line 0 Image 1 Scan Line 239...

  • Page 112: Displaying A Single Image On A Dual Panel

    EPSON Displaying a Single Image on a Dual Panel The following is the procedure to show a single image on a dual panel LCD. In this procedure the single image is broken into two smaller images; the first half of the image is placed on the top panel and the second half is placed on the bottom panel.
  • Page 113 S1D13503 Programming Notes and Examples 6. Determine the display memory location for the second half of the image. Place the second half of the image immediately after the first half (see Figure 5-7). Assign the starting address for the second half as follows: Address of second half of image Base display memory address Size of first half of image...

  • Page 114: Panning And Scrolling

    EPSON 5.5 Panning and Scrolling Panning and scrolling are typically used to show an image which is too large to be shown completely on an LCD panel. Although the image is stored entirely in display memory, only a small portion is actually visible on the LCD panel.
  • Page 115 S1D13503 Programming Notes and Examples 2. Add the number of words in a virtual scan line to the Screen 1 Display Start Address Register. In this example the Screen 1 Display Start Address points to the beginning of the image. Number of bytes in a virtual scan line Screen 1 display start address Screen 1 display start address...

  • Page 116: Power Saving

    EPSON 5.6 Power Saving The following section introduces the power saving capabilities of the S1D13503. A detailed descrip- tion of the Power Save Register is provided, followed by a description of the power save modes. Registers Register bits discussed in this section are highlighted.

  • Page 117: Programming To Enter Power Down Mode

    S1D13503 Programming Notes and Examples Programming to Enter Power Down Mode If the LCDENB pin is used to control an external LCDBIAS power supply, the following sequence is recommended to prevent damage to the panel. Panel damage can occur if the LCDBIAS is present without active panel sync signals.

  • Page 118: Identifying The S1D13503

    EPSON S1D13503 DENTIFYING THE To identify the LCD controller upon power up / reset, perform the following steps: 1. Power up LCD controller. 2. Read AUX[0Eh], bits 5–4. Refer to Table 6-1 below to decode chip ID. Table 6-1 ID-Bit Usage...

  • Page 119: Programming The S1D13503

    S1D13503 Programming Notes and Examples S1D13503 ROGRAMMING THE The purpose of this section is to show how to program the S1D13503 exercising the specific capabil- ities of this chip. A series of functions written in ‘C’ will be presented, each illustrating a basic fea- ture of the S1D13503.

  • Page 120: Main Loop Code

    EPSON 7.1 Main Loop Code //------------------------------------------------------------------------- // FUNCTION: main() // DESCRIPTION: Start of demo program. // INPUTS: Command line arguments. // RETURN VALUE: None. //------------------------------------------------------------------------- void main(char argc, char **argv) int ch; CheckArguments(argc, argv); printf("Initializing\n"); Initialize(); SetDisplay(OFF); ClearLCDScreen(); switch (GetID(PanelPortAddr)) case ID_1352FOA: printf("Detected SED1352F0A.\n\n");...
  • Page 121 S1D13503 Programming Notes and Examples break; case '5': PowerSaving(); break; case ESC: exit(0); S18A-G-002-02 2-45...

  • Page 122: Initialization Code

    EPSON 7.2 Initialization Code //------------------------------------------------------------------------- // FUNCTION: Initialize() // DESCRIPTION: Intialize S1D13503 registers. // INPUTS: This function looks at the followingl global variables to determine the appropriate register settings: PanelX, PanelY, PanelType // OUTPUTS: The following global variables are changed:...
  • Page 123 S1D13503 Programming Notes and Examples Memory Interface Width switch (PanelGrayLevel) case 2: val = (PanelX / 16) - 1; // For black and white mode break; case 4: val = (PanelX / 8) - 1; // For 4 gray shades/colors break;...
  • Page 124 EPSON // To show a full image on Screen 1, copy the Total Display Line Count // into the Screen 1 Display Line Count. // Old programs had previously assumed that all panels smaller // than 400 lines use a 4 bit interface. However, newer panels // which are less than 400 lines may use an 8 bit interface.
  • Page 125 S1D13503 Programming Notes and Examples // On a single panel, Screen 1 was programmed to show all of its // lines. Consequently Screen 2 will not be seen, and so the // Screen 2 Display Start Address will have no observable effect. // For convenience, set the screen 2 address to 0.
  • Page 126 EPSON // This function returns the Chip ID. //------------------------------------------------------------------------- static unsigned char GetID(int PortAddr) static unsigned char ChipID; ChipID = ID_NOT_DETECTED; // If the chip was just powered up, and no registers have been initialized, // then use the following code: outp(PortAddr, 0x0e);...

  • Page 127: Advanced Functions

    S1D13503 Programming Notes and Examples 7.3 Advanced Functions #define VIRTUAL_X (360L) #define VIRTUAL_Y (360L) //------------------------------------------------------------------------- // FUNCTION: ShowRegisters() // DESCRIPTION: Shows the contents of the S1D13503 registers. // INPUTS: None. // RETURN VALUE: None. //------------------------------------------------------------------------- void ShowRegisters(void) static unsigned char x; static unsigned char red, green, blue;...
  • Page 128 EPSON static unsigned char _far *pVideo; static char Gray4[] = "Vertical Bars at 4 Gray Shades"; static char Color4[] = "Vertical Bars at 4 Colors"; static char Gray16[] = "Vertical Bars at 16 Gray Shades"; static char Color16[] = "Vertical Bars at 16 Colors";...
  • Page 129 S1D13503 Programming Notes and Examples SetDisplay(ON); Delay(2000); //-------------------------------------- SetDisplay(OFF); ClearLCDScreen(); // Select 4 gray shades/colors if (PanelD == PANEL_MONO) val = ReadRegister(1); val &= 0xf7; // Clear AUX[01] bit 3 WriteRegister(1, val); val = ReadRegister(3); val &= 0xf9; // Clear AUX[03] bits 1 and 2 WriteRegister(3, val);...
  • Page 130 EPSON // there are ((x horizontal pixels)/8) words per scan line. // Since the Memory Interface is set to 16 bits, the Line Byte/Word Count // refers to words. val = (PanelX / 8) - 1; BytesPerScanLine = (PanelX / 4);...
  • Page 131 S1D13503 Programming Notes and Examples val = ReadRegister(3); val &= 0xf9; // Clear AUX[03] bits 1 and 2 WriteRegister(3, val); // Update Lookup Table for 16 gray shades for (x = 0; x < 16; ++x) WriteRegister(0x0e, x); WriteRegister(0x0f, MonoLUT16[x]); str = Gray16;...
  • Page 132 EPSON // Show text. The lightest color/gray shade is set to PanelGrayLevel-1. ShowText(pVideo, BANK0, str, PanelGrayLevel-1); SetDisplay(ON); Delay(2000); //-------------------------------------- if (PanelD == PANEL_COLOR) SetDisplay(OFF); ClearLCDScreen(); // Select 256 colors val = ReadRegister(3); val |= 0x06; // Set AUX[03] bits 1 and 2 WriteRegister(3, val);...
  • Page 133 S1D13503 Programming Notes and Examples SetDisplay(ON); Delay(2000); else SetDisplay(ON); ShowMenu(); //------------------------------------------------------------------------- // ShowText() // DESCRIPTION: Writes text to the LCD panel. Text must only contain the letters A-Z, and the space character. All other characters are replaced by spaces. // NOTES: It is assumed that a pixel set to a value of 0 represents the background color (black).
  • Page 134 EPSON { 0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x00 }, // : { 0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x60 }, // ; { 0x18, 0x30, 0x60, 0xC0, 0x60, 0x30, 0x18, 0x00 }, // < { 0x00, 0x00, 0xFC, 0x00, 0x00, 0xFC, 0x00, 0x00 },...
  • Page 135 S1D13503 Programming Notes and Examples { 0x00, 0x00, 0xFC, 0x98, 0x30, 0x64, 0xFC, 0x00 }, // z { 0x1C, 0x30, 0x30, 0xE0, 0x30, 0x30, 0x1C, 0x00 }, // { { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00 }, // | { 0xE0, 0x30, 0x30, 0x1C, 0x30, 0x30, 0xE0, 0x00 }, // } { 0x76, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },...
  • Page 136 EPSON Video |= (color << 2); if (val & 0x02) Video |= (color << 1); if (val & 0x01) Video |= color; *pVideo++ = (unsigned char) Video; CheckBank(pVideo, &bank); pVideoFirstColumn += BytesPerScanLine; ++pVideoStart; // Point to next character pVideoFirstColumn = pVideoStart;...
  • Page 137 S1D13503 Programming Notes and Examples if (val & 0x04) Video |= (color << 4); if (val & 0x02) Video |= (color << 2); if (val & 0x01) Video |= color; *pVideo++ = (unsigned char) Video; CheckBank(pVideo, &bank); pVideoFirstColumn += BytesPerScanLine; pVideoStart += 2;...
  • Page 138 EPSON Video |= (color << 4); if (val & 0x04) Video |= color; *pVideo++ = (unsigned char) Video; CheckBank(pVideo, &bank); Video = 0; if (val & 0x02) Video |= (color << 4); if (val & 0x01) Video |= color; *pVideo++ = (unsigned char) Video;...
  • Page 139 S1D13503 Programming Notes and Examples break; //------------------------------------------------------------------------- // FUNCTION: SplitScreen() // DESCRIPTION: Show split screen. // INPUTS: None. // RETURN VALUE: None. //------------------------------------------------------------------------- void SplitScreen(void) static unsigned char _far *pVideoImage1; static unsigned char _far *pVideoImage2; static unsigned long ImageSize; static unsigned int OriginalLineCount; static unsigned int val;...
  • Page 140 EPSON // Calculate starting video memory location for image 2 by finding the // last location of image 1 ImageSize = (unsigned long) BytesPerScanLine * PanelY; // Because the image size is limited to a maximum of 320 x 240, and there // is 128K of video memory, there is enough memory available.
  • Page 141 S1D13503 Programming Notes and Examples // Scroll image 2 down for (val = MinLineCount; val < OriginalLineCount; val += 1) WriteRegister(0x0a, val & 0xff); // Total Display Line Count WriteRegister(0x0b, (val >> 8) & 0x03); // Total Disp Line Cnt/WF Count Delay(DELAY_SHORT);...
  • Page 142 EPSON Initialize(); SetDisplay(OFF); ClearLCDScreen(); switch (PanelGrayLevel) case 16: pitch = (unsigned int) (((VIRTUAL_X / 2) - BytesPerScanLine) / 2); BytesPerScanLine = (VIRTUAL_X / 2); break; case 256: pitch = (unsigned int) ((VIRTUAL_X - BytesPerScanLine) / 2); BytesPerScanLine = VIRTUAL_X; break;...
  • Page 143 S1D13503 Programming Notes and Examples ShowBorders(); // Move virtual display from (0, 0) to (MaxX, 0) MaxX = (unsigned int) (VIRTUAL_X - PanelX); MaxY = (unsigned int) (VIRTUAL_Y - PanelY); SetDisplay(ON); for (x = 0; x <= MaxX; ++x) SetStartAddress(x, 0); Delay(DELAY_SHORT);...
  • Page 144 EPSON val &= 0x7f; WriteRegister(1, val); // Step 2: Disable LCDE (turn off LCD power supply). For the S5U13503P00C, set LCDE bit to 0. val = ReadRegister(1); val &= 0xef; WriteRegister(1, val); // Step 2: Wait for LCD power supply to drop to zero volts For the S5U13503P00C, wait about a half second.

  • Page 145: Glossary

    S1D13503 Programming Notes and Examples LOSSARY 13503 The S1D13503 LCD controller chip. bank In reference to display memory banking, a bank is a 64K byte block of display mem- ory. Bank 0 represents the first 64K bytes of display memory, and bank 1 represents the second 64K bytes.
  • Page 146 EPSON S1D13503 R EGISTER UMMARY AUX[01] Mode Register 0: I/O address = 0001b, RW Gray Shade / LCD Data Memory DISP PANEL Mask XSCL LCDE RAMS Color Width Bit 0 Interface AUX[02] Line Byte Count Register (LSB): I/O address = 0010b, RW...
  • Page 148 UTILITIES Table of Contents 1 13503SHOW.EXE D ..................3-1 ISPLAY TILITY 2 13503VIRT.EXE D ..................3-3 ISPLAY TILITY 3 13503BIOS.COM U ......................3-5 TILITY 4 13503MODE.EXE D ..................3-7 ISPLAY TILITY 5 13503PD.EXE P ..................3-9 OWER TILITY 6 13503READ.EXE D .................3-11 IAGNOSTIC TILITY...

  • Page 149: 13503Show.exe D Isplay Tility

    S1D13503 by loading two images and vertically scrolling one image. Program Requirements Video Controller : S1D13503 : Up to 640 × 480 LCD Display Type BIOS : Seiko Epson 13503BIOS version 1.xx or later DOS Program : Yes DOS Version : 3.0 or greater Windows Program : No...
  • Page 150 EPSON Comments • 13503SHOW requires 13503BIOS.COM to be loaded prior to running. • Split screen viewing is limited on dual panels. The view port is fixed in place at the top left of the bottom LCD panel. Panning and scrolling is still possible within the screen 2 view port.

  • Page 151: 13503Virt.exe Display Utility

    Program Requirements Video Controller : S1D13503 : Up to 640 × 480 LCD Display Type BIOS : Seiko Epson 13503BIOS version 1.xx or later DOS Program : Yes DOS Version : 3.0 or greater Windows Program : No...
  • Page 152 EPSON S18A-B-002-01...

  • Page 153: 13503Bios.com U Tility

    13503BIOS.COM Utility 3 13503BIOS.COM U TILITY 13503BIOS is a Terminate and Stay Resident (TSR) program which replaces and/or supplements the PC video interrupt INT 10h. This program provides text, scroll, and cursor functionality when no VGA BIOS is present. Although the S1D13503 is not a VGA or EGA compatible controller, this program is supplied to give the user a familiar prompt.
  • Page 154 EPSON Comments • 13503BIOS can be used in conjunction with a Monochrome Display Adapter (mono) card. The standard DOS command MODE MONO will switch to the monochrome card and the DOS com- mand MODE CO80 will switch to the LCD panel.

  • Page 155: 13503Mode.exe D Isplay Tility

    Program Requirements Video Controller : S1D13503 : Up to 640 × 480 LCD Display Type BIOS : Seiko Epson 13503BIOS version 1.xx or later DOS Program : Yes DOS Version : 3.0 or greater Windows Program : No...
  • Page 156 EPSON Comment 13503MODE requires 13503BIOS.COM to be loaded prior to running. Program Message ERROR: This program requires 13503BIOS to be loaded! The program 13503BIOS.COM must be run before 13503MODE. Load 13503BIOS.COM and then re-run 13503MODE.EXE. S18A-B-004-01...

  • Page 157: 13503Pd.exe Power Down Utility

    Program Requirements Video Controller : S1D13503 : Up to 640 × 480 LCD Display Type BIOS : Seiko Epson 13503BIOS version 1.xx or later DOS Program : Yes DOS Version : 3.0 or greater Windows Program : No...
  • Page 158 EPSON Program Messages Power Down Mode xx is set. The power down mode xx has been set. This message may not be visible if the active display con- troller is the S1D13503. ERROR: Cannot set power mode xx! 13503PD.EXE cannot set the power down mode requested - either 13503BIOS.COM is not loaded or the power down mode number exceeds 2.

  • Page 159: 13503Read.exe D Iagnostic Utility

    13503BIOS loaded, it will try to interpret the BIOS settings. Program Requirements Video Controller : S1D13503 : Up to 640 × 480 LCD Display Type BIOS : Seiko Epson 13503BIOS.COM (optional) DOS Program : Yes DOS Version : 3.0 or greater Windows Program : No...
  • Page 160 EPSON Program Messages ERROR: 13503 registers not responding at port address [port]. 13503READ has not found an S1D13503 at the port address specified. Check the command line port setting for 13503BIOS and/or 13503READ to ensure it is correct and re-run the program.
  • Page 162 S5U13503P00C EVALUATION BOARD USER’S MANUAL Table of Contents 1 S5U13503P00C R 1.0 E ................4-1 VALUATION OARD 1.1 Features ............................4-1 ...................4-2 NSTALLATION AND ONFIGURATION ......................4-6 ECHNICAL ESCRIPTION 3.1 ISA Bus Support ..........................4-6 3.2 Non-ISA Bus Support ........................4-7 3.3 SRAM Support ..........................4-7 3.4 Monochrome LCD Support......................4-7 3.5 Color LCD Support ........................4-8 3.6 Power Save Modes ........................4-8...
  • Page 163 List of Figures Figure 1 S5U13503P00C Rev. 1.0 Schematic Diagram (1 of 7) ............4-11 Figure 2 S5U13503P00C Rev. 1.0 Schematic Diagram (2 of 7) ............4-12 Figure 3 S5U13503P00C Rev. 1.0 Schematic Diagram (3 of 7) ............4-13 Figure 4 S5U13503P00C Rev.

  • Page 164: S5U13503P00C Rev 1.0 Evaluation Board

    S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual 1 S5U13503P00C R 1.0 E VALUATION OARD This manual reflects the use of the S5U13503P00C Rev 1.0 evaluation board in conjunction with the S1D13503F00A LCD Controller. All appropriate components are surface-mount to reduce cost and minimize board space.

  • Page 165: Installation And Configuration

    EPSON NSTALLATION AND ONFIGURATION The S1D13503F00A uses the display memory data lines (VD[15:0]) as configuration inputs which are read on power-up. For the purpose of this design, most of these configuration inputs have been factory set and therefore are not configurable. An eight position DIP switch is provided for the selec- tion of the following: Table 2-1 Configuration DIP Switch Settings...
  • Page 166 S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual LCD Signal Connector Pinout Table 2-4 LCD Signal Connector J1 Pinout Color STN LCD Mono STN LCD 8-bit 8-bit S1D13503 Single Single Connector 16-bit 8-bit Pin Name 4-bit 8-bit 4-bit (Format 1 (Format 2 Pin No.
  • Page 167 EPSON CPU / BUS Interface Connector Pinouts Table 2-5 CPU/BUS Connector H1 Pinout Connector CPU/BUS Comments Pin No. Pin Name Connected to DB0 of the S1D13503 Connected to DB1 of the S1D13503 Connected to DB2 of the S1D13503 Connected to DB3 of the S1D13503...
  • Page 168 S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual Table 2-6 CPU/BUS Connector H2 Pinout Connector CPU/BUS Comments Pin No. Pin Name Connected to AB0 of the S1D13503 Connected to AB1 of the S1D13503 Connected to AB2 of the S1D13503 Connected to AB3 of the S1D13503 Connected to AB4 of the S1D13503 Connected to AB5 of the S1D13503 Connected to AB6 of the S1D13503...

  • Page 169: Technical Description

    EPSON ECHNICAL ESCRIPTION 3.1 ISA Bus Support This board directly supports the 8/16-bit ISA Bus with Indexed I/O via a standard AT edge connec- tor. Only those configuration resistors needed for ISA Bus support have been assembled, refer to “Hard-Wired Configuration Inputs” on page 2 for configuration details. External logic has been added to provide signals which the S1D13503F00A does not directly support.

  • Page 170: Non-Isa Bus Support

    S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual 3.2 Non-ISA Bus Support This evaluation board was specifically designed to support the standard 8/16-bit ISA bus. However, as the S1D13503F00A does support other bus interfaces, header strips have been provided contain- ing all necessary I/O pins. (See Table 2-1, “Configuration DIP Switch Settings,” on page 2, “Hard- Wired Configuration Inputs”...

  • Page 171: Color Lcd Support

    EPSON 3.5 Color LCD Support The S5U13503P00C directly supports 4/8/16-bit Dual and Single color LCD panels. All the neces- sary signals are provided on the 40-pin ribbon cable header. The interface signals are alternated with grounds on the cable to reduce cross talk and noise related problems.

  • Page 172: Crystal Support

    S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual 3.9 Crystal Support The input crystal frequency may be up to 25.0 MHz depending on the specific panel size and frame rate desired. Refer to Section 9.3 of the Hardware Functional Specification for further details. 3.10 Oscillator Support The input oscillator frequency used may be up to 25.0 MHz, depending on the specific panel size and frame rate desired.

  • Page 173: Appendix A Parts List4-10

    EPSON APPENDIX A P ARTS Item # Qty/Board Designation Part Value Description C11–C23 0.01µF 0.01µF, 1206 pckg C9 –C10 10µF 10µF / 25V Tantalum D-SIZE C7–C8 7pF, 1206 pckg (This Parts isn’t assembled) C2–C4 10µF / 63V Electrolytic / Radial (LXF63VB10RM5X11LL) C1, C5, C6 56µF/35V...

  • Page 174: Appendix B S5U13503P00C Rev. 1.0 Schematic Diagrams

    S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual APPENDIX B S5U13503P00C R . 1.0 S CHEMATIC IAGRAMS Figure 1 S5U13503P00C Rev. 1.0 Schematic Diagram (1 of 7) S18A-G-007-01 4-11...
  • Page 175 EPSON Figure 2 S5U13503P00C Rev. 1.0 Schematic Diagram (2 of 7) 4-12 S18A-G-007-01...
  • Page 176 S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual Figure 3 S5U13503P00C Rev. 1.0 Schematic Diagram (3 of 7) S18A-G-007-01 4-13...
  • Page 177 EPSON Figure 4 S5U13503P00C Rev. 1.0 Schematic Diagram (4 of 7) 4-14 S18A-G-007-01...
  • Page 178 S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual Figure 5 S5U13503P00C Rev. 1.0 Schematic Diagram (5 of 7) S18A-G-007-01 4-15...
  • Page 179 EPSON Figure 6 S5U13503P00C Rev. 1.0 Schematic Diagram (6 of 7) 4-16 S18A-G-007-01...
  • Page 180 S5U13503P00C Rev. 1.0 Evaluation Board User’s Manual Figure 7 S5U13503P00C Rev. 1.0 Schematic Diagram (7 of 7) S18A-G-007-01 4-17...
  • Page 181 EPSON THIS PAGE IS BLANK. 4-18 S18A-G-007-01...
  • Page 183 APPLICATION NOTES Table of Contents 1 ISA B ..................5-1 NTERFACE ONSIDERATIONS 1.1 Introduction............................5-1 Reference Material........................5-1 1.2 16-Bit ISA Bus Interface ........................5-2 PAL Equations ...........................5-2 Additional Discrete Logic Description ..................5-3 S1D13503 Default Setup ......................5-3 Configuration Options......................5-3 Register Setting........................5-3 1.3 8-Bit ISA Bus Interface ........................5-4 S1D13503 Default Setup ......................5-4 Configuration Options......................5-4 Register Setting........................5-4...
  • Page 184 List of Figures Figure 1-1 16-Bit ISA Bus Implementation .................... 5-2 Figure 1-2 8-Bit ISA Bus Implementation ....................5-4 Figure 2-1 MC68340 MPU Interface Block Diagram ................5-6 Figure 3-1 16-Bit Memory Configuration Example ................5-10 List of Tables Table 4-1 Total Power Consumption - 3V ..................

  • Page 185: Isa Bus Interface Considerations

    S1D13503 ISA Bus Interface Considerations 1 ISA B NTERFACE ONSIDERATIONS 1.1 Introduction The S1D13503 is a general purpose LCD controller capable of interfacing to a variety of micropro- cessors. In some cases this interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the S1D13503 and the ISA Bus both 8 and 16- bit implementations.

  • Page 186: 16-Bit Isa Bus Interface

    EPSON 1.2 16-Bit ISA Bus Interface For the purpose of the example shown below, the following conditions apply: 1. Indexed I/O with addresses 0310h and 0311h (see Configuration Options) 2. 128K bytes of display memory occupying $C and $D segments (see Configuration Options) Note: This memory configuration will conflict with a VGA card installed on the same bus, therefore either a serial terminal or monochrome display adapter is recommended as the primary console.

  • Page 187: Additional Discrete Logic Description

    S1D13503 ISA Bus Interface Considerations 3. With 128K bytes of display memory and A17 to A19 decoded internally to S1D13503; MEMCS# = !REFRESH Note: The MSBs of the address (A23:A20) need not be externally decoded if using SMEMW# and SMEMR# as they will only assert on addresses < 1MB. Additional Discrete Logic Description 1.

  • Page 188: 8-Bit Isa Bus Interface

    EPSON 1.3 8-Bit ISA Bus Interface For the purpose of the example shown below, the following conditions apply: 1. Indexed I/O with partial decoding, i.e. address lines A10 to A15 are not decoded for I/O cycles Note: Partial decoding is quite safe on most ISA Bus systems as I/O addresses above 03FFh are rarely used.

  • Page 189: Mc68340 Interface Considerations

    S1D13503 MC68340 Interface Considerations 2 MC68340 I NTERFACE ONSIDERATIONS 2.1 Introduction The S1D13503 is a general purpose LCD controller capable of interfacing to a variety of micropro- cessors. This interface is accomplished through the use of minimal external circuitry. This applica- tion note describes the interface between the S1D13503 and the 16-bit MC68340 microcontroller.

  • Page 190: Mc68340 Mpu Interface

    EPSON 2.2 MC68340 MPU Interface The following sections provide the necessary settings and equations to complete the interface between the S1D13503 and the MC68340 microcontroller. MC68340 S1D13503 MEMCS# SIZ0 IOCS# A0, A10–17 BHE# 10kΩ VD0–3, A0–19 AB0–19 VD13 D0–15 DB0–15 4.7kΩ...

  • Page 191: S1D13503 Default Setup

    S1D13503 MC68340 Interface Considerations S1D13503 Default Setup Configuration Options 1. VD15–VD13 = 001 memory decoding for locations 20000h–3FFFFh 2. VD12–VD4 = 000000xxx I/O decoding for locations 0000000000b–0000001111b 3. VD3 = 1 byte swap of high and low bytes 4. VD2 = 1 MC68K interface 5.

  • Page 192: Lcd Panel Options / Memory Requirements

    EPSON 3 LCD P ANEL PTIONS EMORY EQUIREMENTS 3.1 Introduction The S1D13503 is a highly configurable general purpose LCD controller. The LCD panel frame-rate, resolution, and number of colors / gray shades all determine the memory and input clock require- ments.

  • Page 193: Configuration Equations

    S1D13503 LCD Panel Options / Mamory Requirements 3.2 Configuration Equations This application note will follow one example through all the required calculations, for a complete description of all formula and associated parameters refer to the S1D13503 Hardware Functional Specification . Example 320 ×...

  • Page 194: Sram Access Time

    EPSON SRAM Access Time To support 256 color modes the S1D13503 must be configured to support a 16-bit data path into dis- play memory (SRAM). For 16-bit display memory interface the required SRAM access time must be; SRAM Access time ≤ 1/f - 40ns.

  • Page 195: Register Settings

    S1D13503 LCD Panel Options / Mamory Requirements Register Settings AUX[0] = 0000 0000 not in test mode AUX[1] = 1011 100x 8-bit single panel, 256 color, 16-bit display memory interface AUX[2] = 1001 1111 horizontal resolution = 320 ; 256 colors = 1 pixel per byte; 1 pixel per fetch AUX[3] = 0000 0110 not in power save modes...
  • Page 196 EPSON 4 S1D13503 P OWER ONSUMPTION 4.1 Conditions Table 4-1 Total Power Consumption - 3V Total Power Consumption Gray Shades / Test Condition Power Save Mode Colors Active Input Clock = 6MHz Black-and-White 5.4 mW 1.2 mW less than 300 µW LCD Panel Connected = 320 ×...

  • Page 197: S1D13503 Power Consumption

    S1D13503 Power Consumption S1D13503 Total Power Consumption - 3V Condition 1 - BW Condition 1 - 4 grays Condition 1 - 16 grays Condition 2 - 4 colors Condition 2 - 16 colors Condition 2 - 256 colors Condition 3 - BW Condition 3 - 4 colors Condition 4 - 4 colors ACTIVE...

  • Page 198: Table 8-2 Lcd Data Width

    EPSON 5 S1D13503 / SED1352 C OMPARISON The S1D13503 is pin compatible with, and includes all features of the SED1352. This allows an easy upgrade path for the system designer, both from the hardware and software aspect. The purpose of this document is to briefly describe the differences between these two controllers, for further details refer to the individual Hardware Functional Specifications.
  • Page 199 Telex: 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 Northeast EPSON TAIWAN TECHNOLOGY & TRADING LTD. 301 Edgewater Place, Suite 120 10F, No. 287, Nanking East Road, Sec. 3 Wakefield, MA 01880, U.S.A. Taipei Phone: +1-781-246-3600...
  • Page 200 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
  • Page 201 S1D13503 Series Technicl Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue October,1997 This manual was made with recycle papaer, Printed April, 2001 in Japan and printed using soy-based inks.

This manual is also suitable for:

S1d13503d00aS1d13503f00aS1d13503f01aS1d13503p00c

Table of Contents