Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 2 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 TECHNICAL MANUAL X26A-Q-001-04 Issue Date: 01/02/12...
Page 3 Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and sche- matics. • To borrow an evaluation board, please contact your local Seiko Epson Corp. sales repre- sentative. Chip Documentation • Technical manual includes Data Sheet, Application Notes, and Programmer’s Refer- ence.
Page 4 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 TECHNICAL MANUAL X26A-Q-001-04 Issue Date: 01/02/12...
Page 5 Epson Research and Development Page 5 Vancouver Design Center Table of Contents INTRODUCTION S1D13704 Embedded Memory Color LCD Controller Product Brief SPECIFICATION S1D13704 Hardware Functional Specification PROGRAMMER’S REFERENCE S1D13704 Programming Notes and Examples S1D13704 Register Summary UTILITIES 13704CFG.EXE File Configuration Program...
Page 6 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 TECHNICAL MANUAL X26A-Q-001-04 Issue Date: 01/02/12...
Page 7 The S1D13704 is a color/monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer. The high integration of the S1D13704 provides a low cost, low power, single chip solution to meet the require- ments of embedded markets such as Office Automation equipment, Mobile Communications devices, and Palm- size PCs where board size and battery life are major concerns.
Page 8 Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Ep- son/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
Page 9 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 10 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08...
Page 11: Table Of Contents
Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........9 Scope .
Page 12 Page 4 Epson Research and Development Vancouver Design Center 7.1.4 Motorola M68K #2 Interface Timing ......31 7.1.5...
Page 13 Table 13-4: Power Save Mode Function Summary ......85 Table 13-5: S1D13704 Internal Clock Requirements ......87...
Page 14: Vancouver Design Center
Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08...
Page 15: Vancouver Design Center
Epson Research and Development Page 7 Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram (SH-4 Bus)......12 Figure 3-2: Typical System Diagram (SH-3 Bus).
Page 16: Vancouver Design Center
Figure 11-8: 256-Level Color Mode Look-Up Table Architecture....78 Figure 12-1: Relationship Between The Screen Image and the Image Refreshed by S1D13704 ..79 Figure 12-2: Relationship Between The Screen Image and the Image Refreshed by S1D13704 .
Page 17: Introduction
The S1D13704 is a color / monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer. The high integration of the S1D13704 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices, and Hand-Held PCs where board size and battery life are major concerns.
Page 18: Features
Page 10 Epson Research and Development Vancouver Design Center 2 Features 2.1 Integrated Frame Buffer • Embedded 40K byte SRAM display buffer. 2.2 CPU Interface • Direct support of the following interfaces: Hitachi SH-3. Hitachi SH-4. Motorola M68K. MPU bus interface using WAIT# signal.
Page 19: Display Modes
Epson Research and Development Page 11 Vancouver Design Center 2.4 Display Modes • SwivelView™: direct 90° hardware rotation of display image for portrait mode display. • 1/2/4 bit-per-pixel (bpp), 2/4/16-level grayshade display. • 1/2/4/8 bit-per-pixel, 2/4/16/256-level color display. • Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 Look- Up-Table is used to map 1/2/4-bpp modes into these shades.
Page 20: Typical System Implementation Diagrams
Page 12 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Oscillator SH-4 CSn# A[15:0] AB[15:0] D[15:0] DB[15:0] FPDAT[7:0] D[7:0] FPSHIFT FPSHIFT WE1# WE1# S1D13704 8-bit FPFRAME FPFRAME RD/WR# RD/WR# FPLINE FPLINE Display DRDY WE0# WE0# RDY#...
Page 21: Figure 3-3: Typical System Diagram (M68K #1 Bus)
Epson Research and Development Page 13 Vancouver Design Center Oscillator MC68000 A[23:16] Decoder FC0, FC1, FC2 A[15:1] AB[15:1] D[15:0] DB[15:0] FPDAT[3:0] D[3:0] FPSHIFT FPSHIFT S1D13704 4-bit LDS# AB0# FPFRAME FPFRAME UDS# WE1# FPLINE FPLINE Display DRDY R/W# RD/WR# DTACK# WAIT#...
Page 22: Figure 3-5: Typical System Diagram (Generic #1 Bus)
Page 14 Epson Research and Development Vancouver Design Center Oscillator GENERIC #1 CSn# A[15:0] AB[15:0] D[15:0] DB[15:0] FPDAT[11:0] D[11:0] FPSHIFT FPSHIFT S1D13704 12-bit WE0# WE0# FPFRAME FPFRAME WE1# WE1# FPLINE FPLINE Display RD0# DRDY DRDY RD1# RD/WR# WAIT# WAIT# LCDPWR...
Page 23: Functional Block Diagram
Epson Research and Development Page 15 Vancouver Design Center 4 Functional Block Diagram 20k x 16-bit SRAM Memory Power Save Register Controller Clocks Generic MPU MC68K Host SH-3 Look-Up SH-4 Table Sequence Controller Bus Clock Memory Clock Pixel Clock Figure 4-1: System Block Diagram Showing Data Paths 4.1 Functional Block Descriptions...
Page 24: Look-Up Table
Page 16 Epson Research and Development Vancouver Design Center 4.1.4 Look-Up Table The Look-Up Table contains three 16x4 Look-Up Tables or palettes, one for each primary color. In monochrome mode only one of these Look-Up Tables is used. 4.1.5 LCD Interface The LCD Interface performs frame rate modulation for passive LCD panels.
Page 25: Pins
Epson Research and Development Page 17 Vancouver Design Center 5 Pins 5.1 Pinout Diagram 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COREVDD FPFRAME FPLINE FPDAT0 FPDAT1 FPDAT2...
Page 26: Pin Description
Page 18 Epson Research and Development Vancouver Design Center 5.2 Pin Description Key: Input Output Bi-Directional (Input/Output) Power pin CMOS level input CMOS level input with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V respectively) CMOS level Schmitt input CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
Page 27: Vancouver Design Center
See “Host Bus Interface Pin Mapping” for summary. This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs the RD/WR# signal. The S1D13704 needs this signal for early decode of the bus cycle. • For MC68K #1, this pin inputs the R/W# signal.
Page 28: Lcd Interface
Page 20 Epson Research and Development Vancouver Design Center RESET# Pin Names Type Pin # Cell Description State This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs the read signal (RD#). • For MC68K #1, this pin must be tied to IO V •...
Page 29: Clock Input
RESET# Pin Name Type Pin # Cell Description State These inputs are used to configure the S1D13704 - see 45, 46, 47, As set by “Summary of Configuration Options”. CNF[4:0] 48, 49 hardware Must be connected directly to IO V or V This pin has multiple functions - see REG[03h] bit 2.
Page 30: Summary Of Configuration Options
Page 22 Epson Research and Development Vancouver Design Center 5.3 Summary of Configuration Options Table 5-1: Summary of Power On/Reset Options Power On/Reset State Configuration CNF4 Active high (On) LCDPWR polarity Active low (On) LCDPWR polarity CNF3 Big Endian Little Endian...
Page 31: Lcd Interface Pin Mapping
Epson Research and Development Page 23 Vancouver Design Center 5.5 LCD Interface Pin Mapping Table 5-3: LCD Interface Pin Mapping Monochrome Passive Panel Color Passive Panel Color TFT/D-TFD S1D13704 8-bit 8-bit 4-bit 8-bit 4-bit Pin Name 8-bit Dual Single Single...
Page 32: C. Characteristics
Page 24 Epson Research and Development Vancouver Design Center 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Core V Supply Voltage - 0.3 to 4.6 IO V Supply Voltage - 0.3 to 6.0 Input Voltage - 0.3 to IO V + 0.5...
Page 33: Table 6-4: Output Specifications
Epson Research and Development Page 25 Vancouver Design Center Table 6-4: Output Specifications Symbol Parameter Condition Units Low Level Output Voltage Type 1 - TS1, CO1 = 3mA Type 2- TS2, CO2 = 6mA Type 3 - TS3, CO3 = 12mA...
Page 34: C. Characteristics
Figure 7-1: SH-4 Timing Note The SH-4 Wait State Control Register for the area in which the S1D13704 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK).
Page 35: Table 7-1: Sh-4 Timing
Epson Research and Development Page 27 Vancouver Design Center Table 7-1: SH-4 Timing Symbol Parameter Units Bus Clock frequency CKIO Bus Clock period CKIO CKIO Clock pulse width high Clock pulse width low A[15:0], RD/WR# setup to CKIO A[15:0], RD/WR# hold from CS#...
Page 36: Interface Timing
D[15:0] Hi-Z Hi-Z VALID (read) Figure 7-2: SH-3 Bus Timing Note The SH-3 Wait State Control Register for the area in which the S1D13704 resides must be set to a non-zero value. S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08...
Page 37: Table 7-2: Sh-3 Bus Timing
Epson Research and Development Page 29 Vancouver Design Center Table 7-2: SH-3 Bus Timing Symbol Parameter Units Bus Clock frequency CKIO Bus Clock period CKIO CKIO Clock pulse width high Clock pulse width low A[15:0], RD/WR# setup to CKIO A[15:0], RD/WR# hold from CS#...
Page 38: Motorola M68K #1 Interface Timing
Page 30 Epson Research and Development Vancouver Design Center 7.1.3 Motorola M68K #1 Interface Timing A[15:1] VALID R/W# UDS#, LDS# INVALID Hi-Z Hi-Z DTACK# D[15:0] Hi-Z Hi-Z (write VALID D[15:0] Hi-Z Hi-Z (read) VALID Figure 7-3: M68K #1 Bus Timing (MC68000)
Page 39: Motorola M68K #2 Interface Timing
Epson Research and Development Page 31 Vancouver Design Center 7.1.4 Motorola M68K #2 Interface Timing A[15:0] VALID SIZ0, SIZ1 R/W# Hi-Z Hi-Z DSACK1# D[31:16] Hi-Z Hi-Z VALID (write) Hi-Z D[31:16] Hi-Z VALID (read) Figure 7-4: M68K #2 Timing (MC68030) Table 7-4: M68K #2 Timing (MC68030)
Page 40: Generic #1 Interface Timing
Page 32 Epson Research and Development Vancouver Design Center 7.1.5 Generic #1 Interface Timing BCLK BCLK A[15:0] VALID WE0#,WE1# RD0#, RD1# D[15:0] Hi-Z VALID (write) D[15:0] Hi-Z Hi-Z VALID (read) Hi-Z Hi-Z WAIT# Figure 7-5: Generic #1 Timing Table 7-5: Generic #1 Timing...
Page 41: Generic #2 Interface Timing
Epson Research and Development Page 33 Vancouver Design Center 7.1.6 Generic #2 Interface Timing BCLK BCLK A[15:0] VALID BHE# WE#,RD# Hi-Z VALID D[15:0] (write) Hi-Z Hi-Z VALID D[15:0] (read) Hi-Z Hi-Z WAIT# Figure 7-6: Generic #2 Timing Table 7-6: Generic #2 Timing...
Page 42: Clock Input Requirements
Page 34 Epson Research and Development Vancouver Design Center 7.2 Clock Input Requirements Clock Input Waveform V IL T CLKI Figure 7-7: Clock Input Requirements Table 7-7: Clock Input Requirements Symbol Parameter Units Input Clock Frequency (CLKI) CLKI Input Clock period (CLKI)
Page 43: Display Interface
Epson Research and Development Page 35 Vancouver Design Center 7.3 Display Interface 7.3.1 Power On/Reset Timing RESET# REG[03h] bits [1:0] LCDPWR (CNF4 = 1) LCDPWR (CNF4 = 0) FPLINE ACTIVE FPSHIFT FPDAT FPFRAME DRDY Figure 7-8: LCD Panel Power On/Reset Timing...
Page 44: Power Down/Up Timing
Page 36 Epson Research and Development Vancouver Design Center 7.3.2 Power Down/Up Timing LCDPWR Override (REG[03h] bit 3) HW Power Save Software Power Save REG[03h] bits [1:0] FP Signals Active Inactive Active Inactive Active LCDPWR Active Inactive Active Inactive Active...
Page 45: Single Monochrome 4-Bit Panel Timing
Epson Research and Development Page 37 Vancouver Design Center 7.3.3 Single Monochrome 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-317 FPDAT6 1-318 FPDAT5 1-319...
Page 46: Figure 7-11: Single Monochrome 4-Bit Panel A.c. Timing
Page 38 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse DRDY (MOD) Data Timing Line Pulse Shift Pulse FPDAT[7:4] Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1 Figure 7-11: Single Monochrome 4-Bit Panel A.C. Timing...
Page 47: Single Monochrome 8-Bit Panel Timing
Epson Research and Development Page 39 Vancouver Design Center 7.3.4 Single Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-633 FPDAT6 1-10 1-634 FPDAT5...
Page 48: Figure 7-13: Single Monochrome 8-Bit Panel A.c. Timing
Page 40 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse Data Timing Line Pulse Shift Pulse FPDAT[7:0] Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1 Figure 7-13: Single Monochrome 8-Bit Panel A.C. Timing...
Page 49: Single Color 4-Bit Panel Timing
Epson Research and Development Page 41 Vancouver Design Center 7.3.5 Single Color 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-R1 1-G2 1-B3 1-B319 FPDAT6...
Page 50: Figure 7-15: Single Color 4-Bit Panel A.c. Timing
Page 42 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse DRDY (MOD) Data Timing Line Pulse Shift Pulse FPDAT[7:4] Figure 7-15: Single Color 4-Bit Panel A.C. Timing Symbol Parameter Units Frame Pulse setup to Line Pulse falling edge...
Page 51: Single Color 8-Bit Panel Timing (Format 1)
Epson Research and Development Page 43 Vancouver Design Center 7.3.6 Single Color 8-Bit Panel Timing (Format 1) VNDP FPFRAME FPLINE FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE FPSHIFT HNDP FPSHIFT 2 FPDAT7 1-R1 1-G1 1-G6 1-B6 1-B11...
Page 52: Figure 7-17: Single Color 8-Bit Panel A.c. Timing (Format 1)
Page 44 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse Data Timing Line Pulse Shift Pulse 2 Shift Pulse t12 t13 t12 t13 FPDAT[7:0] Figure 7-17: Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol...
Page 53: Single Color 8-Bit Panel Timing (Format 2)
Epson Research and Development Page 45 Vancouver Design Center 7.3.7 Single Color 8-Bit Panel Timing (Format 2) VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-R1 1-B3 1-G6...
Page 54: Figure 7-19: Single Color 8-Bit Panel A.c. Timing (Format 2)
Page 46 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse DRDY (MOD) Data Timing Line Pulse Shift Pulse FPDAT[7:0] Figure 7-19: Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol Parameter Units Frame Pulse setup to Line Pulse falling edge...
Page 55: Dual Monochrome 8-Bit Panel Timing
Epson Research and Development Page 47 Vancouver Design Center 7.3.8 Dual Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE DRDY (MOD)
Page 56: Figure 7-21: Dual Monochrome 8-Bit Panel A.c. Timing
Page 48 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse DRDY (MOD) Data Timing Line Pulse Shift Pulse FPDAT[7:0] Figure 7-21: Dual Monochrome 8-Bit Panel A.C. Timing Symbol Parameter Units Frame Pulse setup to Line Pulse falling edge...
Page 57: Dual Color 8-Bit Panel Timing
Epson Research and Development Page 49 Vancouver Design Center 7.3.9 Dual Color 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE 1/241 LINE 2/242 LINE 239/479 LINE 240/480 LINE 1/241 FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-G2 1-G6 1-B7...
Page 58: Figure 7-23: Dual Color 8-Bit Panel A.c. Timing
Page 50 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse DRDY (MOD) Data Timing Line Pulse Shift Pulse FPDAT[7:0] Figure 7-23: Dual Color 8-Bit Panel A.C. Timing Symbol Parameter Units Frame Pulse setup to Line Pulse falling edge...
Page 59: 9/12-Bit Tft/D-Tfd Panel Timing
Epson Research and Development Page 51 Vancouver Design Center 7.3.10 9/12-Bit TFT/D-TFD Panel Timing VNDP VNDP FPFRAME FPLINE FPDAT[11:0] LINE480 LINE1 LINE480 DRDY FPLINE HNDP HNDP FPSHIFT DRDY FPDAT[9] 1-640 FPDAT[2:0] FPDAT[10] 1-640 FPDAT[4:3] 1-640 FPDAT[11] FPDAT[8:6] Note: DRDY is used to indicate the first pixel...
Page 60: Figure 7-25: Tft/D-Tfd A.c. Timing
Page 52 Epson Research and Development Vancouver Design Center Frame Pulse Line Pulse Line Pulse DRDY Shift Pulse FPDAT[11:0] Note: DRDY is used to indicate the first pixel Figure 7-25: TFT/D-TFD A.C. Timing S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08...
Page 61 Epson Research and Development Page 53 Vancouver Design Center Symbol Parameter Units Shift Pulse period (note 1) Shift Pulse pulse width high Shift Pulse pulse width low Data setup to Shift Pulse falling edge Data hold from Shift Pulse falling edge...
Page 62: Registers
Vancouver Design Center 8 Registers 8.1 Register Mapping The S1D13704 registers are located in the upper 32 bytes of the 64K byte S1D13704 address range. The registers are accessible when CS# = 0 and AB[15:0] are in the range FFE0h through FFFFh.
Page 63: Table 8-1: Panel Data Format
Epson Research and Development Page 55 Vancouver Design Center bit 4 FPLINE Polarity This bit controls the polarity of FPLINE in TFT/D-TFD mode (no effect in passive panel mode). When this bit = 0, FPLINE is active low. When this bit = 1, FPLINE is active high.
Page 64: Table 8-2: Gray Shade/Color Mode Selection
Page 56 Epson Research and Development Vancouver Design Center REG[02h] Mode Register 1 Address = FFE2h Read/Write. Input Clock Hardware Bit-Per-Pixel Bit-Per-Pixel High Frame Software divide Display Blank Video Invert Bit 1 Bit 0 Performance Repeat Video Invert (CLKI/2) Enable...
Page 65: Table 8-4: Inverse Video Mode Select Options
Epson Research and Development Page 57 Vancouver Design Center bit 4 Input Clock Divide When this bit = 0, the operating clock(CLK) is same as the input clock (CLKI). When this bit = 1, CLK = CLKI/2. In landscape mode PCLK=CLK and MCLK is selected as per Table 8-3: “High Perfor- mance Selection”.
Page 66: Table 8-5: Hardware Power Save/Gpio0 Operation
Page 58 Epson Research and Development Vancouver Design Center REG[03h] Mode Register 2 Address = FFE3h Read/Write Hardware Software Software Look-Up LCDPWR Power Save Power Save Power Save Table Bypass Override Enable Bit 1 Bit 0 bit 7 Look-Up Table Bypass When the Look-Up Table Bypass bit = 0, the Green Look-Up Table is used for display data output in gray shade modes.
Page 67 Epson Research and Development Page 59 Vancouver Design Center Refer to Power Save Modes on page 84 for a complete description. REG[04h] Horizontal Panel Size Register Address = FFE4h Read/Write Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Panel Size Bit...
Page 68 Page 60 Epson Research and Development Vancouver Design Center REG[07h] FPLINE Start Position Address = FFE7h Read/Write FPLINE Start FPLINE Start FPLINE Start FPLINE Start FPLINE Start Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0...
Page 69 Epson Research and Development Page 61 Vancouver Design Center REG[0Ah] Vertical Non-Display Period Address = FFEAh Read/Write Vertical Non- Vertical Non- Vertical Non- Vertical Non- Vertical Non- Vertical Non- Vertical Non- Display Display Display Display Display Display Display Status Period Bit 5...
Page 70 Page 62 Epson Research and Development Vancouver Design Center REG[0Fh] Screen 2 Start Address Register (LSB) Address = FFEFh Read/Write Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start...
Page 71 Screen 1 Vertical Size Bits [9:0] REG[13h] bits 7-0 This register is used to implement the Split Screen feature of the S1D13704. These bits determine the height (in lines) of Screen 1. On reset this register is set to 0h.
Page 72: Figure 8-1: Screen-Register Relationship, Split Screen
Page 64 Epson Research and Development Vancouver Design Center (REG[0Dh], REG[0Ch]) Words Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) + × (8(REG[04h]+1) BPP/16)) Line 0 Last Pixel Address + REG[12h] Words Words Line 0 Line 1 Image 1 ((REG[06h], REG[05])+1) Lines...
Page 73: Table 8-7: Look-Up Table Access
Bit 1 Bit 0 The S1D13704 has three 16-position, 4-bit wide Look-Up Tables, one each for red, green, and blue. Refer to “Look-Up Table Architecture” for details. This register selects which Look-Up Table position is read/write accessible through the Look-Up Table Data Register (REG[17h]).
Page 74 Page 66 Epson Research and Development Vancouver Design Center REG[16h] Look-Up Table Bank Select Register Address = FFF6h Read/Write Red Bank Red Bank Green Bank Green Bank Blue Bank Blue Bank Select Select Select Select Select Select Bit 1 Bit 0...
Page 75 Epson Research and Development Page 67 Vancouver Design Center REG[17h] Look-Up Table Data Register Address = FFF7h Read/Write Look-Up Look-Up Look-Up Look-Up Table Data Table Data Table Data Table Data Bit 3 Bit 2 Bit 1 Bit 0 bits 3-0 Look-Up Table Data Bits [3:0] This register is used to read/write the RGB Look-Up Tables.
Page 76: Table 8-8: Selection Of Swivelview Mode
Page 68 Epson Research and Development Vancouver Design Center REG[1Ah] Scratch Pad Register Address = FFFAh Read/Write Scratch bit 7 Scratch bit 6 Scratch bit 5 Scratch bit 4 Scratch bit 3 Scratch bit 2 Scratch bit 1 Scratch bit 0...
Page 77: Table 8-9: Selection Of Pclk And Mclk In Swivelview Mode
REG[1Eh] and REG[1Fh] REG[1Eh] and REG[1Fh] are reserved for factory S1D13704 testing and should not be written. Any value written to these registers may result in damage to the S1D13704 and/or any panel connected to the S1D13704. Hardware Functional Specification...
Page 78: Frame Rate Calculation
Page 70 Epson Research and Development Vancouver Design Center 9 Frame Rate Calculation The following formulae are used to calculate the display frame rate. TFT/D-TFD and Passive Single-Panel modes PCLK FrameRate ---------------------------------------------------------------------------------------- - × HNDP VNDP Where: f = PClk frequency (Hz)
Page 79: Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization
Epson Research and Development Page 71 Vancouver Design Center 10 Display Data Formats 1-bpp: bit 7 bit 0 Byte 0 = (A Panel Display Host Address Display Memory 2-bpp: bit 7 bit 0 Byte 0 Byte 1 = (A Panel Display...
Page 80: Table 11-1: Look-Up Table Configurations
Page 72 Epson Research and Development Vancouver Design Center 11 Look-Up Table Architecture Table 11-1: Look-Up Table Configurations Display Mode 4-bit wide Look-Up Table GREEN BLUE 2-level gray 4 banks of 2 4-level gray 4 banks of 4 16-level gray...
Page 81: Figure 11-2: 4-Level Gray-Shade Mode Look-Up Table Architecture
Epson Research and Development Page 73 Vancouver Design Center 4-Level Gray Shade Mode 4 Gray Data Format: Green Look-Up Table A0 B0 A1 B1 A2 B2 A3 B3 See Section 10 Bank 0 2-bit pixel data Bank 1 Bank 4-bit display data output...
Page 82: Figure 11-4: Look-Up Table Bypass Mode Architecture
Note In 1 bit-per-pixel display mode, Look-Up Table Bypass mode will turn off the FRM circuitry and place the S1D13704 in Black-and-White mode. In 2 bit-per-pixel mode the Display Data Output values are 0, 5, A, and F (in hex).
Page 83: Figure 11-5: 2-Level Color Look-Up Table Architecture
Epson Research and Development Page 75 Vancouver Design Center 11.2 Color Display Modes 2-Level Color Mode 2 Color Data Format: Red Look-Up Table 1-bit pixel data A0 A1 A2 A3 A4 A5 A6 A7 See Section 10 Bank 4-bit ‘Red’ display data output...
Page 84: Figure 11-6: 4-Level Color Mode Look-Up Table Architecture
Page 76 Epson Research and Development Vancouver Design Center 4-Level Color Mode 4 Color Data Format: Red Look-Up Table Bank 0 A0 B0 A1 B1 A2 B2 A3 B3 2-bit pixel data See Section 10 Bank 1 Bank 4-bit ‘Red’ display data output...
Page 85: Figure 11-7: 16-Level Color Mode Look-Up Table Architecture
Epson Research and Development Page 77 Vancouver Design Center 16-Level Color Mode 16 Color Data Format: Red Look-Up Table 16x4 A0 B0 C0 D0 A1 B1 C1 D1 See Section 10 4-bit pixel data 4-bit ‘Red’ display data output Green Look-Up Table 16x4 4-bit ‘Green’...
Page 86: Figure 11-8: 256-Level Color Mode Look-Up Table Architecture
Page 78 Epson Research and Development Vancouver Design Center 256-Level Color Mode 256 Color Data Format: Red Look-Up Table Bank 0 R2 R1 R0 G2 G1 G0 B1 B0 See Section 10 3-bit pixel data Bank Select Bank 1 Logic...
Page 87: Figure 12-1: Relationship Between The Screen Image And The Image Refreshed By S1D13704
Many of todays applications use the LCD panel in a portrait orientation. In this case it becomes necessary to “rotate” the displayed image. This rotation can be done by software at the expense of performance or, as with the S1D13704, it can be done by hardware with no CPU penalty.
Page 88: How To Set Up Default Swivelview Mode
Page 80 Epson Research and Development Vancouver Design Center 12.1.1 How to Set Up Default SwivelView Mode The following describes the register settings needed to set up Default SwivelView Mode for a 240x320x4 bpp image: • Select Default SwivelView Mode: REG[1Bh] bit 7 = 1 and bit 6 = 0 •...
Page 89: Figure 12-2: Relationship Between The Screen Image And The Image Refreshed By S1D13704
The following figure shows how the programmer sees a 240x160 image and how the image is being displayed. The application image is written to the S1D13704 in the following sense: A–B–C–D. The display is refreshed by the S1D13704 in the following sense: B-D- A-C.
Page 90: How To Set Up Alternate Swivelview Mode
Page 82 Epson Research and Development Vancouver Design Center 12.2.1 How to Set Up Alternate SwivelView Mode The following describes the register settings needed to set up Alternate SwivelView Mode for a 160x240x8 bpp image. • Select Alternate SwivelView Mode: REG[1Bh] bit 7 = 1 and bit 6 = 1 •...
Page 91: Table 12-1: Default And Alternate Swivelview Mode Comparison
Epson Research and Development Page 83 Vancouver Design Center 12.3 Comparison Between Default and Alternate SwivelView Modes Table 12-1: Default and Alternate SwivelView Mode Comparison Item Default SwivelView Mode Alternate SwivelView Mode The width of the rotated image must be a power of 2.
Page 92: Table 13-1: Power Save Mode Selection
Epson Research and Development Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13704 to accommodate the need for power reduction in the hand-held devices market. These modes are enabled as follows: Table 13-1: Power Save Mode Selection...
Page 93: Table 13-4: Power Save Mode Function Summary
Epson Research and Development Page 85 Vancouver Design Center 13.3 Power Save Mode Function Summary Table 13-4: Power Save Mode Function Summary Hardware Software Normal Power Save Power Save IO Access Possible? Memory Access Possible? Sequence Controller Running? Display Active?
Page 94: Figure 13-1: Panel On/Off Sequence
Page 86 Epson Research and Development Vancouver Design Center RESET# Software Power Save REG[03h] bits [1:0] Hardware Power Save LCDPWR Power Save Mode (CNF4 = Low) LCDPWR (CNF4 = Hi) Panel Interface Output Signals (except LCDPWR) 0 frame 127 frames...
Page 95: Table 13-5: S1D13704 Internal Clock Requirements
Epson Research and Development Page 87 Vancouver Design Center 13.6 Clock Requirements The following table shows what clock is required for which function in the S1D13704. Table 13-5: S1D13704 Internal Clock Requirements Function BCLK CLKI Is required during register accesses. BCLK...
Page 96: Figure 14-1: Mechanical Drawing Qfp14
Page 88 Epson Research and Development Vancouver Design Center 14 Mechanical Data QFP14 - 80 pin Unit: mm ± 0.4 14.0 ± 0.1 12.0 Index + 0.1 0.18 - 0.05 0~10° ± 0.2 Figure 14-1: Mechanical Drawing QFP14 S1D13704 Hardware Functional Specification...
Page 97 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 98 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Programming Notes and Examples X26A-G-002-03 Issue Date: 01/02/12...
Page 99 Examples ....... . 42 Identifying the S1D13704 ....... . 46 Hardware Abstraction Layer (HAL) .
Page 100 10.1 Introduction ....... . 61 10.1.1 Sample code using the S1D13704 HAL API ..... 61 10.1.2 Sample code without using the S1D13704 HAL API .
Page 101 List of Tables Table 2-1: S1D13704 Initialization Sequence ......8 Table 4-1: 2 Bpp Banking Scheme ........16 Table 4-2: 4 Bpp Banking Scheme .
Page 102 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Programming Notes and Examples X26A-G-002-03 Issue Date: 01/02/12...
Page 103: Introduction
Vancouver Design Center 1 Introduction This guide describes how to program various features of the S1D13704 Embedded Memory Color LCD controller. The demonstrations include descriptions of how to calculate register values and explanations of how or why you might want to do certain procedures.
Page 104: Initialization
This example writes to all the control registers. In practice, it may be possible to write to only a subset of the registers. When the S1D13704 is first powered up all registers, unless noted otherwise in the specification, are set to zero. This example programs these registers to zero to establish a known state.
Page 105: Frame Rate Calculation
These registers are reserved and should not be written to. 2.1 Frame Rate Calculation The system the S1D13704 is being configured for dictates certain physical constraints such as the width and height of the panel and the video system input clock.
Page 106 Page 10 Epson Research and Development Vancouver Design Center This routine first performs a formula rearrangement so that HNDP or VNDP can be solved for. Start with VNDP set to a small value. Loop increasing VNDP and solving the equation for HNDP until satisfactory HNDP and VNDP values are found.
Page 107: Memory Models
Vancouver Design Center 3 Memory Models The S1D13704 is capable of operating at four different color depths. The data format for each color depth is packed pixel. S1D13704 packed pixel modes can range from one byte containing eight adjacent pixels (1-bpp) to one byte containing just one pixel (8-bpp).
Page 108: Bit-Per-Pixel (4 Colors/Gray Shades)
Page 12 Epson Research and Development Vancouver Design Center 3.1.2 2 Bit-Per-Pixel (4 Colors/Gray Shades) 2-bit pixels support four color/gray shades. In this memory format each byte of display buffer contains four adjacent pixels. Setting or resetting any pixel requires reading the entire byte, masking out the appropriate bits and, if necessary, setting bits to "1".
Page 109: Eight Bit-Per-Pixel (256 Colors)
Epson Research and Development Page 13 Vancouver Design Center 3.1.4 Eight Bit-Per-Pixel (256 Colors) In eight bit-per-pixel mode one byte of display buffer represents one pixel on the display. At this color depth the read-modify-write cycles, required by the lessor pixel depths, are eliminated.
Page 110: Look-Up Table (Lut)
LUT registers, recommendations for the color and monochrome LUT values, and additional programming considerations for the LUT. The S1D13704 Look-Up Table consists of sixteen 4-bit wide entries for each of red, green and blue. The Look-Up Table is controlled by three registers. REG[15h] forms the index into the table.
Page 111 Epson Research and Development Page 15 Vancouver Design Center Look-Up Table Address The Look-Up Table (LUT) consists of 16 indexed entries each consisting three 4-bit elements (red, green, blue). The LUT Address bits select which of the 16 entries is accessed.
Page 112 Page 16 Epson Research and Development Vancouver Design Center At 2-bpp, sixteen Look-Up Table addresses are used. The Look-Up Table is a now arranged into four banks of four colors each. As with 1-bpp, the bank select bits determine the initial offset into the Look-Up Table.
Page 113 Epson Research and Development Page 17 Vancouver Design Center At 4-bpp the pixel data is a direct index to the color to be displayed. At this color depth the Look-Up Table Bank Select bits have no effect on the display colors. For instance: If the data was 7Bh then the first pixel color would be from the RGB values of the 8th Look-Up Table address.
Page 114 Page 18 Epson Research and Development Vancouver Design Center At 8-bpp the lookup scheme gets a little more complicated. Each byte of display data contains 3 bits of red lookup, 3 bits of green lookup and 2 bits of blue lookup. The 16 addresses of the Look-Up Table are divided into 2 eight-element banks for the red and green components and 4 four-element banks for the blue component.
Page 115: Look-Up Table (Lut) Organization
Epson Research and Development Page 19 Vancouver Design Center REG[17h] Look-Up Table Data Register Read/Write LUT Data LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 Bit 0 LUT Data This register is where the 4-bit red/green/blue data value is written/read. With each successive read or write the internal RGB selector is incremented.
Page 116 Color Modes 1 Bpp Color When the S1D13704 is configured for 1 bit-per-pixel color mode, only the first two colors from the active bank are displayed. The two entries can be set to any color but are typically set to black and white.
Page 117 Vancouver Design Center 4 Bpp Color When the S1D13704 is configured for 4 bit-per-pixel operation all sixteen Look-Up Table entries are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT.
Page 118 The S1D13704 LUT has four bits (16 levels) of intensity control per primary color while a standard VGA RAMDAC has six bits (64 levels). This four to one difference has to be considered when attempting to match colors between a VGA RAMDAC and the S1D13704 LUT.
Page 119 Epson Research and Development Page 23 Vancouver Design Center Gray Shade Modes 1 Bpp Gray Shade (Black-and-White) In 1 bpp gray shade mode only the first two entries of the green LUT are used. All other LUT entries are unused.
Page 120 Page 24 Epson Research and Development Vancouver Design Center 4 Bpp Gray Shade The 4 bpp gray shade mode uses all 16 LUT elements. Table 4-11: Suggested LUT Values for 4 Bpp Gray Shade Index Green Blue Normally unused entries...
Page 121: Advanced Techniques
Epson Research and Development Page 25 Vancouver Design Center 5 Advanced Techniques This section contains information on the following: • virtual display • panning and scrolling • split screen display 5.1 Virtual Display Virtual display refers to the situation where the image to be viewed is larger than the physical display.
Page 122: Registers
Page 26 Epson Research and Development Vancouver Design Center 5.1.1 Registers REG[12h] Memory Address Offset Register Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Offset Offset Offset Offset Offset Offset Offset...
Page 123 The start address registers in the S1D13704 are an offset to the first word to be displayed in the top left corner of every frame.
Page 124: Registers
Page 28 Epson Research and Development Vancouver Design Center 5.2.1 Registers REG[0Ch] Screen 1 Display Start Address 0 (LSB) Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5...
Page 125 Epson Research and Development Page 29 Vancouver Design Center Panning to the right. StartWord = GetStartAddress(); StartWord ++; SetStartAddress(StartWord); Panning to the left. StartWord = GetStartAddress(); StartWord --; if (StartWord < 0) StartWord = 0; SetStartAddress(StartWord); Example 4: Scrolling (Up and Down) To scroll down, increase the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line.
Page 126: Split Screen
The status area updates far less often than the main play area. The Split Screen feature of the S1D13704 allows a programmer to setup a display for such an application. The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 199 and image 2 displaying from scan line 200 to scan line 239.
Page 127: Registers
Epson Research and Development Page 31 Vancouver Design Center 5.3.1 Registers The other registers required for split screen operations, REG[0Ch] through REG[0Dh] (Screen 1 Start Word Address) and REG[0Fh] through REG[10h] (Screen 2 Start Word Address) are described in Section 5.2.1 on page 28.
Page 128: Examples
Page 32 Epson Research and Development Vancouver Design Center REG[0Fh] Screen 2 Display Start Address 0 (LSB) Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit...
Page 129 Epson Research and Development Page 33 Vancouver Design Center 3. Calculate the Screen 2 Start Word Address register values. Screen 2 display data is coming from the very beginning of the display buffer. All there is to do here is ensure that both the LSB and MSB of the Screen 2 Start Word Address registers are set to zero.
Page 130: Lcd Power Sequencing And Power Save Modes
LCD. The time intervals vary depending on the power supply design. One frame after a power save mode has been enabled the S1D13704 disables LCD power. One hundred and twenty seven frames later the LCD logic signals are disabled. There may be situations where the internal time delay is insufficient to discharge the LCD power supply before the LCD signals are shut down.
Page 131: Lcd Enable/Disable
The following is the recommended sequence for manually powering-down an LCD panel. These steps would be used if power supply timing requirements were larger than the timings built into the S1D13704 power disable sequence. 1. Set REG[03h] bit 3, LCDPWR Override, to "1" (disables LCD Power).
Page 132: Swivelview
Many of todays applications use the LCD panel in a portrait orientation. In this case it becomes necessary to “rotate” the displayed image. This rotation can be done by software at the expense of performance or, as with the S1D13704, it can be done by hardware with no performance penalty.
Page 133: Alternate Swivelview Mode
The following figures show how the programmer sees a 240x320 image and how the image is displayed. The application image is written to the S1D13704 in the following sense: A–B–C–D. The display is refreshed by the S1D13704 in the following sense: B-D-A-C.
Page 134 SwivelView window display start address image seen by programmer image refreshed by S1D13704 = image in display buffer Figure 7-2: Relationship Between The Screen Image and the Image Refreshed by S1D13704 S1D13704 Programming Notes and Examples X26A-G-002-03 Issue Date: 01/02/12...
Page 135: Registers
The SwivelView mode register contains several items for SwivelView mode support. The first is the SwivelView Mode Enable bit. When this bit is “0” the S1D13704 is in landscape mode and the remainder of the settings in this register as well as the Line Byte Count in REG[1Ch] are ignored.
Page 136 SwivelView mode due to a lack of memory may now be used. Clocking for the S1D13704 works as follows: An external clock source supplies CLKI, the input clock. CLKI is routed through the Input Clock Divide from Mode Register 1 (REG[02h] bit 4) and is either divided by two or passed on.
Page 137: Limitations
Page 41 Vancouver Design Center 7.5 Limitations The only limitation to using SwivelView mode on the S1D13704 is that split screen operation is not supported. A comparison of the two SwivelView modes is as follows: Table 7-1: Default and Alternate SwivelView Mode Comparison...
Page 138: Examples
Page 42 Epson Research and Development Vancouver Design Center 7.6 Examples Example 6: Enable default SwivelView mode for a 320x240 panel at 4 bpp. Before switching to SwivelView mode from landscape mode, display memory should be cleared to make the user perceived transition smoother. Images in display memory are not rotated automatically by hardware and the garbled image would be visible for a short period of time if video memory is not cleared.
Page 139 Note These examples don’t use the Pixel Clock Select bits. The ability to divide the PCLK value down further than the default values was added to the S1D13704 to support SwivelView mode on very small panels. The Pixel Clock value has changed so we must calculate horizontal and vertical non-display times to reach the desired frame rate.
Page 140 Page 44 Epson Research and Development Vancouver Design Center Plugging the values into the frame rate calculations yields: PCLK FrameRate ---------------------------------------------------------------------------------------- - × HNDP VNDP 16 000 000 ----------------------------- - FrameRate ------------------------------------------------------- 80.69 × For this example the Horizontal Non-Display register [REG[08h]) needs to be set to 07h and the Vertical Non-Display register (REG[0Ah]) needs to be set to 03h.
Page 141 Epson Research and Development Page 45 Vancouver Design Center Example 8: Pan the above SwivelView mode image to the right by 4 pixels then scroll it up by 6 pixels. To pan by four pixels the start address needs to be advanced.
Page 142: Identifying The S1D13704
It may be important for a program to identify between products at run time. Identification of the S1D13704 can be performed any time after the system has been powered up by reading REG[00h], the Revision Code register. The six most significant bits form the product identification code and the two least significant bits form the product revision.
Page 143: Hardware Abstraction Layer (Hal)
9 Hardware Abstraction Layer (HAL ) 9.1 Introduction The HAL is a processor independent programming library provided by Epson with support for several different computing platforms. The HAL was developed to aid implementation of internal test programs and provides an easy, consistent method of programming S1D1350x, S1D1370x, and S1D1380x products on different processor platforms.
Page 144 Vancouver Design Center seSetInit(int DevID) Description: Configures the S1D13704 for operation. This function sets all the S1D13704 control registers to their default values. Initialization of the S1D13704 was made a stand-alone step to accommodate those programs (e.g. 13704PLAY.EXE) which needed the ability to start and examine the system before changing register contents.
Page 145: Miscellaneous Hal Support
Functions in this group do not fit into any specific category of support. They provide a miscellaneous range of support for working with the S1D13704 int seGetId(int DevID, int * pId) Description: Reads the S1D13704 revision code register to determine the chip product and revisions. The interpreted value is returned in pID. Parameters: DevID - registered device ID - pointer to an integer which will receive the controller ID.
Page 146 2) the combination of width, height and color depth may require more memory than is available on the S1D13704. int seGetBitsPerPixel(int DevID, int * pBitsPerPixel) Description: This function reads the S1D13704 registers to determine the current color depth and returns the result in pBitsPerPixel. Parameters: DevID - registered device ID pBitsPerPixel - pointer to an integer to receive current color depth.
Page 147 The S1D13704 registers must be initialized for this function to work correctly. On the PC platform this is simply a call to the C timing functions and is therefore independent of the register settings.
Page 148: Advanced Hal Functions
DevID, BOOL OnOff) Description: This function call enables or disable the high performance bit of the S1D13704. When high performance is enabled then MClk equals PClk for all video display resolutions. In the high performance state CPU to video memory performance is improved at the cost of higher power consumption.
Page 149 The smallest surface screen 1 can display is one line. This is due to the way the S1D13704 operates. Setting Screen 1 Vertical Size to zero results in one line of screen 1 being displayed. The remainder of the display will be screen 2 image.
Page 150 Page 54 Epson Research and Development Vancouver Design Center int seVirtInit(int DevID, DWORD VirtX, DWORD * VirtY) Description: This function prepares the system for virtual screen operation. The programmer passes the desired virtual width, in pixels, as VirtX. When the routine returns VirtY will contain the maximum number of line that can be displayed at the requested virtual width.
Page 151: Register / Memory Access
Epson Research and Development Page 55 Vancouver Design Center 9.2.4 Register / Memory Access The Register/Memory Access functions provide access to the S1D13704 registers and display buffer through the HAL. int seGetReg(int DevID, int Index, BYTE * pValue) Description: Reads the value in the register specified by index.
Page 152 Page 56 Epson Research and Development Vancouver Design Center int seReadDisplayWord(int DevID, DWORD Offset, WORD *pWord) Description: Reads a word from the display buffer at the specified offset and returns the value in pWord. Parameters: DevID - registered device ID...
Page 153 Epson Research and Development Page 57 Vancouver Design Center int seWriteDisplayWords(int DevID, DWORD Offset, WORD Value, DWORD Count) Description: Writes one or more WORDS to the display buffer at the offset specified by Addr. If a count greater than one is specified all WORDS will have the same value.
Page 154: Power Save
This section covers the HAL functions dealing with the Power Save features of the S1D13704. int seSetPowerSaveMode(int DevID, int PwrSaveMode) Description: This function sets on the S1D13704’s software selectable power save modes. Parameters: DevID - a registered device ID PwrSaveMode - integer value specifying the desired power save mode.
Page 155: Lut Manipulation
Epson Research and Development Page 59 Vancouver Design Center int seDrawRect(int DevID, long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) Description: This routine draws and optionally fills a rectangular area of display buffer. The upper right corner is defined by x1,y1 and the lower right corner is defined by x2,y2.
Page 156 Page 60 Epson Research and Development Vancouver Design Center int seGetLut(int DevID, BYTE *pLUT, int Count) Description: This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT. A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.
Page 157: Sample Code
10 Sample Code 10.1 Introduction Included in the sample code section are two examples of programing the S1D13704. The first sample uses the HAL to draw a red square, wait for user input then rotates to SwivelView mode and draws a blue square. The second sample code performs the same procedures but directly accesses the registers of the S1D13704.
Page 158 Vancouver Design Center printf("\nERROR: Could not register S1D13704 device."); exit(1); ** Get the product code to verify this is an S1D13704. ** NOTE: If the S1D13704 design is modified then the product identification change. Additional IDs will have to be checked for.
Page 159 Epson Research and Development Page 63 Vancouver Design Center seSetHWRotate(Device, PORTRAIT); ** Draw a solid blue 100x100 rectangle in center of the display. ** This starting co-ordinates, assuming a 320x240 display is ** (320-100)/2 , (240-100)/2 = 110,70. seDrawRect(Device, 110, 70, 210, 170, 2, TRUE);...
Page 160: Sample Code Without Using The S1D13704 Hal Api
This second sample demonstrates exactly the same sequence as the first howerver the HAL is not used, all manipulation is done by manually adjusting the registers. **=========================================================================== ** SAMPLE2.C - Sample code demonstating a direct access of the S1D13704. **------------------------------------------------------------------------- ** Created 1998, Vancouver Design Centre ** Copyright (c) 1998 Epson Research and Development, Inc.
Page 161 Epson Research and Development Page 65 Vancouver Design Center 0x00, 0x00, 0x0F,/* LT BLUE 0x00, 0x0F, 0x00,/* LT GREEN 0x00, 0x0F, 0x0F,/* LT CYAN 0x0F, 0x00, 0x00,/* LT RED 0x0F, 0x00, 0x0F,/* LT PURPLE */ 0x0F, 0x0F, 0x00,/* LT YELLOW */ 0x0F, 0x0F, 0x0F/* LT WHITE ** Register data for the configuratin described above.
Page 162 Page 66 Epson Research and Development Vancouver Design Center ** Check the revision code. Exit if we don't find an S1D13704. if (0x18 != *pRegs) return; ** Initialize the chip. ** Each register is individually programmed to make comments clearer.
Page 163 Epson Research and Development Page 67 Vancouver Design Center Frame Rate = --------------------------- (HDP + HNDP) * (VDP + VNDP) SET_REG(0x08, 0x1E); ** Register 09h - FPFRAME Start Position - not used by STN SET_REG(0x09, 0x00); ** Register 0Ah - Vertical Non-Display Register - CAlculated in conjunction with register 08h (HNDP) to achieve the desired frame rate.
Page 164 Page 68 Epson Research and Development Vancouver Design Center - Set to maximum (i.e. 0x3FF). This register is used for split screen operation and should be set to 0 during initialization. SET_REG(0x13, 0xFF); SET_REG(0x14, 0x03); ** Look-Up Table ** In this example the LUT will be programmed in the register sequence.
Page 165 Epson Research and Development Page 69 Vancouver Design Center values low should the pins get configured as outputs. SET_REG(0x19, 0x00); ** Register 1Ah - Scratch Pad - set to 0 SET_REG(0x1A, 0x00); ** Register 1Bh - SwivelView Mode - set to 0 - disable SwivelView mode SET_REG(0x1B, 0x00);...
Page 166 Page 70 Epson Research and Development Vancouver Design Center ** This is done because an image in display memory is not rotated with the ** switch to SwivelView mode we are about to make. pMem = (LPBYTE)MEM_OFFSET; do { *pMem = 0;...
Page 167 Epson Research and Development Page 71 Vancouver Design Center ** Set the memory pointer at the start of each line. Pointer = MEM_OFFSET + (Y * Line_Width * BPP / 8) + (X * BPP / 8) ** NOTICE that in SwivelView mode we will use a value of 256 ** for the line width value (not 240).
Page 168: Header Files
** HAL.H - Typical HAL header file for use with programs written to use the S1D13704 HAL. **--------------------------------------------------------------------------- ** Created 1998, Vancouver Design Centre ** Copyright (c) 1998 Epson Research and Development, Inc. ** All Rights Reserved. **=========================================================================== #ifndef _HAL_H_...
Page 169 Epson Research and Development Page 73 Vancouver Design Center #ifndef MAKEWORD #define MAKEWORD(lo, hi) ((WORD)(((WORD)(lo)) | (((WORD)(hi)) << 8)) ) #endif #ifndef MAKELONG #define MAKELONG(lo, hi) ((long)(((WORD)(lo)) | (((DWORD)((WORD)(hi))) << 16))) #endif #ifndef TRUE #define TRUE #endif #ifndef FALSE #define FALSE...
Page 170 Page 74 Epson Research and Development Vancouver Design Center /*-------------------------------------------------------------------------*/ enum ERR_OK = 0, /* No error, call was successful. */ ERR_FAILED, /* General purpose failure. ERR_UNKNOWN_DEVICE, /* */ ERR_INVALID_PARAMETER, /* Function was called with invalid parameter. */ ERR_HAL_BAD_ARG, ERR_TOOMANY_DEVS...
Page 171 Epson Research and Development Page 75 Vancouver Design Center #define FONT_DOUBLE_WIDTH 0x01 #define FONT_DOUBLE_HEIGHT 0x02 enum RED, GREEN, BLUE /*************************************************************************/ typedef struct tagHalStruct char szIdString[16]; WORD wDetectEndian; WORD wSize; BYTE Reg[MAX_REG + 1]; DWORD dwClkI; /* Input Clock Frequency (in kHz) */ DWORD dwDispMem;...
Page 172 Page 76 Epson Research and Development Vancouver Design Center int seSplitInit( int nDevID, WORD Scrn1Addr, WORD Scrn2Addr ); int seSplitScreen( int nDevID, int WhichScreen, int VisibleScanlines ); int seVirtInit( int nDevID, int xVirt, long *yVirt ); int seVirtMove( int nDevID, int nWhichScreen, int x, int y );...
Page 173 **=========================================================================== /**************************************************************/ 1374 HAL HDR (do not remove) HAL_STRUCT Information generated by 1374CFG.EXE Copyright (c) 1998 Seiko Epson Corp. All rights reserved. */ Include this file ONCE in your primary source file /**************************************************************/ HAL_STRUCT HalInfo = "1374 HAL EXE", /* ID string...
Page 174 Page 78 Epson Research and Development Vancouver Design Center 1374 register names #define REG_REVISION_CODE 0x00 #define REG_MODE_REGISTER_0 0x01 #define REG_MODE_REGISTER_1 0x02 #define REG_MODE_REGISTER_2 0x03 #define REG_HORZ_PANEL_SIZE 0x04 #define REG_VERT_PANEL_SIZE_LSB 0x05 #define REG_VERT_PANEL_SIZE_MSB 0x06 #define REG_FPLINE_START_POS 0x07 #define REG_HORZ_NONDISP_PERIOD 0x08 #define REG_FPFRAME_START_POS...
Page 175 Epson Research and Development Page 79 Vancouver Design Center Appendix A Supported Panel Values A.1 Introduction Future versions of this document will supply example tables for programming the S1D13704 for different panels. Programming Notes and Examples S1D13704 Issue Date: 01/02/12 X26A-G-002-03...
Page 176 Page 80 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Programming Notes and Examples X26A-G-002-03 Issue Date: 01/02/12...
Page 177 Bit 3 Bit 2 Bit 1 Bit 0 Software Power Save Mode Notes reserved 1 These bits are used to identify the S1D13704 at power on / reset. REG[0Ah] V IO address = FFEAh, RW ERTICAL ISPLAY ERIOD EGISTER reserved 2 IO addresses are relative to the beginning of display memory.
Page 178 S1D13704 Register Summary X26A-R-001-03 Page 2 01/02/12...
Page 179 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 180 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704CFG.EXE Configuration Program X26A-B-001-02 Issue Date: 01/02/08...
Page 181 Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ..........5 Program Requirements .
Page 182 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704CFG.EXE Configuration Program X26A-B-001-02 Issue Date: 01/02/08...
Page 183: Introduction
Introduction 13704CFG is a Win 32 program which gives developers an easy means to modify panel types, clock rates, color depths, etc. for S1D13704 demonstration programs. 13704CFG can: • Read programs, based on the 13704 Hardware Abstraction Layer (HAL), modify the settings and write the changes back to the file.
Page 184: Program Requirements
Page 6 Epson Research and Development Vancouver Design Center Program Requirements This program is designed to run under Windows 95/98 or Windows NT 4.0 Installation There is no installation program for 13704CFG. Installation to a local drive is done by copying 13704CFG.EXE and 13704CFG.HLP to your hard drive and optionally creating a...
Page 185: 13704Cfg
Epson Research and Development Page 7 Vancouver Design Center 13704CFG The 13704CFG window has four main sections: Panel information (includes Dimensions), LookUp Table, Miscellaneous Options, and System settings. Figure 1: 13704CFG Window The following sections describe each of the main sections of the configuration dialog box.
Page 186: Panel Information
Panel Information Figure 2: Panel Information This section of the 13704CFG dialog describes the panel connected to the S1D13704. Each of the settings are described briefly below. • Mono / Color – select mono for monochrome panels or color for color panels.
Page 187 Epson Research and Development Page 9 Vancouver Design Center • Format 2 – There are two data clocking formats in use by 8-bit color panels. The orig- inal clocking scheme was designated to be format 1 and the newer scheme was desig- nated format 2.
Page 188 - HW Video Invert is not availlable for TFT operation. • HW Power Save Enable - the S1D13704 supports two power save modes. One is initi- ated by software, the second in response to input on the GPIO0 pin. In order for the hardware power save mode to function this option must be selected.
Page 189: System
• Memory Location - this describes where in CPU address space the S1D13704 will be located. This setting is required by the HAL to locate the S1D13704. If the settings from 13704CFG will be saved to a C header file for use in a non-HAL program this value does not have to be filled in.
Page 190: Lut Control
Figure 6: ERROR: Zero Frame Rate • Input Clock - this field specifies the clock rate being applied to the S1D13704 in kHz. LUT Control The items in this section control the color depth for the S1D13704 after initialization.
Page 191: Open
From here the user selects the file to be opened. 13704CFG is capable of opening executable files based on the S1D13704 HAL. Typically the file extension for these file are .EXE for intel platform executables and .S9 for 68k and SH3 platform executables.
Page 192: Save
Page 14 Epson Research and Development Vancouver Design Center Opening a file reads that files HAL configuration information. Use the data read as a starting point in configuring this or other files or to check on the current configuration. If 13704CFG is unable locate the HAL information in the selected file the following dialog box is displayed.
Page 193: Help
If an executable file (.EXE or .S9) is selected as the type of file to save to the file being saved to must already exist and be an S1D13704 HAL based program. 13704CFG is cannot save to a non-existent program. If 13704CFG is unable to locate the HAL information in the file being saved to the following dialog box is displayed.
Page 194: Comments
Epson Research and Development Vancouver Design Center Comments It is assumed that the 13704CFG user is familiar with S1D13704 hardware and software. Refer to the S1D13704 “Functional Hardware Specification,” drawing office number X22A-A-001-xx, and the S1D13704 “Programming Notes and Examples” manual, drawing office number X22A-G-002-xx for information.
Page 195 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 196 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704SHOW Demonstration Program X26A-B-002-02 Issue Date: 01/02/08...
Page 197 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13704 Programming Notes and Examples manual, document number X26A-G-002-xx. Installation PC platform: copy the file 13704SHOW.EXE to a directory that is in the DOS path on...
Page 198 13704CFG configuration program. ERROR: Did not find a 13704 device. The HAL was unable to read the revision code register on the S1D13704. Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly.
Page 199 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 200 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704SPLT Display Utility X26A-B-003-02 Issue Date: 01/02/08...
Page 201 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13704 Programming Notes and Examples manual, document number X26A-G-002-xx. Installation PC platform: Copy the file 13704SPLT.EXE to a directory that is in the DOS path on your...
Page 202 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13704SPLT [/a] [/l] [/p] [/?] Embedded platform: execute 13704splt and at the prompt, type the command line argument. Where: no argument enables manual split screen operation...
Page 203 13704CFG configuration program. ERROR: Did not detect 13704. The HAL was unable to read the revision code register on the S1D13704. Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly. 13704SPLT Display Utility...
Page 204 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704SPLT Display Utility X26A-B-003-02 Issue Date: 01/02/08...
Page 205 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 206 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704VIRT Display Utility X26A-B-004-02 Issue Date: 01/02/08...
Page 207 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13704 Programming Notes and Examples manual, document number X26A-G-002-xx. Installation PC platform: copy the file 13704VIRT.EXE to a directory that is in the DOS path on your...
Page 208 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13704virt [/a] [/w=???]. Embedded platform: execute 13704virt and at the prompt, type the command line argument. Where: panning and scrolling is performed manually no argument...
Page 209 13704CFG configuration program. ERROR: Did not detect 13704. The HAL was unable to read the revision code register on the S1D13704. Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly. 13704VIRT Display Utility...
Page 210 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704VIRT Display Utility X26A-B-004-02 Issue Date: 01/02/08...
Page 211 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 212 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704PLAY Diagnostic Utility X26A-B-005-03 Issue Date: 01/02/08...
Page 213 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13704 Programming Notes and Examples manual, document number X26A-G-002-xx. 13704PLAY Diagnostic Utility...
Page 214 Page 4 Epson Research and Development Vancouver Design Center Installation PC platform: copy the file 13704PLAY.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 13704PLAY to the system. Usage PC platform: at the prompt, type 13704play [/?].
Page 215 Epson Research and Development Page 5 Vancouver Design Center Returns information about the current mode. M [bpp] If “bpp” is specified then set the requested color depth. Sets software power save mode 0-2. P 0|1|2 Power save mode 0 is normal operation.
Page 216 “results.” Example 1: The script file “dumpregs.scr” can be created with and text editor and will look like the following: ; This file initializes the S1D13704 and reads the registers ; Initialize the registers. ; Dump all the registers ;...
Page 217 A 13704 device was not found at the configured addresses. Check the configuration address using the 13704CFG configuration program. WARNING: Did not detect 13704. The HAL did not detect an S1D13704, however 13704PLAY will continue to function. 13704PLAY Diagnostic Utility S1D13704...
Page 218 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704PLAY Diagnostic Utility X26A-B-005-03 Issue Date: 01/02/08...
Page 219 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 220 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704BMP Demonstration Program X26A-B-006-02 Issue Date: 01/02/08...
Page 221 Page 3 Vancouver Design Center 13704BMP 13704BMP demonstrates S1D13704 display capabilities by rendering bitmap images on the display. The 13704BMP display utility is designed to operate in a personal computer DOS environment and must be configured to work with your display hardware. Consult documentation for the program 13704CFG.EXE which can be used to configure...
Page 222 13704CFG configuration program. ERROR: Did not detect 13704. The HAL was unable to read the revision code register on the S1D13704. Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly. S1D13704...
Page 223 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 224 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 13704PWR Power Save Utility X26A-B-007-02 Issue Date: 01/02/08...
Page 225 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13704 “Programming Notes and Examples” manual, document number X26A-G-002-xx. Installation PC platform: copy the file 13704PWR.EXE to a directory that is in the DOS path on your...
Page 226 13704CFG configuration program. ERROR: Did not detect 13704. The HAL was unable to read the revision code register on the S1D13704. Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly. S1D13704...
Page 227 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows is a registered trademark of Microsoft Corporation. All other Trademarks are the property of their respective owners.
Page 228 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Windows® CE Display Drivers X26A-E-001-02 Issue Date: 01/02/08...
Page 229 Memory LCD Controller running under the Microsoft Windows CE operating system. Available drivers include: 4 bit-per-pixel landscape mode, and 4 bit-per-pixel portrait mode. For updated source code, visit Epson Research and Development on the World Wide Web at www.erd.epson.com, or contact your Seiko Epson sales representative. 1.1 Program Requirements...
Page 230 3. Add an entry for the 4BPP13704 in the file \wince\platform\cepc\drivers\display\dirs. 4. Modify the file CONFIG.BIB (using any text editor such as NOTEPAD) to set the system RAM size, the S1D13704 IO port and display buffer address mapping. Note that CONFIG.BIB is located in X:\wince\platform\cepc\files (where X: is the drive letter).
Page 231 Epson Research and Development Page 5 Vancouver Design Center 6. Edit the file DISPDRVR.C (located in X:\wince\platform\odo\drivers\display\ 4BPP13704) to set the desired screen resolution, color depth (bpp) and panel type. The sample code defaults to a 320x240 color single passive 4-bit LCD panel. To sup- port one of the other listed panels, change the #define statement.
Page 232 • At the time of this printing, the drivers have been tested on the x86 CPUs and have only been run with version 2.0 of the ETK. We are constantly updating the drivers so please check our website at www.erd.epson.com, or contact your Seiko Epson or Epson Electronics America sales representative.
Page 233 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 234 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X26A-G-005-03 Issue Date: 01/02/12...
Page 235 Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........7 Features .
Page 236 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X26A-G-005-03 Issue Date: 01/02/12...
Page 237 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2-1: Configuration DIP Switch Settings ......8 Table 2-2: Host Bus Selection .
Page 238 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X26A-G-005-03 Issue Date: 01/02/12...
Page 239: Introduction
1 Introduction This manual describes the setup and operation of the S5U13704B00C Rev. 1.0 Evaluation Board. Implemented using the S1D13704 Embedded Memory Color LCD Controller, the S5U13704B00C board is designed for the 16-bit ISA bus environment. To accommodate other bus architectures, the S5U13704B00C board also provides CPU/Bus interface connectors.
Page 240: Installation And Configuration
Vancouver Design Center 2 Installation and Configuration The S1D13704 has five configuration inputs, CNF[4:0], which are read on the rising edge of RESET# and are fully configurable on this evaluation board. One six-position DIP switch is provided on the board to configure these five configuration inputs and to enable/disable hardware power save mode.
Page 241 Epson Research and Development Page 9 Vancouver Design Center Table 2-3: Jumper Settings Description IOVDD Selection 5.0V IOVDD 3.3V IOVDD RD/WR# Signal Selection Pulled up to IOVDD No Connection BS# Signal Selection Pulled up to IOVDD No Connection LCD Panel Voltage Selection 5.0V LCD Panel...
Page 242: Lcd Interface Pin Mapping
Page 10 Epson Research and Development Vancouver Design Center 3 LCD Interface Pin Mapping Table 3-1: LCD Signal Connector (J5) Pinout Connector Single Passive Panel Dual Passive Panel Color TFT/D-TFD Color Mono Color Mono 8-bit Pin Name Pin # 4-bit...
Page 243: Cpu/Bus Interface Connector Pinouts
SD13 Connected to DB13 of the S1D13704 SD14 Connected to DB14 of the S1D13704 SD15 Connected to DB15 of the S1D13704 RESET# Connected to the RESET# signal of the S1D13704 Ground Ground Ground +12V 12 volt supply +12V 12 volt supply...
Page 244 Ground 5 volt supply 5 volt supply RD/WR# Connected to the R/W# signal of the S1D13704 Connected to the BS# signal of the S1D13704 BUSCLK Connected to the BCLK signal of the S1D13704 Connected to the RD# signal of the S1D13704...
Page 245: Host Bus Interface Pin Mapping
Epson Research and Development Page 13 Vancouver Design Center 5 Host Bus Interface Pin Mapping Table 5-1: Host Bus Interface Pin Mapping S1D13704 SH-3 SH-4 MC68K #1 MC68K #2 Generic Bus #1 Generic Bus #2 Pin Names AB[15:1] A[15:1] A[15:1]...
Page 246: Technical Description
Page 14 Epson Research and Development Vancouver Design Center 6 Technical Description 6.1 ISA Bus Support This board has been designed to support the 16-bit ISA bus environment and can be used in conjunction with either a VGA or a monochrome display adapter card.
Page 247: Non-Isa Bus Support
Voltage lines are provided on the header strips. • U7, a TIBPAL16L8-15 PAL, is currently used to provide the S1D13704 CS# (pin 74), RESET# (pin 73) and other decode logic signals for ISA bus use. This functionality must now be provided externally;...
Page 248: Clock Input Support
Vancouver Design Center 6.5 Clock Input Support The input clock (CLKI) frequency can be up to 50.0MHz for the S1D13704 if the internal clock divide by 2 is set. If the clock divide is not used, the maximum CLKI frequency is 25MHz.
Page 249: Power Save Modes
R21 to give an output voltage from -14V to -23V, and is enabled/disabled by the S1D13704 control signal LCDPWR. LCDPWR is an S1D13704 output signal which is configurable as active high or active low by the CNF4 signal status on the rising edge of the RESET# signal. For the proper operation of the VLCD power supply, LCDPWR must be configured as active low.
Page 250: Cpu/Bus Interface Header Strips
Vancouver Design Center 6.13 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of the S1D13704 are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than ISA. Refer to Table 4-1: “CPU/BUS Connector (H1) Pinout,” on page 11 and Table 4-2: “CPU/BUS Connector (H2) Pinout,”...
Page 251: Parts List
Epson Research and Development Page 19 Vancouver Design Center 7 Parts List Item # Qty/board Designation Part Value Description C1-C11, C15,C16 0.1uF, 5%, 50V 0805 ceramic capacitor 1uF, 10%, 16V Tantalum capacitor size A C13, C14 10uF, 10%, 25V Tantalum capacitor size D...
Page 252: Schematic Diagrams
Page 20 Epson Research and Development Vancouver Design Center 8 Schematic Diagrams Figure 8-1: S1D13704B00C Schematic Diagram (1 of 4) S1D13704 S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X26A-G-005-03 Issue Date: 01/02/12...
Page 253 Epson Research and Development Page 21 Vancouver Design Center Figure 8-2: S1D13704B00C Schematic Diagram (2 of 4) S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual S1D13704 Issue Date: 01/02/12 X26A-G-005-03...
Page 254 Page 22 Epson Research and Development Vancouver Design Center Figure 8-3: S1D13704B00C Schematic Diagram (3 of 4) S1D13704 S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X26A-G-005-03 Issue Date: 01/02/12...
Page 255 Epson Research and Development Page 23 Vancouver Design Center Figure 8-4: S1D13704B00C Schematic Diagram (4 of 4) S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual S1D13704 Issue Date: 01/02/12 X26A-G-005-03...
Page 256 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X26A-G-005-03 Issue Date: 01/02/12...
Page 257 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 258 Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A-G-004-02 Issue Date: 01/02/12...
Page 259 Memory Mapping and Aliasing ......12 S1D13704 Configuration ......13 Software .
Page 260 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A-G-004-02 Issue Date: 01/02/12...
Page 261 Figure 2-1: S1D13704 to TX3912 Direct Connection ....... 8 Figure 3-1: S1D13704 to TX3912 Connection Using an IT8368E .
Page 262 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A-G-004-02 Issue Date: 01/02/12...
Page 263: Introduction
S1D13704 Embedded Memory Color Graphics LCD Controller and the Toshiba MIPS TX3912 Processor. For further information on the S1D13704, refer to the S1D13704 Hardware Functional Specifi- cation, document number X26A-A-001-xx. For further information on the TX3912, contact Toshiba or refer to the Toshiba website under semiconductors at http://www.toshiba.com/taec/nonflash/indexproducts.html.
Page 264: Direct Connection To The Toshiba Tx3912
In this example implementation, the S1D13704 occupies the TX3912 PC Card slot #1. The S1D13704 is easily interfaced to the TX3912 with minimal additional logic. The address bus of the TX3912 PC Card interface is multiplexed and can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373).
Page 265: Memory Mapping And Aliasing
2.3 S1D13704 Configuration and Pin Mapping The S1D13704 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also plays a role in host bus interface configuration. For details on configuration, refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx.
Page 266: System Design Using The Ite It8368E Pc Card Buffer
If the system designer uses the ITE IT8368E PC Card and multiple-function I/O buffer, the S1D13704 can be interfaced so that it ’shares’ a PC Card slot. The S1D13704 is mapped to a rarely- used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the S1D13704 virtually transparent to PC Card devices that use the same slot.
Page 267: It8368E Configuration
Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide control signals needed by the S1D13704 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13704. When accessing the S1D13704 the associated card-side signals are disabled in order to avoid any conflicts.
Page 268: Memory Mapping And Aliasing
CARD2IOEN are ignored and the attribute/IO space of the TX3912 is divided into Attribute, I/O and S1D13704 access. Table 3-2:, “TX3912 to PC Card Slots Address Remapping Using the IT8368E” provides all details of the Attribute/IO address reallocation by the IT8368E.
Page 269: S1D13704 Configuration
Vancouver Design Center 3.4 S1D13704 Configuration The S1D13704 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also plays a role in host bus interface configuration. For details on configuration, refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx.
Page 270: Software
Vancouver Design Center 4 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1357CFG, or by directly modifying the source.
Page 271: Epson Lcd Controllers (S1D13704)
EPSON Research and Development Page 15 Vancouver Design Center 5 Technical Support 5.1 EPSON LCD Controllers (S1D13704) Taiwan, R.O.C. North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.
Page 272 Page 16 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A-G-004-02 Issue Date: 01/02/12...
Page 273 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 274 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Power Consumption X26A-G-006-02 Issue Date: 01/02/12...
Page 275 • V voltage levels (Core and IO): the voltage level of the Core and IO sections in the S1D13704 affects power consumption – the higher the voltage, the higher the consumption. • Display mode: the resolution, panel type, and color depth affect power consumption. The higher the resolution/color depth and number of LCD panel signals, the higher the power consumption.
Page 276 Page 4 Epson Research and Development Vancouver Design Center 1.1 Conditions Table 1-1: “S1D13704 Total Power Consumption” below gives an example of a specific environment and its effects on power consumption. Table 1-1: S1D13704 Total Power Consumption Power Consumption Test Condition...
Page 277 LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13704 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility.
Page 278 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Power Consumption X26A-G-006-02 Issue Date: 01/02/12...
Page 279 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 280 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor X26A-G-007-03 Issue Date: 01/02/12...
Page 281 Chip-Select Module ......8 S1D13704 Host Bus Interface ......9 Bus Interface Modes .
Page 282 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor X26A-G-007-03 Issue Date: 01/02/12...
Page 283 List of Figures Figure 4-1: Typical Implementation of MC68328 to S1D13704 Interface - MC68K #1 ..12 Figure 4-2: Typical Implementation of MC68328 to S1D13704 Interface - Generic #1 ..13 Interfacing to the Motorola MC68328 ‘Dragonball’...
Page 284 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor X26A-G-007-03 Issue Date: 01/02/12...
Page 285: Introduction
This application note describes the hardware required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the Motorola MC68328 “Dragonball” Microprocessor. By implementing a dedicated display refresh memory, the S1D13704 can reduce system power consumption, improve image quality, and increase system perfor- mance as compared to the Dragonball’s on-chip LCD controller.
Page 286: Interfacing To The Mc68328
The S1D13704 implements the MC68000 bus interface using its “MC68K #1” mode, so this mode may be used to connect the MC68328 directly to the S1D13704 with no glue logic. However, several of the MC68000 bus control signals are multiplexed with IO and interrupt signals on the MC68328, and in many applications it may be desirable to make these pins available for these alternate functions.
Page 287: S1D13704 Host Bus Interface
Vancouver Design Center 3 S1D13704 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic #1 and MC68K #1 host bus interfaces that may be used to implement the interface to the MC68328.
Page 288: Generic #1 Interface Mode
3.2 Generic #1 Interface Mode Generic #1 interface mode is the most general and least processor-specific interface mode on the S1D13704. The Generic # 1 interface mode was chosen for this interface due to the simplicity of its timing. The interface requires the following signals: •...
Page 289: Mc68K #1 Interface Mode
CPU. • WAIT# is a signal which is output from the S1D13704 to the host CPU that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host...
Page 290: Mc68328 To S1D13704 Interface
UDS, LDS, and DTACK). In implementations where all of these pins are available for use as bus control pins, then the S1D13704 interface is a straightforward implementation of the “MC68K #1” host bus interface. For further information on this host bus interface, refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx.
Page 291: Using The Generic #1 Host Bus Interface
Note that in either case, the DTACK signal must be made available for the S1D13704, since it inserts a variable number of wait states depending upon CPU/LCD synchronization and the LCD panel display mode. WAIT# must be inverted (using an inverter enabled by CS#) to make it an active high signal and thus compatible with the MC68328 architecture.
Page 292: S1D13704 Hardware Configuration
Vancouver Design Center 4.2 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx for details.
Page 293: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13704CFG, or by directly modifying the source.
Page 294: References
• Epson Research and Development, Inc., S1D13704 Hardware Functional Specification; Document Number X26A-A-001-xx. • Epson Research and Development, Inc., S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual; Document Number X26A-G-005-xx. • Epson Research and Development, Inc., S1D13704 Programming Notes and Examples;...
Page 295 Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13704) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...
Page 296 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor X26A-G-007-03 Issue Date: 01/02/12...
Page 297 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 298 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the NEC VR4102™ Microprocessor X26A-G-008-05 Issue Date: 01/02/12...
Page 299 LCD Memory Access Cycles ......9 S1D13704 Host Bus Interface ......10 Bus Interface Modes .
Page 300 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the NEC VR4102™ Microprocessor X26A-G-008-05 Issue Date: 01/02/12...
Page 301 Figure 2-1: NEC VR4102 Read/Write Cycles ......9 Figure 4-1: Typical Implementation of VR4102 to S1D13704 Interface ....13 Interfacing to the NEC VR4102™...
Page 302 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the NEC VR4102™ Microprocessor X26A-G-008-05 Issue Date: 01/02/12...
Page 303: Introduction
Vancouver Design Center 1 Introduction This application note describes the hardware required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the NEC V 4102 Microprocessor (uPD30102). The NEC V 4102 Microprocessor is specifically designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption.
Page 304: Interfacing To The Nec Vr4102
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 2.1 The NEC VR4102 System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE-based embedded consumer applications in mind, the VR4102 offers a highly integrated solution for portable systems.
Page 305: Lcd Memory Access Cycles
Epson Research and Development Page 9 Vancouver Design Center 2.1.2 LCD Memory Access Cycles Figure 2-1: “NEC VR4102 Read/Write Cycles,” on page 9 shows the read and write cycles to the LCD Controller Interface. Once an address in the LCD block of memory is placed on the external address bus, ADD[25:0], the LCD chip select, LCDCS#, is driven low.
Page 306: S1D13704 Host Bus Interface
Vancouver Design Center 3 S1D13704 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic #2 host bus interface used to implement the interface to the VR4102.
Page 307: Generic #2 Interface Mode
These must be generated by external decode hardware based upon the control outputs from the host CPU. • RD# is the read enable for the S1D13704, to be driven low when the host CPU is reading data from the S1D13704. RD# must be generated by external decode hardware based upon the control outputs from the host CPU.
Page 308 • The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter- face for Generic #2 mode. However, BS# is used to configure the S1D13704 for Generic #2 mode and should be tied high (connected to IO V ).
Page 309: Vr4102 To S1D13704 Interface
Generic # 2 interface, only one inverter is required to change the polarity of the system reset signal to active low. A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle. The following diagram shows a typical implementation of the VR4102 to S1D13704 interface. NEC V...
Page 310: S1D13704 Hardware Configuration
Vancouver Design Center 4.2 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx for details.
Page 311: Nec Vr4102 Configuration
LCD controller. Physical address 0A000000h to 0AFFFFFFh (16M bytes) is reserved for an external LCD controller. The S1D13704 supports up to 40K bytes of display buffer memory and 32 bytes for internal registers. Therefore, the S1D13704 will be shadowed over the entire 16M byte memory range at 64K byte segments.
Page 312: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13704CFG, or by directly modifying the source.
Page 313 6.1 Documents • NEC V 4102 64/32-bit Microprocessor Preliminary User’s Manual. • Epson Research and Development, Inc., S1D13704 Embedded Memory Color LCD Controller Hardware Functional Specification; Document Number X26A-A-001-xx. • Epson Research and Development, Inc., S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual;...
Page 314 Page 18 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 Epson LCD Controllers (S1D13704) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...
Page 315 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 316 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the PC Card Bus X26A-G-009-03 Issue Date: 01/02/12...
Page 317 Memory Access Cycles ....... . . 8 S1D13704 Bus Interface ....... . 10 Bus Interface Modes .
Page 318 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the PC Card Bus X26A-G-009-03 Issue Date: 01/02/12...
Page 319 Figure 2-2: PC Card Write Cycle ........9 Figure 4-1: Typical Implementation of PC Card to S1D13704 Interface ....12...
Page 320 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the PC Card Bus X26A-G-009-03 Issue Date: 01/02/12...
Page 321: Introduction
1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 322: Interfacing To The Pc Card Bus
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2.1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness. This section is an overview of the operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1...
Page 323 Epson Research and Development Page 9 Vancouver Design Center During a read cycle, OE# (output enable) is driven low. A write cycle is specified by driving OE# high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT# low for the time needed to complete the cycle.
Page 324: S1D13704 Bus Interface
Vancouver Design Center 3 S1D13704 Bus Interface This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic #1 host bus interface used to implement the interface to the PC Card bus.
Page 325: Generic #1 Interface Mode
3.2 Generic #1 Interface Mode Generic #1 interface mode is the most general and least processor-specific interface mode on the S1D13704. The Generic # 1 interface mode was chosen for this interface due to the simplicity of its timing. The interface requires the following signals: •...
Page 326: Pc Card To S1D13704 Interface
RD/WR#, WE0#, WE1#, and CS# for the S1D13704. The PAL also inverts the reset signal of the PC card since it is active high and the S1D13704 uses an active low reset. For PAL equations for this implementation refer to Section 4.3, “PAL Equations” on page 14.
Page 327: S1D13704 Hardware Configuration
Vancouver Design Center 4.2 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx for details.
Page 328: Pal Equations
32 bytes of the 64K byte block (i.e. REG[0] = FFE0h). While the PC Card socket provides 64M bytes of address space, the S1D13704 only needs a 64K byte block of memory to accommodate its 40K byte display buffer and its 32 byte register set.
Page 329: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13704CFG, or by directly modifying the source.
Page 330 6 References 6.1 Documents • PC Card (PCMCIA) Standard March 1997 • Epson Research and Development, Inc., S1D13704 Embedded Memory Color LCD Controller Hardware Functional Specification; Document Number X26A-A-001-xx. • Epson Research and Development, Inc., S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual;...
Page 331 Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13704) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...
Page 332 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the PC Card Bus X26A-G-009-03 Issue Date: 01/02/12...
Page 333 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 334 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A-G-010-03 Issue Date: 01/02/12...
Page 335 User-Programmable Machine (UPM) ......12 S1D13704 Host Bus Interface ......13 Host Bus Interface Modes .
Page 336 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A-G-010-03 Issue Date: 01/02/12...
Page 337 Table 3-1: Host Bus Interface Pin Mapping ......13 Table 4-1: List of Connections from MPC821ADS to S1D13704 ....16 Table 4-2: Configuration Settings .
Page 338 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A-G-010-03 Issue Date: 01/02/12...
Page 339: Introduction
1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the Motorola MPC821 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 340: Interfacing To The Mpc821
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2.1 The MPC8xx System Bus The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern RISC microprocessors. This section provides an overview of the operation of the CPU bus in order to establish interface requirements.
Page 341: Normal (Non-Burst) Bus Transactions
Epson Research and Development Page 9 Vancouver Design Center 2.2.1 Normal (Non-Burst) Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: •...
Page 342: Burst Cycles
Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: “Power PC Memory Write Cycle” illustrates a typical memory write cycle on the Power PC system bus. SYSCLK A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Valid Transfer Start Wait States Transfer...
Page 343: Memory Controller Module
Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI) simultaneously with TA, and the processor will revert to normal bus cycles for the remaining data transfers.
Page 344: User-Programmable Machine (Upm)
Page 12 Epson Research and Development Vancouver Design Center 2.3.2 User-Programmable Machine (UPM) The UPM is typically used to control memory types, such as Dynamic RAMs, which have complex control or address multiplexing requirements. The UPM is a general purpose RAM-based pattern generator which can control address multiplexing, wait state gener- ation, and five general-purpose output lines on the MPC821.
Page 345: S1D13704 Host Bus Interface
Vancouver Design Center 3 S1D13704 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic #1 host bus interface used to implement the interface to the MPC821 bus.
Page 346: Generic #1 Host Bus Interface Mode
The host bus interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13704 host interface. It is sepa- rate from the input clock (CLKI) and is typically driven by the host CPU system clock.
Page 347: Mpc821 To S1D13704 Interface
The inverter is enabled using CS# so that TA is not driven by the S1D13704 during non-S1D13704 bus cycles. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.
Page 348 4.2 Hardware Connections The following table details the connections between the pins and signals of the MPC821 and the S1D13704. Table 4-1: List of Connections from MPC821ADS to S1D13704 MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13704 Signal Name...
Page 349 Epson Research and Development Page 17 Vancouver Design Center Table 4-1: List of Connections from MPC821ADS to S1D13704 (Continued) MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13704 Signal Name P6-B6 to inverter enabled by CS# WAIT# P6-B15 WE1# P6-A14...
Page 350: S1D13704 Hardware Configuration
Vancouver Design Center 4.3 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx for details.
Page 351: Mpc821 Chip Select Configuration
Chip select 4 is used to control the S1D13704. The following options are selected in the base address register (BR4): • BA (0:16) = 0000 0000 0100 0000 0 – set starting address of S1D13704 to 40 0000h • AT (0:2) = 0 – ignore address type bits •...
Page 352: Test Software
The test software to exercise this interface is very simple. It configures chip select 4 on the MPC821 to map the S1D13704 to an unused 64k byte block of address space and loads the appropriate values into the option register for CS4. At that point the software runs in a tight loop reading the 13704 Revision Code Register REG[00h], which allows monitoring of the bus timing on a logic analyzer.
Page 353 S1D13704 memory block is tagged as non-cacheable, to ensure that accesses to the S1D13704 will occur in proper order, and also to ensure that the MPC821 does not attempt to cache any data read from or written to the S1D13704 or its display buffer.
Page 354: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13704CFG, or by directly modifying the source.
Page 355 • Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User’s Manual, Motorola Publication no. MPC821UM/AD; available on the Internet at http://www.mot.com/SPS/ADC/pps/_subpgs/_documentation/821/821UM.html. • Epson Research and Development, Inc., S1D13704 Embedded Memory LCD Controller Hardware Functional Specification; Document Number X126A-A-002-xx. • Epson Research and Development, Inc., S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual;...
Page 356 Page 24 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13704) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...
Page 357 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 358 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor X26A-G-011-03 Issue Date: 01/02/12...
Page 359 Chip-Select Module ......10 S1D13704 Bus Interface ....... . 11 Bus Interface Modes .
Page 360 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor X26A-G-011-03 Issue Date: 01/02/12...
Page 361 Figure 2-2: MCF5307 Memory Write Cycle ......9 Figure 4-1: Typical Implementation of MCF5307 to S1D13704 Interface ....13 Interfacing to the Motorola MCF5307 "ColdFire"...
Page 362 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor X26A-G-011-03 Issue Date: 01/02/12...
Page 363: Introduction
1 Introduction This application note describes the hardware required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the Motorola MCF5307 Processor. The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption.
Page 364: Interfacing To The Mcf5307
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2.1 The MCF5307 System Bus The MCF5200/5300 family of processors feature a high-speed synchronous system bus typical of modern microprocessors. This section is an overview of the operation of the CPU bus to establish interface requirements.
Page 365: Burst Cycles
IO peripheral devices such as the S1D13704. The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them.
Page 366: Chip-Select Module
Page 10 Epson Research and Development Vancouver Design Center 2.2 Chip-Select Module In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select Module can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible with most memory and x86-style peripherals. The MCF5307 bus controller also provides a Read/Write (R/W) signal which is compatible with most 68K peripherals.
Page 367: S1D13704 Bus Interface
Vancouver Design Center 3 S1D13704 Bus Interface This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic #1 host bus interface used to implement the interface to the MCF5307.
Page 368: Generic #1 Interface Mode
3.2 Generic #1 Interface Mode Generic #1 interface mode is the most general and least processor-specific interface mode on the S1D13704. The Generic # 1 interface mode was chosen for this interface due to the simplicity of its timing. The interface requires the following signals: •...
Page 369: Mcf5307 To S1D13704 Interface
(TA) is an active low signal to end the current bus cycle. The inverter is enabled by CS# so that TA is not driven by the S1D13704 during non-S1D13704 bus cycles. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.
Page 370: S1D13704 Hardware Configuration
Vancouver Design Center 4.2 S1D13704 Hardware Configuration The S1D13704 uses CNF0 through CNF4 and BS# to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Table 4-1: “Summary of Power- On/Reset Options” and Table 4-2: “Host Bus Interface Selection” shows the settings used for the S1D13704 in this interface.
Page 371: Mcf5307 Chip Select Configuration
Therefore, one of the IO chip selects, CS2 through CS7, is required to address the entire address space of the S1D13704. These IO chip selects have a fixed, 2M byte block size. In the example interface, chip select 4 is used to control the S1D13704. The S1D13704 only uses a 64K byte block with its 40K byte display buffer residing at the start of this 64K byte block and its internal registers occupying the last 32 bytes of this block.
Page 372: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13704CFG, or by directly modifying the source.
Page 373 • Epson Research and Development, Inc., S1D13704 Hardware Functional Specification; Document Number X26A-A-002-xx. • Epson Research and Development, Inc., S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual; Document Number X26A-G-005-xx. • Epson Research and Development, Inc., S1D13704 Programming Notes and Examples;...
Page 374 Page 18 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13704) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...
Page 375 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 376 Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Philips MIPS PR31500/PR31700 Processor X26A-G-012-02 Issue Date: 01/02/12...
Page 377 Memory Mapping and Aliasing ......12 S1D13704 Configuration ......13 Software .
Page 378 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Philips MIPS PR31500/PR31700 Processor X26A-G-012-02 Issue Date: 01/02/12...
Page 379 Table 2-2: S1D13704 Generic #2 Interface Pin Mapping ......9 Table 3-1: PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping .
Page 380 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Philips MIPS PR31500/PR31700 Processor X26A-G-012-02 Issue Date: 01/02/12...
Page 381: Introduction
S1D13704 Embedded Memory Color Graphics LCD Controller and the Philips MIPS PR31500/PR31700 Processor. For further information on the S1D13704, refer to the S1D13704 Hardware Functional Specifi- cation, document number X26A-A-001-xx. For further information on the PR31500/PR31700, contact Philips or refer to the Philips website at http://www.philips.com.
Page 382: Direct Connection To The Philips Pr31500/Pr31700
Clock divider Figure 2-1: S1D13704 to PR31500/PR31700 Direct Connection The “Generic #2” host interface control signals of the S1D13704 are asynchronous with respect to the S1D13704 bus clock. This gives the system designer full flexibility to choose the appropriate source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and whether to use DCLKOUT (divided) as clock source, should be based on the desired: •...
Page 383: Memory Mapping And Aliasing
2.3 S1D13704 Configuration and Pin Mapping The S1D13704 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also plays a role in host bus interface configuration. For details on configuration, refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx.
Page 384: System Design Using The Ite It8368E Pc Card Buffer
If the system designer uses the ITE IT8368E PC Card and multiple-function I/O buffer, the S1D13704 can be interfaced so that it ’shares’ a PC Card slot. The S1D13704 is mapped to a rarely- used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the S1D13704 virtually transparent to PC Card devices that use the same slot.
Page 385: It8368E Configuration
Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide control signals needed by the S1D13704 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13704. When accessing the S1D13704 the associated card-side signals are disabled in order to avoid any conflicts.
Page 386 CARD1IOEN and CARD2IOEN are ignored and the attribute/IO space of the PR31500/PR31700 is divided into Attribute, I/O and S1D13704 access. Table 3-2:, “PR31500/PR31700 to PC Card Slots Address Remapping Using the IT8368E” provides all details of the Attribute/IO address reallocation by the IT8368E.
Page 387 Vancouver Design Center 3.4 S1D13704 Configuration The S1D13704 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also plays a role in host bus interface configuration. For details on configuration, refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx.
Page 388 Vancouver Design Center 4 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1357CFG, or by directly modifying the source.
Page 389 EPSON Research and Development Page 15 Vancouver Design Center 5 Technical Support 5.1 EPSON LCD Controllers (S1D13704) Taiwan, R.O.C. North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.
Page 390 Page 16 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to the Philips MIPS PR31500/PR31700 Processor X26A-G-012-02 Issue Date: 01/02/12...
Page 391 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 392 Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704/5 - TMPR3912/22U CPU Module X00A-G-004-02 Issue Date: 01/03/07...
Page 393 S1D13704 vs. S1D13705 ........13...
Page 394 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704/5 - TMPR3912/22U CPU Module X00A-G-004-02 Issue Date: 01/03/07...
Page 395 Figure 3-1: S1D13704 to TMPR3912/22U Interface ......10 S5U13704/5 - TMPR3912/22U CPU Module...
Page 396 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704/5 - TMPR3912/22U CPU Module X00A-G-004-02 Issue Date: 01/03/07...
Page 397: Introduction
This manual describes the interface between the S1D13704/5 LCD Controller (LCDC) and the TMPR3912/22U microprocessor as implemented on the Toshiba 3912/22 and S1D13704/5 CPU Module. This module is uS1D in conjunction with the Toshiba TX RISC Reference Platform. For more information regarding the S1D13704 or S1D13705 refer to their respective Hardware Functional Specification, document number X26A-A-001-xx and X27A-A-001-xx respectively.
Page 398: S1D13704/5 Bus Interface
Bus interface mode selections are made during reset by sampling the state of the configu- ration pins CNF[2:0] and the BS# line. Table 5-1 in the S1D13704 or S1D13705 Hardware Functional Specification details the values needed for the configuration pins and BS# to select the desired mode.
Page 399: Generic #2 Interface Mode
These must be generated by external decode hardware based upon the control outputs from the host CPU. • RD# is the read enable for the S1D13704/5, to be driven low when the host CPU is reading data from the S1D13704/5. RD# must be generated by external decode hard- ware based upon the control outputs from the host CPU.
Page 400: Tmpr3912/22U And S1D13704/5 Interface
The Generic # 2 bus mode of the S1D13704/5 is used to interface to this PC Card slot #1. The S1D13704/5 is interfaced to the TMPR3912/22U with minimal glue logic. Since the address bus of the TMPR3912/22U is multiplexed, it is demultiplexed using an advanced CMOS latch (74ACT373) to obtain the higher address bits needed for the S1D13704/5.
Page 401: Memory Mapping And Aliasing
FFE0h through FFFFh. The TMPR3912/22U demultiplexed address lines A16 and above are ignored if the S1D13704 is used, thus it is aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot #1 memory space. If the S1D13705 is used, address lines A17 and above are ignored;...
Page 402: Cpu Module Description
4.1 Clock Signals 4.1.1 BUSCLK Because the bus clock for the S1D13704/5 does not need to be synchronous with the bus interface control signals, a lot of flexibility is available in the choice for BUSCLK. In this CPU module, BUSCLK is a divided by two version of the SDRAM clock signal, DCLKOUT.
Page 403: Standard Epson Lcd Connector, J4
The LCD controller used in conjunction with the TMPR3912/22U microprocessor can either be a S1D13704 or a S1D13705. If a S1D13704 is used, jumper JP7 must be set to position 1 2. This setting allows CNF4 to be configured for the S1D13704. CNF4 controls the polarity of the LCDPWR signal and can be set either high or low with jumper, JP11.
Page 404 Page 14 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704/5 - TMPR3912/22U CPU Module X00A-G-004-02 Issue Date: 01/03/07...
Page 405 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 406 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to an 8-bit Processor X26A-G-013-02 Issue Date: 01/02/12...
Page 407 The Generic 8-bit Processor System Bus ..... 8 S1D13704 Bus Interface ....... . . 9 Host Bus Pin Connection .
Page 408 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to an 8-bit Processor X26A-G-013-02 Issue Date: 01/02/12...
Page 409 Table 4-2: Host Bus Selection ........12 List of Figures Figure 4-1: Typical Implementation of an 8-bit Processor to the S1D13704 Generic #2 Interface . . 11 Interfacing to an 8-bit Processor...
Page 410 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13704 Interfacing to an 8-bit Processor X26A-G-013-02 Issue Date: 01/02/12...
Page 411: Introduction
1 Introduction This application note describes the hardware environment required to provide an interface between the S1D13704 Embedded Memory LCD Controller and a generic 8-bit micropro- cessor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 412: Interfacing To An 8-Bit Processor
Typically, the bus of an 8-bit microprocessor is straight forward with minimal CPU and system control signals. To connect a memory mapped device such as the S1D13704, only the write, read, and wait control signals, as well as the data and address lines, need to be interfaced.
Page 413: S1D13704 Bus Interface
Vancouver Design Center 3 S1D13704 Bus Interface This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic #2 Host Bus Interface used to implement the interface to an 8-bit processor.
Page 414: Generic #2 Interface Mode
• WE0# is the enable signal for a write access, to be driven low when the host CPU is writing the 13704 memory or registers. • RD# is the read enable for the S1D13704, to be driven low when the host CPU is reading data from the S1D13704.
Page 415: 8-Bit Processor To S1D13704 Interface
The interface between the S1D13704 and an 8-bit processor requires minimal glue logic. A decoder is used to generate the chip select for the S1D13704 based on where the S1D13704 is mapped into memory. Alternatively, if the processor supports a chip select module, it can be programmed to generate a chip select for the S1D13704 without the need of an address decoder.
Page 416: S1D13704 Hardware Configuration
Vancouver Design Center 4.2 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx for details.
Page 417: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13704. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13704CFG, or by directly modifying the source.
Page 418 Vancouver Design Center 6 References 6.1 Documents • Epson Research and Development, Inc., S1D13704 Embedded Memory LCD Controller Hardware Functional Specification; Document Number X26A-A-002-xx. • Epson Research and Development, Inc., S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual; Document Number X26A-G-005-xx.
Page 419 Epson Research and Development Page 15 Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13704) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...
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Epson S1D13704 Technical Manual

Table of Contents

1 Introduction

2 Features

3 Typical System Implementation Diagrams

4 Functional Block Diagram

5 Pins

6 C. Characteristics

7 C. Characteristics

8 Registers

10 Display Data Formats

14 Mechanical Data

Table of Contents

1 Introduction

2 Initialization

3 Memory Models

4 Look-Up Table (LUT)

5 Advanced Techniques

6 LCD Power Sequencing and Power Save Modes

7 Swivelview

8 Identifying the S1D13704

9 Hardware Abstraction Layer (HAL)

10 Sample Code

Table of Contents

Introduction

Program Requirements

Comments

Table of Contents

1 Introduction

2 Installation and Configuration

3 LCD Interface Pin Mapping

4 Cpu/Bus Interface Connector Pinouts

5 Host Bus Interface Pin Mapping

6 Technical Description

7 Parts List

8 Schematic Diagrams

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1 Introduction

2 Direct Connection to the Toshiba TX3912

3 System Design Using the ITE IT8368E PC Card Buffer

4 Software

Table of Contents

1 Introduction

2 Interfacing to the MC68328

3 S1D13704 Host Bus Interface

4 MC68328 to S1D13704 Interface

5 Software

6 References

Table of Contents

1 Introduction

2 Interfacing to the NEC VR4102

3 S1D13704 Host Bus Interface

4 VR4102 to S1D13704 Interface

5 Software

Table of Contents

1 Introduction

2 Interfacing to the PC Card Bus

3 S1D13704 Bus Interface

4 PC Card to S1D13704 Interface

5 Software

Table of Contents

1 Introduction

2 Interfacing to the MPC821

3 S1D13704 Host Bus Interface

4 MPC821 to S1D13704 Interface

5 Software

Quick Links

Chapters

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Summary of Contents for Epson S1D13704