Flash Electronically Erasable Programmable Memory - Motorola 6864115B62-C Detailed Service Manual

1-8 THEORY OF OPERATION
On the µP the lines XIRQ (U0101-48), MODA LIR (U0101-58), MODB VSTPY (U0101-57) and
RESET (U0101-94) should be high at all times during normal operation. Whenever a data or address
line becomes open or shorted to an adjacent line, a common symptom is that the RESET line goes
low periodically, with the period being in the order of 20msecs. In the case of shorted lines you may
also detect the line periodically at an intermediate level, i.e. around 2.5V when 2 shorted lines
attempt to drive to opposite rails.
The MODA LIR (U0101-58) and MODB VSTPY (U0101-57) inputs to the µP must be at a logic 1 for
it to start executing correctly. After the µP starts execution it will periodically pulse these lines to
determine the desired operating mode. While the Central Processing Unit (CPU) is running, MODA
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction (an
instruction typically requires 2-4 external bus cycles, or memory fetches). However, since it is an
open-drain output, the waveform rise assumes an exponential shape similar to an RC circuit.
There are 8 analogue to digital converter ports (A/D) on U0101. They are labelled within the device
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and
convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action.
For example U0101-67 is the battery voltage detect line. R0671 and R0672 form a resistor divider on
INT SWB+. With 30K and 10K and a voltage range of 11V to 17V, that A/D port would see 2.74V to
4.24V which would then be converted to ~140 to 217 respectively.
U0101-69 is the high reference voltage for the A/D ports on the µP. Capacitor C0101 filters the +5V
reference. If this voltage is lower than +5V the A/D readings will be incorrect. Likewise U0101-68 is
the low reference for the A/D ports. This line is normally tied to ground. If this line is not connected to
ground, the A/D readings will be incorrect.
1.13 FLASH Electronically Erasable Programmable Memory (FLASH EEPROM)
The 512KByte FLASH EEPROM (U0121) contains the radio's operating software. This software is
common to all open architecture radios within a given model type. For example Trunking radios may
have a different version of software in the FLASH EEPROM than a non Trunking radio. This is, as
opposed to the codeplug information stored in EEPROM (U0111) which could be different from one
user to another in the same company.
In normal operating mode, this memory is only read, not written to. The memory access signals (CE,
OE and WE) are generated by the µP.
To upgrade/reprogram the FLASH software, the µP must be set in bootstrap operating mode. This is
done by pulling microprocessor pins MODA LIR (U0101-58) and MODB VSTBY (U0101-57) to low
during power up. When accessory connector pin 18 is at ground level, diode D0151 will pull both
microprocessor pins to low. The same can be done by a level of 12 volts on line ON OFF CONTROL
from the controlhead. Q0151 pulls diode D0151 and in turn both microprocessor pins to low. Diode
VR0151 prevents entering bootstrap operating mode during normal power up.
In bootstrap operating mode the µP controls the FLASH EN OE (U0121-32) input by µP pin 86. Chip
select (U0121-30) and read or write operation (U0121-7) are controlled by µP pins 38 and 4.
The FLASH device may be reprogrammed 1,000 times without issue. It is not recommended to
reprogram the FLASH device at a temperature below 0°C.
Capacitor C0121 serves to filter out any AC noise which may ride on +5V at U0121.