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2.17.3 External Memory Control Signal Expansion Connector
The External Memory Control Signal connector contains 56F836's external memory
control signal lines. CS2 and CS3 are MPIO signals, which can be configured as GPIO
Port D lines (bits 0 & 1). Refer to
Table 2-16. External Memory Control Signal Connector Description
2.17.4 Encoder #0 / Quad Timer Channel A Expansion Connector
The Encoder #0 / Quad Timer Channel A port is an MPIO port attached to the Timer A
expansion connector. This port can be configured as a Quadrature Decoder interface port
or as a Quad Timer port. Refer to
Table 2-17. Timer A Signal Connector Description
2.17.5 Encoder #1 / SPI #1 Expansion Connector
The Encoder #1 / SPI #1 port is an MPIO port attached to the SPI #1 expansion connector.
This port can be configured as a Quadrature Decoder interface port, a Serial Peripherial
Interface, Quad Timer port or General Purpose I/O port. Refer to
signals attached to the connector.
MOTOROLA
Freescale Semiconductor, Inc.
Table 2-16
J9
Pin #
Signal
1
RD
3
WR
5
PS/CS0
7
PD0/CS2
9
CLKO
11
GND
Table 2-17
J18
Pin #
Signal
1
PHASEA0/TA0
3
INDEX0/TA2
5
GND
Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Peripheral Expansion Connectors
for the names of these signals.
Pin #
Signal
2
IRQA
4
IRQB
6
DS/CS1
8
PD1/CS3
10
RESET
12
RSTO
for the signals attached to the connector.
Pin #
Signal
2
PHASEB0/TA1
4
HOME0/TA3
6
+3.3V
Table 2-18
for the
2-27
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