Motorola MVME2400 Series Manuals

Manuals and User Guides for Motorola MVME2400 Series. We have 3 Motorola MVME2400 Series manuals available for free PDF download: Programmer's Reference Manual, Installation And Use Manual, Installation And User Manual

Motorola MVME2400 Series Programmer's Reference Manual

Motorola MVME2400 Series Programmer's Reference Manual (331 pages)

VME Processor Module

Brand: Motorola | Category: Control Unit | Size: 1.33 MB

Safety Summary
4
Table of Contents
8
About this Manual

20
- Summary of Changes
  20
- Overview of Contents
  21
- Comments and Suggestions
  21
- Manual Terminology
  22
- Conventions Used in this Manual
  24
CHAPTER 1 Board Description and Memory Maps

25
CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

59
- Introduction
  59
  - Overview
    59
  - Features
    59
- Block Diagram
  61
- Figure 2-1. Hawk's PCI Host Bridge Block Diagram
  61
- Functional Description
  62
  - Architectural Overview
    62
  - PPC Bus Interface
    63
    
    PPC Address Mapping
    63
    
    Figure 2-2. PPC to PCI Address Decoding
    64
    
    Figure 2-3. PPC to PCI Address Translation
    65
    
    PPC Slave
    65
    
    Table 2-1. PPC Slave Response Command Types
    66
    
    Ppc Fifo
    67
    
    PPC Master
    68
    
    Table 2-2. PPC Master Transaction Profiles and Starting Offsets
    69
    
    Table 2-3. PPC Master Write Posting Options
    70
    
    Table 2-4. PPC Master Read Ahead Options
    71
    
    Table 2-5. PPC Master Transfer Types
    72
    
    PPC Arbiter
    73
    
    Table 2-6. PPC Arbiter Pin Assignments
    73
    
    PPC Bus Timer
    75
    
    PPC Parity
    75
  - PCI Bus Interface
    77
    
    PCI Address Mapping
    77
    
    Figure 2-4. PCI to PPC Address Decoding
    78
    
    Figure 2-5. PCI to PPC Address Translation
    79
    
    PCI Slave
    80
    
    Table 2-7. PCI Slave Response Command Types
    81
    
    Pci Fifo
    84
    
    PCI Master
    84
    
    Table 2-8. PCI Master Command Codes
    85
    
    Generating PCI Cycles
    88
    
    Figure 2-6. PCI Spread I/O Address Translation
    89
    
    PCI Arbiter
    92
    
    Table 2-9. PCI Arbiter Pin Description
    92
    
    Table 2-10. Fixed Mode Priority Level Setting
    93
    
    Table 2-11. Mixed Mode Priority Level Setting
    94
    
    Table 2-12. Arbitration Setting
    95
  - Endian Conversion
    96
    
    When PPC Devices Are Big-Endian
    96
    
    Figure 2-7. Big to Little Endian Data Swap
    97
    
    When PPC Devices Are Little Endian
    97
    
    PHB Registers
    98
    
    Table 2-13. Address Modification for Little Endian Transfers
    98
  - Error Handling
    99
  - Watchdog Timers
    100
  - PCI/PPC Contention Handling
    102
  - Table 2-14. Wdtxcntl Programming
    102
  - Transaction Ordering
    105
  - PHB Hardware Configuration
    107
  - Table 2-15. PHB Hardware Configuration
    107
- Multi-Processor Interrupt Controller (MPIC) Functional Description
  108
  - MPIC Features
    108
  - Architecture
    109
  - External Interrupt Interface
    109
  - Csr's Readability
    110
  - Interrupt Source Priority
    110
  - Figure 2-8. Serial Mode Interrupt Scan
    110
  - Processor's Current Task Priority
    111
    
    Interprocessor Interrupts (IPI)
    111
    
    Nesting of Interrupt Events
    111
    
    Spurious Vector Generation
    111
    
    8259 Compatibility
    112
    
    PHB Detected Errors
    112
    
    Interrupt Delivery Modes
    113
    
    Timers
    113
    
    Block Diagram Description
    114
    
    Figure 2-9. MPIC Block Diagram
    115
    
    Interrupt Pending Register (IPR)
    116
    
    Interrupt Selector (IS)
    116
    
    Program Visible Registers
    116
    
    In-Service Register (ISR)
    117
    
    Interrupt Request Register (IRR)
    117
    
    Interrupt Router
    117
    
    External Interrupt Service
    119
    
    Programming Notes
    119
    
    Reset State
    120
    
    Dynamically Changing I/O Interrupt Configuration
    121
    
    EOI Register
    121
    
    Interprocessor Interrupts
    121
    
    Operation
    121
    
    8259 Mode
    122
    
    Architectural Notes
    122
    
    Current Task Priority Level
    122
    
    Interrupt Acknowledge Register
    122
    
    Effects of Interrupt Serialization
    123
  - Registers
    123
    
    PPC Registers
    124
    
    Table 2-16. PPC Register Map for PHB
    125
    
    Vendor ID/Device ID Registers
    125
    
    Revision ID Register
    126
    
    General Control-Status/Feature Registers
    127
    
    PPC Arbiter/Pci Arbiter Control Registers
    129
    
    Hardware Control-Status/Prescaler Adjust Register
    132
    
    PPC Error Test/Error Enable Register
    135
    
    PPC Error Status Register
    137
    
    PPC Error Address Register
    139
    
    PPC Error Attribute Register
    140
    
    PCI Interrupt Acknowledge Register
    141
    
    PPC Slave Address (0,1 and 2) Registers
    142
    
    PPC Slave Offset/Attribute (0, 1 and 2) Registers
    143
    
    PPC Slave Address (3) Register
    144
    
    PPC Slave Offset/Attribute (3) Registers
    145
    
    Wdtxcntl Registers
    146
    
    General Purpose Registers
    148
    
    Wdtxstat Registers
    148
  - PCI Registers
    149
    
    Table 2-17. PCI Configuration Register Map
    150
    
    Table 2-18. PCI I/O Register Map
    150
    
    Vendor ID/ Device ID Registers
    150
    
    PCI Command/Status Registers
    151
    
    Header Type Register
    153
    
    Revision ID/Class Code Registers
    153
    
    MPIC I/O Base Address Register
    154
    
    MPIC Memory Base Register
    155
    
    PCI Slave Address (0,1,2 and 3) Registers
    156
    
    PCI Slave Attribute/Offset (0,1,2 and 3) Registers
    157
    
    CONFIG_ADDRESS Register
    158
    
    CONFIG_DATA Register
    161
  - MPIC Registers
    162
    
    Feature Reporting Register 0
    163
    
    Global Configuration Register 0
    163
    
    Table 2-19. MPIC Register Map
    163
    
    Table 2-20. Cascade Mode Encoding
    167
    
    Table 2-21. Tie Mode Encoding
    167
    
    Processor Init Register
    168
    
    Vendor Identification Register
    168
    
    IPI Vector/Priority Registers
    169
    
    Spurious Vector Register
    170
    
    Timer Frequency Register
    170
    
    Timer Current Count Registers
    171
    
    Timer Basecount Registers
    172
    
    Timer Vector/Priority Registers
    173
    
    External Source Vector/Priority Registers
    174
    
    Timer Destination Registers
    174
    
    External Source Destination Registers
    176
    
    PHB-Detected Errors Vector/Priority Register
    176
    
    PHB-Detected Errors Destination Register
    177
    
    Interprocessor Interrupt Dispatch Registers
    178
    
    Interrupt Task Priority Registers
    178
    
    Interrupt Acknowledge Registers
    179
    
    End-Of-Interrupt Registers
    180
CHAPTER 3 System Memory Controller (SMC)

181
- Introduction
  181
  - Overview
    181
  - System Memory Controller
    181
  - Bit Ordering Convention
    181
  - Features
    181
  - Block Diagrams
    182
  - Figure 3-1. Hawk Used with Synchronous DRAM in a System
    183
  - Figure 3-2. Hawk's System Memory Controller Internal Data Paths
    184
  - Figure 3-3. Overall SDRAM Connections (4 Blocks Using Register Buffers)
    185
  - Functional Description
    186
    
    Figure 3-4. Hawk's System Memory Controller Block Diagram
    186
    
    Four-Beat Reads/Writes
    186
    
    Performance
    186
    
    Address Pipelining
    187
    
    Page Holding
    187
    
    SDRAM Speeds
    187
    
    Single-Beat Reads/Writes
    187
    
    Table 3-1. 60X Bus to SDRAM Estimated Access Timing at 100Mhz with PC100 Sdrams (Cas_Latency of 2)
    188
    
    SDRAM Organization
    189
    
    Rom/Flash Speeds
    190
    
    Responding to Address Transfers
    192
    
    Completing Data Transfers
    193
    
    Ppc60X Address Parity
    193
    
    Ppc60X Data Parity
    193
    
    Cache Coherency
    194
    
    Cache Coherency Restrictions
    194
    
    L2 Cache Support
    194
    
    Cycle Types
    195
    
    Ecc
    195
    
    Error Reporting
    195
    
    Table 3-6. Error Reporting
    196
    
    Error Logging
    197
    
    Rom/Flash Interface
    197
    
    I2C Interface
    201
    
    I2C Byte Write
    202
    
    Figure 3-5. Programming Sequence for I2C Byte Write
    204
    
    I2C Random Read
    205
    
    Figure 3-6. Programming Sequence for I2C Random Read
    206
    
    I2C Current Address Read
    207
    
    Figure 3-7. Programming Sequence for I2C Current Address Read
    208
    
    I2C Page Write
    209
    
    Figure 3-8. Programming Sequence for I2C Page Write
    210
    
    I2C Sequential Read
    211
    
    Figure 3-9. Programming Sequence for I2C Sequential Read
    213
    
    Chip Configuration
    214
    
    CSR Accesses
    214
    
    External Register Set
    214
    
    Refresh/Scrub
    214
  - Programming Model
    215
    
    CSR Architecture
    215
    
    Register Summary
    215
    
    Table 3-9. Register Summary
    216
    
    Detailed Register Bit Descriptions
    218
    
    Vendor/Device Register
    219
    
    Revision ID/ General Control Register
    220
    
    SDRAM Enable and Size Register (Blocks A, B, C, D)
    221
    
    Table 3-10. Block_A/B/C/D/E/F/G/H Configurations
    222
    
    SDRAM Base Address Register (Blocks A/B/C/D)
    223
    
    CLK Frequency Register
    224
    
    ECC Control Register
    225
    
    Figure 3-10. Read/Write Check-Bit Data Paths
    226
    
    Error Logger Register
    229
    
    Error_Address Register
    230
    
    Scrub/Refresh Register
    231
    
    Scrub Address Register
    232
    
    ROM a Base/Size Register
    233
    
    Table 3-11. ROM Block a Size Encoding
    234
    
    Table 3-13. Read/Write to Rom/Flash
    235
    
    ROM B Base/Size Register
    236
    
    ROM Speed Attributes Registers
    238
    
    Table 3-15. ROM Speed Bit Encodings
    238
    
    Data Parity Error Log Register
    239
    
    Data Parity Error Address Register
    240
    
    Data Parity Error Upper Data Register
    240
    
    Data Parity Error Lower Data Register
    241
    
    I2C Clock Prescaler Register
    241
    
    I2C Control Register
    242
    
    I2C Status Register
    243
    
    I2C Transmitter Data Register
    244
    
    I2C Receiver Data Register
    245
    
    SDRAM Enable and Size Register (Blocks E,F,G,H)
    245
    
    SDRAM Base Address Register (Blocks E/F/G/H)
    246
    
    SDRAM Speed Attributes Register
    248
    
    Table 3-16. Trc Encoding
    249
    
    Table 3-17. tras Encoding
    249
    
    Address Parity Error Log Register
    250
    
    32-Bit Counter
    251
    
    Address Parity Error Address Register
    251
    
    External Register Set
    252
    
    Tben Register
    253
- Software Considerations
  254
- ECC Codes
  266
- Table 3-21. Syndrome Codes Ordered by Bit in Error
  266
- Table 3-22. Single Bit Errors Ordered by Syndrome Code
  267
CHAPTER 4 Universe II (Vmebus to PCI) Chip

269
- General Information
  269
  - Introduction
    269
    
    Product Overview - Features
    269
  - Functional Description
    270
    
    Architectural Overview
    270
    
    PCI Bus Interface
    270
    
    Vmebus Interface
    270
    
    Figure 4-1. Architectural Diagram for the Universe II
    271
    
    Interrupter and Interrupt Handler
    271
    
    DMA Controller
    275
  - Registers - Universe II Control and Status Registers (UCSR)
    276
    
    Figure 4-2. UCSR Access Mechanisms
    276
    
    Table 4-1. Universe II Register Map
    277
    
    Universe II Register Map
    277
  - Introduction
    282
  - Table 5-1. Hawk Arbitration Assignments
    282
  - Pci Arbitration
    282
CHAPTER 5 Programming Details

282
- Interrupt Handling
  283
- ISA DMA Channels
  288
- Exceptions
  288
  - Sources of Reset
    288
  - Soft Reset
    289
  - Universe II Chip Problems after a PCI Reset
    289
  - Table 5-4. Reset Sources and Devices Affected
    289
  - Error Notification and Handling
    290
  - Table 5-5. Error Notification and Handling
    290
- Endian Issues
  291
  - Figure 5-3. Big-Endian Mode
    292
  - Figure 5-4. Little-Endian Mode
    293
  - Mpic's Involvement
    294
  - PCI Domain
    294
    
    PCI-Ethernet
    294
    
    Pci-Scsi
    294
    
    PCI-Graphics
    295
  - Processor/Memory Domain
    294
  - Universe II's Involvement
    295
  - Vmebus Domain
    295
- Rom/Flash Initialization
  296
- Table 5-6. ROM/FLASH Bank Default
  296
- Table A-1. VPD Packet Types
  297
APPENDIX A MVME2400 VPD Reference Information

299
- Vital Product Data (VPD) Introduction
  299

Motorola MVME2400 Series Installation And Use Manual (175 pages)

VME Processor Module

Brand: Motorola | Category: Control Unit | Size: 1.81 MB

Table of Contents
7
Overview of Contents
16
Summary of Changes
16
Comments and Suggestions
17
Conventions Used in this Manual
18
CHAPTER 1 Hardware Preparation and Installation

21
CHAPTER 2 Operating Instructions

45
- Overview
  45
- Applying Power
  45
  - Figure 2-1. Ppcbug Firmware System Startup
    46
  - Switches
    47
    
    Abt (S1)
    47
    
    Rst (S2)
    47
  - Front Panel Indicators (DS1 - DS4)
    48
    
    Bfl (Ds1)
    48
    
    Cpu (Ds2)
    48
    
    Pmc2 (Ds3)
    48
    
    Pmc1 (Ds4)
    48
  - 10/100Baset Port
    49
  - DEBUG Port
    49
  - Figure 2-2. Mvme240X DEBUG Port Configuration
    50
  - PMC Slots
    51
    
    PCI MEZZANINE CARD (PMC Slot 1)
    51
    
    PCI MEZZANINE CARD (PMC Slot 2)
    51
- Pmcspan
  52
CHAPTER 3 Functional Description

53
CHAPTER 4 Programming Details

79
- Introduction
  79
- Memory Maps
  79
- Programming Considerations
  82
  - PCI Arbitration
    82
  - Figure 4-1. Vmebus Master Mapping
    83
  - Interrupt Handling
    84
  - Table 4-2. PCI Arbitration Assignments
    84
  - Figure 4-2. Mvme240X Interrupt Architecture
    85
  - DMA Channels
    86
  - Sources of Reset
    86
  - Table 4-3. Classes of Reset and Effectiveness
    87
  - Endian Issues
    88
    
    Processor/Memory Domain
    88
    
    PCI Domain
    88
    
    Vmebus Domain
    89
CHAPTER 5 Ppcbug

91
- Ppcbug Overview
  91
- Ppcbug Basics
  91
  - Memory Requirements
    93
  - Ppcbug Implementation
    93
- MPU, Hardware, and Firmware Initialization
  93
- Using Ppcbug
  95
  - Debugger Commands
    96
  - Table 5-1. Debugger Commands
    97
  - Diagnostic Tests
    101
  - Table 5-2. Diagnostic Test Groups
    102
CHAPTER 6 Environment Modification

103
- Overview
  103
  - CNFG - Configure Board Information Block
    104
  - ENV - Set Environment
    105
    
    Configuring the Ppcbug Parameters
    105
    
    Configuring the Vmebus Interface
    115
APPENDIX A Specifications

121
- Specifications
  121
- Table A-1. Specifications
  121
- Cooling Requirements
  123
- EMC Regulatory Compliance
  124
APPENDIX B Connector Pin Assignments

125
- Introduction
  125
- Pin Assignments
  125
APPENDIX C Troubleshooting

145
- Solving Startup Problems
  145
- Table C-1. Troubleshooting Mvme240X Modules
  145
APPENDIX D Related Documentation

151
- Motorola Computer Group Documents
  151
- Manufacturers' Documents
  152
- Related Specifications
  154

Motorola MVME2400 Series Installation And User Manual (20 pages)

Brand: Motorola | Category: Single board computers | Size: 0.05 MB

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Motorola MVME2400 Series Manuals

Motorola MVME2400 Series Programmer's Reference Manual (331 pages)

Table of Contents

About this Manual

CHAPTER 1 Board Description and Memory Maps

CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

CHAPTER 3 System Memory Controller (SMC)

CHAPTER 4 Universe II (Vmebus to PCI) Chip

CHAPTER 5 Programming Details

APPENDIX A MVME2400 VPD Reference Information

Motorola MVME2400 Series Installation And Use Manual (175 pages)

Table of Contents

CHAPTER 1 Hardware Preparation and Installation

CHAPTER 2 Operating Instructions

CHAPTER 3 Functional Description

CHAPTER 4 Programming Details

CHAPTER 5 Ppcbug

CHAPTER 6 Environment Modification

APPENDIX A Specifications

APPENDIX B Connector Pin Assignments

APPENDIX C Troubleshooting

APPENDIX D Related Documentation

Motorola MVME2400 Series Installation And User Manual (20 pages)

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