Sdram Latency; Table 3-8. 60X Bus To Sdram Access Timing (100 Mhz/Pc100 Sdrams) - Motorola MVME2400 Series Installation And Use Manual

populated for 64MB or 128MB of onboard memory. With 128Mbit (8-bit
data) devices, the blocks can be populated for 128MB and 256MB. If
64Mbit (4-bit data) devices are installed, there is one block consisting of
18 devices that total 128MB. With 128Mbit (4-bit data) devices, the block
contains 256MB. When populated, these blocks appear as Block A and
Block B to the Hawk.
Refer to the MVME2400 Series VME Processor Module Programmer's
Reference Guide for additional information and programming details.

SDRAM Latency

The following table shows the performance summary for SDRAM when
operating at 100 MHz using PC100 SDRAM with a CAS_latency of 2. The
figure on the next page defines the times that are specified in the table.

Table 3-8. 60x Bus to SDRAM Access Timing (100 MHz/PC100 SDRAMs)

ACCESS TYPE
4-Beat Read after idle,
SDRAM Bank Inactive
4-Beat Read after idle,
SDRAM Bank Active - Page Miss
4-Beat Read after idle,
SDRAM Bank Active - Page Hit
4-Beat Read after 4-Beat Read,
SDRAM Bank Active - Page Miss
4-Beat Read after 4-Beat Read,
SDRAM Bank Active - Page Hit
4-Beat Write after idle,
SDRAM Bank Active or Inactive
4-Beat Write after 4-Beat Write,
SDRAM Bank Active - Page Miss
http://www.motorola.com/computer/literature
Access Time
(tB1-tB2-tB3-tB4)
10-1-1-1
12-1-1-1
7-1-1-1
5-1-1-1
2.5-1-1-1
4-1-1-1
6-1-1-1
Block Diagram
Comments
2.5-1-1-1 is an average of 2-
1-1-1 half of the time and 3-
1-1-1 the other half.
3
3-13