Pci Originated; Sdram Memory - Motorola MVME2400 Series Installation And Use Manual

Functional Description
3

PCI Originated

SDRAM Memory

3-12
Default FIFO threshold settings
Single beat writes are aligned 32-bit transfer, always executed as
32-bit PCI.
Clock counts represent best case alignment between PCI and
PPC60x clock domains. An exception to this is continuous
bandwidth which reflects the average affects of clock alignment.
Count represents number of PCI Bus clock cycles.
Assumes write posting FIFO is initially empty
L2 caching is not enabled, all transactions exclusively controlled by
the SMC.
Does not include time taken to obtain grant for PCI Bus. The count
starts on the same clock period that FRAME_ is asserted.
One clock request/one clock grant PPC60x bus arbitration.
PPC60x bus traffic limited to PHB transactions only.
Write posting and read ahead enabled.
Default FIFO threshold settings.
One cache line = 32 bytes.
The MVME2400 SDRAM memory size can be 32MB, 64MB, or 128MB.
The SDRAM blocks are controlled by the Hawk ASIC which provides
single-bit error correction and double-bit error detection. ECC is
calculated over 72-bits.
The memory block size is dependant upon the SDRAM devices installed.
Installing five 64Mbit (16-bit data) devices provides 32MB of memory.
With 64Mbit (8bit data) devices, there are two blocks consisting of nine
devices each that total 64MB per block. In this case, either block can be
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