Start-Up Method (Power-On Sequence) - Epson S5U1C33001H Manual

START-UP METHOD (POWER-ON SEQUENCE)

To start up the S5U1C33001H system, follow the sequence described below:
(1) Turn the S5U1C33001H on.
POWER LED (green)
OK LED (green)
EMU/ERASE LED (red) lit
(2) Turn the target system on.
EMU/ERASE LED (red) goes out
This indicates that the target system was connected correctly.
(3) Start up the debugger (gdb.exe) on the host computer in ICD mode.
To terminate the S5U1C33001H system, follow the sequence described below:
(1') Terminate the debugger (gdb.exe) on the host computer.
(2') Turn the target system off.
(3') Turn the S5U1C33001H off.
Notes: • Normally the S5U1C33001H system can work properly when the target system is turned on first and then
the S5U1C33001H. However, the power-on sequence described above is recommended since the system
may not work properly if the target system is in indeterminate operation or in runaway status.
• If the debugger (gdb.exe) is terminated after the S5U1C33001H is turned off, the debugger may not work
properly with "Cannot open ICD33 usb driver." displayed on the screen when it is re-invoked. In this case,
turn on or reset the S5U1C33001H after terminating the debugger (gdb.exe) once, and then re-invoke the
debugger.
For details on how to invoke/terminate the debugger, refer to the "Debugger" section in the "S5U1C33001C Manual (C
Compiler Package for S1C33 Family)". Furthermore the debugger (gdb.exe) must be invoked after turning all the power of
the system on.
Check the following if the debugger reports a target down error, which means that communication between the
S5U1C33001H and the target system is not functioning.
• If the target system power is turned on after the S5U1C33001H is turned on:
After the S5U1C33001H power is turned on, a forced break will be applied continuously to the target system. After the
target system is turned on, the S1C33xxx chip is reset. The S1C33xxx chip enters debug mode and starts communica-
tion with the S5U1C33001H. If multiple power on/reset cycles occur caused by switch bounce when the target is turned
on, the communication between the S5U1C33001H and the target system may be disconnected after the second reset.
Design the target system so that switch bounce does not occur and the system starts up only once. Furthermore, if the
reset is applied with either the power or the oscillator in an unstable state (for example, if the reset is applied within the
first few ms after the power is turned on), the S1C33xxx chip operation will also be unstable. In this case the system will
not enter debug mode and communication between the S5U1C33001H and the target system will not be possible. Apply
the reset only after an adequate stabilization time has elapsed. Refer to the "S1C33xxx Technical Manual" for more
information on the reset operation.
• If the S5U1C33001H is turned on after the target system power is turned on:
When the S5U1C33001H is turned on, it issues a forcible break to the free-running target system. The S1C33xxx chip
enters debug mode and starts communication with the S5U1C33001H. If a boot program was not loaded into ROM, the
S1C33xxx chip cannot respond to the forced break since the S1C33xxx chip is in the runaway state, so communication
is impossible. Load a boot program that operates correctly into boot ROM so that the target system will not be in the
runaway state.
lit
lit
S5U1C33001H
(Ver. 4)
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