Table of Contents
Advertisement
11-9,
500-1000 MHz Phase Locked Loop.
Tl1e 500-1000 MHz output is locked to ei01er the sum or the
djfference of lhe 310···440 lviHz and 60.5 MHz loop output
ln 1he locked condilion
divide
tvJo
of the 500-·1000 MHz VCO"s with the
310~4,10
MHz
a.
·difference
oqual to the 60.5 tAHz output. There are l'.vo
a.t !he cJivide
cH minus the 60.5
oi :he
is
!fVFJ!'ted for one
r'n"'''"''''
\o the other Thus tile
switcil
will lock.
1·]--10.
Modulation ControL
tv1odulaUon of tho
n:odulation of tile FlJ:
a faclor of two v1hen tht: 250-500
MHz source is selected. the modulation control provides
gain control to maintain constan!
sensitivity at the FM MOD and S\NEEP inputs. Additiona!ly, the wideband modulation mode requires a gain of
four beyond that for the narrowband mode. Thus under the control of the processor the Modulation Control
selects between the SWEEP and FM MOD inputs, provides gains of 1, 2, 4. and 8 for the FM MOD input and
gains of 1 and 2 for the SWEEP input Input modulation sensitivi!es are 5kHz/volt and 20kHz/volt for narrow
and wideband FM input and 2 MHz/volt lor the sweep input
11-11.
Module Control.
Control information is latched in four bit control latches which are loaded by the
processor through the RF control bus. The four bit RF ADD BUS 0-3 is decoded by the Address Decoder to
determine which Control Latch the four bit RF DATA BUS 0-3 is to be stored. Synchronization of the data
[
transfer is the function of the RF BUS EN line. Two decoded address outputs, RF LATCH 13 and 14, select
,
latches on the receiver module lor receiver control. One control latch output, LO/HI BAND SEL, goes to the RF
Input module to control the frequency range of the output ampliler.
11-2
I
Advertisement
Table of Contents
