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SECTION 18
FRONT PANEL INTERFACE MODULE (A12)
18·1. GENERAL. The front panel interface module contains the input buffers for front panel control to the
processor. In addition, buffering and ranging circuits for external scope vertical/horizontal, SINAD, DVM, and
frequency counter inputs are in this module. A block diagram and schematic diagram of the Front Panel
Interface Module is shown in figures 18·1 and 18·2, respectively.
18-2.
Input Coupling and Ranging.
Scope inputs to the Range Attenuator are from the front panel jack (EXT
IN) or from the internal modulation sources (INT SCOPE TO RNG SW). An I NT/EXT relay selects the input
path. The external path may be AC or DC coupled and is also the path for external DVM, Frequency Counter,.
and SINAD inputs.
18·3. Four decades of attenuation from 1.0 to 0.001 are provided by the Range Attenuator. The Input
impedance of the attenuator is 1.0 megohm compensated lor a bandwidth ol1 MHz. A unity gain buffer amp
following the attenuator provides the drive for the DVM, Frequency Counter, and Scope Vertical Preamp
circuits.
18·4.
DVM Buffer.
For DC measurements the DVM Buffer provides a 2-pole low pass filter with a minimum
of 30 dB attenuation at 50 Hz. For AC measurements the bandwidth of the buffer is switched so that the
attenuation at 10 kHz is less than 0.5 dB.
18-5.
Frequency Counter Preamp.
The Frequency Counter Preamp has sufficient gain for 30 mV rms
sensitivity and provides hystersis for noise immunity.
18·6.
Scope Vertical Preamp.
A calibrated gain of 50 or a variable gain from 5 to 50 is provided by the
Vertical Preamp. The gain is controlled from the front panel. From vertical scope positioning the DC bias point
of the preamp is controlled by the front panel position control. Deflection sensitivity at the VERT FROM RNG
SW output is 0.5 volt per division.
18·7.
Scope Horizontal Preamp.
A fixed gain of 5 in the Horizontal Preamp gives a horizontal input
sensitivity of 0.1 volt per division. Horizontal vernier gain is implemented on the front panel, and horizontal
positioning on the Scope Amplifier module. Deflection sensitivity at the HORIZ TO SCOPE AMPL is 0.5 volt
per division.
18-8.
Control and Display Interface.
Front panel control information is input to the processor in 4-bit
groups through the AF control bus. Priority encoders convert the multiposition switch positions (scope
horizontal, frequency scan, and RF step attenuator) to 4-bit codes. The processor sequentially addresses each
input buffer (AF ADRS BUS 0-3) through the Address Decoder. Data in the selected buffer is then transfered to
the processor on the AF DATA BUS 0·3 lines while the AF BUS EN 2 signal is low. Two additional latches
provide the processor control interface for the Range Attenuator, input switching, and DVM Buffer control.
18-9. AF BUS. The AF Bus consists of 4-bit tri-state bus AF DATA BUS 0·3. Individual input/output bus
locations are addressed by AF ADD BUS 0·3. When AF BUS EN 2 is low, the function of the AF DATA BUS lines
are determined by the address present on the AF ADD BUS lines.
18·10.
LED CONTROL.
Control output to the display, function, and modulation mode LEDs is by the AF
BUS addressed 0, 1, and 2, respectively. Latch select outputs LSD, LS1, and LS2are low to latch data present on
the AF DATA BUS when the corresponding address is enabled on the AF ADD BUS. These latch select outputs
and the AF DATA BUS are connected to the LED display board A14A1.
18·1
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