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SECTION 15
PROCESSOR MODULE (A9)
15-1. GENERAL The processor module provides primary control and data manipulations for the system.
This module contains a processor and buffer, a program memory (ROM), a nonvolative memory (NVM), a
random access memory (RAM), a peripheral interface adapter (PIA), a timing generator, and a character
generator. Input and output information is via the peripheral interface adapter and the address, data, and
control buses. A block diagram and a schematic diagram ofthe module is shown in figure 15-1 and figure 15-2,
respectively.
15.2 PROCESSOR AND BUFFER. The processor is a Motorola microprocessor MC6802P, operating at a 1
MHz clock rate. This microprocessor controls the processor module via the three signal buses. The address
bus provides access to the selected device for data transfers (read/write) from the data bus. Synchronization of
the data transfer and specialized processor functions are provided through the control bus.
15-3. PROGRAM MEMORY (ROM). The series of commands (program instructions) that direct
microprocessor action are contained in the ROM (Read Only Memory). This ROM is comprised of three 4096 x
8-bit read only memories. An additional 4096 x 8-bit read only memory is provided with the IEEE option.
15-4. NONVOLATILE MEMORY (NVM). The nonvolatile memory provides storage for 84 eight-bit words.
Data that is to be held during power off is held in the NVM. When the power is turned on, the microprocessor
reads the NVM contents to obtain its start up mode, the RF and tone memory presets, and the remainder of the
preset data. If the operator changes a preset, the microprocessor changes the data in the NVM so that the new
preset will be remembered.
15-5.
RANDOM ACCESS MEMORY (RAM). The random access memory provides temporary storage for
both the processor and the CRT alphanumeric display. The RAM has provision to store 1024 eight-bit words, of
which 512 are used for the CRT display data. Data is written in a read out of the RAM by the microprocessor.
15-6. PERIPHERAL INTERFACE ADAPTER (PIA). The peripheral interface adapter provides input and
output latches for external data from/to the processor module. There are nine inputs from the keyboard, four
column inputs (KYBD COL 0-3), and five row inputs (KYBD ROW 0-4). A single input (IEEE OPT DET) signals
the processor that the IEEE option is installed. The AF BUS EN 1 output signal synchronizes the transfer of
data on the system AF control bus.
15-7. TIMING GENERATOR. The timing generator provides the timing signals for the character generator.
All of the timing signals are synchronized to the 1 MHz master clock signal from the processor. A x2 multiplier
provides a 2 MHz clock to the 8-bit shift register, which in turn provides the dot clock. Additionally, the 2 MHz is
successively divided through a divide-by-eight circuit then through a 12-bit binary counter to provide the
remaining clock requirements.
15-8. CHARACTER GENERATOR. The character generator sequentially accesses that part of the RAM
where character information is stored and causes the respective characters to be displayed on the screen.
Since both the character generator and the processor share the same RAM, the two must be synchronized so
they access the RAM during alternate half cycles of the master clock. The 1 MHz master clock signal, from the
processor is used to synchronize the 2 MHz dot clock.
15-1
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